|
|
@ -149,14 +149,18 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint16_t
|
|
|
|
slot_cfg.idx = msg3_slot.slot_idx();
|
|
|
|
slot_cfg.idx = msg3_slot.slot_idx();
|
|
|
|
for (const dl_sched_rar_info_t& grant : pending_rars) {
|
|
|
|
for (const dl_sched_rar_info_t& grant : pending_rars) {
|
|
|
|
slot_ue& ue = ues[grant.temp_crnti];
|
|
|
|
slot_ue& ue = ues[grant.temp_crnti];
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Allocate Msg3
|
|
|
|
prb_interval msg3_interv{last_msg3, last_msg3 + msg3_nof_prbs};
|
|
|
|
prb_interval msg3_interv{last_msg3, last_msg3 + msg3_nof_prbs};
|
|
|
|
ue.h_ul = ue.harq_ent->find_empty_ul_harq();
|
|
|
|
ue.h_ul = ue.harq_ent->find_empty_ul_harq();
|
|
|
|
bool success = ue.h_ul->new_tx(msg3_slot, msg3_slot, msg3_interv, mcs, 100, max_harq_msg3_retx);
|
|
|
|
bool success = ue.h_ul->new_tx(msg3_slot, msg3_slot, msg3_interv, mcs, 100, max_harq_msg3_retx);
|
|
|
|
srsran_assert(success, "Failed to allocate Msg3");
|
|
|
|
srsran_assert(success, "Failed to allocate Msg3");
|
|
|
|
last_msg3 += msg3_nof_prbs;
|
|
|
|
last_msg3 += msg3_nof_prbs;
|
|
|
|
pdcch_ul_t msg3_pdcch;
|
|
|
|
pdcch_ul_t msg3_pdcch; // dummy PDCCH for retx=0
|
|
|
|
fill_dci_msg3(ue, *bwp_grid.cfg, msg3_pdcch.dci);
|
|
|
|
fill_dci_msg3(ue, *bwp_grid.cfg, msg3_pdcch.dci);
|
|
|
|
msg3_pdcch.dci.time_domain_assigment = dai++;
|
|
|
|
msg3_pdcch.dci.time_domain_assigment = dai++;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Generate PUSCH
|
|
|
|
bwp_msg3_slot.puschs.emplace_back();
|
|
|
|
bwp_msg3_slot.puschs.emplace_back();
|
|
|
|
pusch_t& pusch = bwp_msg3_slot.puschs.back();
|
|
|
|
pusch_t& pusch = bwp_msg3_slot.puschs.back();
|
|
|
|
success = ue.cfg->phy().get_pusch_cfg(slot_cfg, msg3_pdcch.dci, pusch.sch);
|
|
|
|
success = ue.cfg->phy().get_pusch_cfg(slot_cfg, msg3_pdcch.dci, pusch.sch);
|
|
|
|