From d8d99054d57d6e0f33d8af879b5835c2daa50c78 Mon Sep 17 00:00:00 2001 From: Francisco Paisana Date: Mon, 23 Aug 2021 11:21:21 +0200 Subject: [PATCH] sched,nr: fix RAR encoding in NR scheduler --- srsenb/src/stack/mac/nr/sched_nr_grant_allocator.cc | 8 ++++++-- srsenb/src/stack/mac/nr/sched_nr_helpers.cc | 4 ++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/srsenb/src/stack/mac/nr/sched_nr_grant_allocator.cc b/srsenb/src/stack/mac/nr/sched_nr_grant_allocator.cc index 76fc2ef23..d7bb85c80 100644 --- a/srsenb/src/stack/mac/nr/sched_nr_grant_allocator.cc +++ b/srsenb/src/stack/mac/nr/sched_nr_grant_allocator.cc @@ -148,15 +148,19 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint16_t srsran_slot_cfg_t slot_cfg; slot_cfg.idx = msg3_slot.slot_idx(); for (const dl_sched_rar_info_t& grant : pending_rars) { - slot_ue& ue = ues[grant.temp_crnti]; + slot_ue& ue = ues[grant.temp_crnti]; + + // Allocate Msg3 prb_interval msg3_interv{last_msg3, last_msg3 + msg3_nof_prbs}; ue.h_ul = ue.harq_ent->find_empty_ul_harq(); bool success = ue.h_ul->new_tx(msg3_slot, msg3_slot, msg3_interv, mcs, 100, max_harq_msg3_retx); srsran_assert(success, "Failed to allocate Msg3"); last_msg3 += msg3_nof_prbs; - pdcch_ul_t msg3_pdcch; + pdcch_ul_t msg3_pdcch; // dummy PDCCH for retx=0 fill_dci_msg3(ue, *bwp_grid.cfg, msg3_pdcch.dci); msg3_pdcch.dci.time_domain_assigment = dai++; + + // Generate PUSCH bwp_msg3_slot.puschs.emplace_back(); pusch_t& pusch = bwp_msg3_slot.puschs.back(); success = ue.cfg->phy().get_pusch_cfg(slot_cfg, msg3_pdcch.dci, pusch.sch); diff --git a/srsenb/src/stack/mac/nr/sched_nr_helpers.cc b/srsenb/src/stack/mac/nr/sched_nr_helpers.cc index af7e02ac2..0474272be 100644 --- a/srsenb/src/stack/mac/nr/sched_nr_helpers.cc +++ b/srsenb/src/stack/mac/nr/sched_nr_helpers.cc @@ -48,7 +48,7 @@ void fill_dci_common(const slot_ue& ue, const bwp_params& bwp_cfg, DciDlOrUl& dc bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params& bwp_cfg, srsran_dci_dl_nr_t& dci) { dci.mcs = 5; - dci.ctx.format = srsran_dci_format_nr_rar; + dci.ctx.format = srsran_dci_format_nr_1_0; dci.ctx.ss_type = srsran_search_space_type_rar; dci.ctx.rnti_type = srsran_rnti_type_ra; dci.ctx.rnti = ra_rnti; @@ -61,6 +61,7 @@ bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params& bwp_c bool fill_dci_msg3(const slot_ue& ue, const bwp_params& bwp_cfg, srsran_dci_ul_nr_t& msg3_dci) { + fill_dci_common(ue, bwp_cfg, msg3_dci); msg3_dci.ctx.coreset_id = ue.cfg->phy().pdcch.ra_search_space.coreset_id; msg3_dci.ctx.rnti_type = srsran_rnti_type_tc; msg3_dci.ctx.rnti = ue.rnti; @@ -70,7 +71,6 @@ bool fill_dci_msg3(const slot_ue& ue, const bwp_params& bwp_cfg, srsran_dci_ul_n } else { msg3_dci.ctx.format = srsran_dci_format_nr_0_0; } - fill_dci_common(ue, bwp_cfg, msg3_dci); return true; }