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@ -4,28 +4,7 @@
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/* ——————————————————————- */
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/* ——————————————————————- */
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/* the state registers of LFSR */
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/* the state registers of LFSR */
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u32 ZUC_LFSR_S0 = 0x00;
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u32 ZUC_LFSR_S1 = 0x00;
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u32 ZUC_LFSR_S2 = 0x00;
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u32 ZUC_LFSR_S3 = 0x00;
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u32 ZUC_LFSR_S4 = 0x00;
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u32 ZUC_LFSR_S5 = 0x00;
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u32 ZUC_LFSR_S6 = 0x00;
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u32 ZUC_LFSR_S7 = 0x00;
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u32 ZUC_LFSR_S8 = 0x00;
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u32 ZUC_LFSR_S9 = 0x00;
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u32 ZUC_LFSR_S10 = 0x00;
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u32 ZUC_LFSR_S11 = 0x00;
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u32 ZUC_LFSR_S12 = 0x00;
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u32 ZUC_LFSR_S13 = 0x00;
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u32 ZUC_LFSR_S14 = 0x00;
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u32 ZUC_LFSR_S15 = 0x00; /* the registers of F */
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u32 F_R1 = 0x00;
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u32 F_R2 = 0x00;/* the outputs of BitReorganization */
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u32 BRC_X0 = 0x00;
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u32 BRC_X1 = 0x00;
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u32 BRC_X2 = 0x00;
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u32 BRC_X3 = 0x00;
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#define MAKEU32(a, b, c, d) (((u32)(a) << 24) | ((u32)(b) << 16) | ((u32)(c) << 8) | ((u32)(d)))
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#define MAKEU32(a, b, c, d) (((u32)(a) << 24) | ((u32)(b) << 16) | ((u32)(c) << 8) | ((u32)(d)))
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#define MulByPow2(x, k) ((((x) << k) | ((x) >> (31 - k))) & 0x7FFFFFFF)
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#define MulByPow2(x, k) ((((x) << k) | ((x) >> (31 - k))) & 0x7FFFFFFF)
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@ -75,79 +54,80 @@ u32 AddM(u32 a, u32 b)
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u32 c = a + b;
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u32 c = a + b;
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return (c & 0x7FFFFFFF) + (c >> 31);
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return (c & 0x7FFFFFFF) + (c >> 31);
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}
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}
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/* LFSR with initialization mode */
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/* LFSR with initialization mode */
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void LFSRWithInitialisationMode(u32 u)
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void LFSRWithInitialisationMode(zuc_state_t * state, u32 u)
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{
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{
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u32 f, v;
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u32 f, v;
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f = ZUC_LFSR_S0;
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f = state->LFSR_S0;
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v = MulByPow2(ZUC_LFSR_S0, 8);
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v = MulByPow2(state->LFSR_S0, 8);
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f = AddM(f, v);
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f = AddM(f, v);
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v = MulByPow2(ZUC_LFSR_S4, 20);
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v = MulByPow2(state->LFSR_S4, 20);
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f = AddM(f, v);
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f = AddM(f, v);
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v = MulByPow2(ZUC_LFSR_S10, 21);
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v = MulByPow2(state->LFSR_S10, 21);
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f = AddM(f, v);
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f = AddM(f, v);
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v = MulByPow2(ZUC_LFSR_S13, 17);
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v = MulByPow2(state->LFSR_S13, 17);
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f = AddM(f, v);
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f = AddM(f, v);
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v = MulByPow2(ZUC_LFSR_S15, 15);
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v = MulByPow2(state->LFSR_S15, 15);
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f = AddM(f, v);
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f = AddM(f, v);
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f = AddM(f, u); /* update the state */
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f = AddM(f, u); /* update the state */
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ZUC_LFSR_S0 = ZUC_LFSR_S1;
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state->LFSR_S0 = state->LFSR_S1;
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ZUC_LFSR_S1 = ZUC_LFSR_S2;
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state->LFSR_S1 = state->LFSR_S2;
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ZUC_LFSR_S2 = ZUC_LFSR_S3;
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state->LFSR_S2 = state->LFSR_S3;
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ZUC_LFSR_S3 = ZUC_LFSR_S4;
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state->LFSR_S3 = state->LFSR_S4;
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ZUC_LFSR_S4 = ZUC_LFSR_S5;
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state->LFSR_S4 = state->LFSR_S5;
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ZUC_LFSR_S5 = ZUC_LFSR_S6;
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state->LFSR_S5 = state->LFSR_S6;
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ZUC_LFSR_S6 = ZUC_LFSR_S7;
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state->LFSR_S6 = state->LFSR_S7;
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ZUC_LFSR_S7 = ZUC_LFSR_S8;
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state->LFSR_S7 = state->LFSR_S8;
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ZUC_LFSR_S8 = ZUC_LFSR_S9;
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state->LFSR_S8 = state->LFSR_S9;
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ZUC_LFSR_S9 = ZUC_LFSR_S10;
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state->LFSR_S9 = state->LFSR_S10;
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ZUC_LFSR_S10 = ZUC_LFSR_S11;
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state->LFSR_S10 = state->LFSR_S11;
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ZUC_LFSR_S11 = ZUC_LFSR_S12;
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state->LFSR_S11 = state->LFSR_S12;
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ZUC_LFSR_S12 = ZUC_LFSR_S13;
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state->LFSR_S12 = state->LFSR_S13;
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ZUC_LFSR_S13 = ZUC_LFSR_S14;
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state->LFSR_S13 = state->LFSR_S14;
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ZUC_LFSR_S14 = ZUC_LFSR_S15;
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state->LFSR_S14 = state->LFSR_S15;
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ZUC_LFSR_S15 = f;
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state->LFSR_S15 = f;
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} /* LFSR with work mode */
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} /* LFSR with work mode */
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void LFSRWithWorkMode()
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void LFSRWithWorkMode(zuc_state_t *state)
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{
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{
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u32 f, v;
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u32 f, v;
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f = ZUC_LFSR_S0;
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f = state->LFSR_S0;
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v = MulByPow2(ZUC_LFSR_S0, 8);
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v = MulByPow2(state->LFSR_S0, 8);
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f = AddM(f, v);
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f = AddM(f, v);
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v = MulByPow2(ZUC_LFSR_S4, 20);
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v = MulByPow2(state->LFSR_S4, 20);
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f = AddM(f, v);
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f = AddM(f, v);
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v = MulByPow2(ZUC_LFSR_S10, 21);
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v = MulByPow2(state->LFSR_S10, 21);
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f = AddM(f, v);
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f = AddM(f, v);
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v = MulByPow2(ZUC_LFSR_S13, 17);
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v = MulByPow2(state->LFSR_S13, 17);
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f = AddM(f, v);
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f = AddM(f, v);
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v = MulByPow2(ZUC_LFSR_S15, 15);
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v = MulByPow2(state->LFSR_S15, 15);
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f = AddM(f, v); /* update the state */
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f = AddM(f, v); /* update the state */
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ZUC_LFSR_S0 = ZUC_LFSR_S1;
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state->LFSR_S0 = state->LFSR_S1;
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ZUC_LFSR_S1 = ZUC_LFSR_S2;
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state->LFSR_S1 = state->LFSR_S2;
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ZUC_LFSR_S2 = ZUC_LFSR_S3;
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state->LFSR_S2 = state->LFSR_S3;
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ZUC_LFSR_S3 = ZUC_LFSR_S4;
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state->LFSR_S3 = state->LFSR_S4;
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ZUC_LFSR_S4 = ZUC_LFSR_S5;
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state->LFSR_S4 = state->LFSR_S5;
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ZUC_LFSR_S5 = ZUC_LFSR_S6;
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state->LFSR_S5 = state->LFSR_S6;
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ZUC_LFSR_S6 = ZUC_LFSR_S7;
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state->LFSR_S6 = state->LFSR_S7;
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ZUC_LFSR_S7 = ZUC_LFSR_S8;
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state->LFSR_S7 = state->LFSR_S8;
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ZUC_LFSR_S8 = ZUC_LFSR_S9;
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state->LFSR_S8 = state->LFSR_S9;
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ZUC_LFSR_S9 = ZUC_LFSR_S10;
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state->LFSR_S9 = state->LFSR_S10;
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ZUC_LFSR_S10 = ZUC_LFSR_S11;
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state->LFSR_S10 = state->LFSR_S11;
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ZUC_LFSR_S11 = ZUC_LFSR_S12;
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state->LFSR_S11 = state->LFSR_S12;
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ZUC_LFSR_S12 = ZUC_LFSR_S13;
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state->LFSR_S12 = state->LFSR_S13;
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ZUC_LFSR_S13 = ZUC_LFSR_S14;
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state->LFSR_S13 = state->LFSR_S14;
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ZUC_LFSR_S14 = ZUC_LFSR_S15;
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state->LFSR_S14 = state->LFSR_S15;
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ZUC_LFSR_S15 = f;
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state->LFSR_S15 = f;
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}
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}
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/* BitReorganization */
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/* BitReorganization */
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void BitReorganization()
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void BitReorganization(zuc_state_t *state)
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{
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{
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BRC_X0 = ((ZUC_LFSR_S15 & 0x7FFF8000) << 1) | (ZUC_LFSR_S14 & 0xFFFF);
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state->BRC_X0 = ((state->LFSR_S15 & 0x7FFF8000) << 1) | (state->LFSR_S14 & 0xFFFF);
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BRC_X1 = ((ZUC_LFSR_S11 & 0xFFFF) << 16) | (ZUC_LFSR_S9 >> 15);
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state->BRC_X1 = ((state->LFSR_S11 & 0xFFFF) << 16) | (state->LFSR_S9 >> 15);
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BRC_X2 = ((ZUC_LFSR_S7 & 0xFFFF) << 16) | (ZUC_LFSR_S5 >> 15);
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state->BRC_X2 = ((state->LFSR_S7 & 0xFFFF) << 16) | (state->LFSR_S5 >> 15);
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BRC_X3 = ((ZUC_LFSR_S2 & 0xFFFF) << 16) | (ZUC_LFSR_S0 >> 15);
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state->BRC_X3 = ((state->LFSR_S2 & 0xFFFF) << 16) | (state->LFSR_S0 >> 15);
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}
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}
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/* L1 */
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/* L1 */
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@ -162,62 +142,64 @@ u32 L2(u32 X)
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}
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}
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/* F */
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/* F */
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u32 F()
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u32 F(zuc_state_t *state)
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{
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{
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u32 W, W1, W2, u, v;
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u32 W, W1, W2, u, v;
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W = (BRC_X0 ^ F_R1) + F_R2;
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W = (state->BRC_X0 ^ state->F_R1) + state->F_R2;
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W1 = F_R1 + BRC_X1;
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W1 = state->F_R1 + state->BRC_X1;
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W2 = F_R2 ^ BRC_X2;
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W2 = state->F_R2 ^ state->BRC_X2;
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u = L1((W1 << 16) | (W2 >> 16));
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u = L1((W1 << 16) | (W2 >> 16));
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v = L2((W2 << 16) | (W1 >> 16));
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v = L2((W2 << 16) | (W1 >> 16));
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F_R1 = MAKEU32(S0[u >> 24], S1[(u >> 16) & 0xFF], S0[(u >> 8) & 0xFF], S1[u & 0xFF]);
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state->F_R1 = MAKEU32(S0[u >> 24], S1[(u >> 16) & 0xFF], S0[(u >> 8) & 0xFF], S1[u & 0xFF]);
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F_R2 = MAKEU32(S0[v >> 24], S1[(v >> 16) & 0xFF], S0[(v >> 8) & 0xFF], S1[v & 0xFF]);
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state->F_R2 = MAKEU32(S0[v >> 24], S1[(v >> 16) & 0xFF], S0[(v >> 8) & 0xFF], S1[v & 0xFF]);
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return W;
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return W;
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}
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}
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/* initialize */
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/* initialize */
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void zuc_initialize(u8* k, u8* iv)
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void zuc_initialize(zuc_state_t *state, u8* k, u8* iv)
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{
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{
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u32 w, nCount; /* expand key */
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u32 w, nCount;
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ZUC_LFSR_S0 = MAKEU31(k[0], EK_d[0], iv[0]);
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/* expand key */
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ZUC_LFSR_S1 = MAKEU31(k[1], EK_d[1], iv[1]);
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state->LFSR_S0 = MAKEU31(k[0], EK_d[0], iv[0]);
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ZUC_LFSR_S2 = MAKEU31(k[2], EK_d[2], iv[2]);
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state->LFSR_S1 = MAKEU31(k[1], EK_d[1], iv[1]);
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ZUC_LFSR_S3 = MAKEU31(k[3], EK_d[3], iv[3]);
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state->LFSR_S2 = MAKEU31(k[2], EK_d[2], iv[2]);
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ZUC_LFSR_S4 = MAKEU31(k[4], EK_d[4], iv[4]);
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state->LFSR_S3 = MAKEU31(k[3], EK_d[3], iv[3]);
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ZUC_LFSR_S5 = MAKEU31(k[5], EK_d[5], iv[5]);
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state->LFSR_S4 = MAKEU31(k[4], EK_d[4], iv[4]);
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ZUC_LFSR_S6 = MAKEU31(k[6], EK_d[6], iv[6]);
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state->LFSR_S5 = MAKEU31(k[5], EK_d[5], iv[5]);
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ZUC_LFSR_S7 = MAKEU31(k[7], EK_d[7], iv[7]);
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state->LFSR_S6 = MAKEU31(k[6], EK_d[6], iv[6]);
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ZUC_LFSR_S8 = MAKEU31(k[8], EK_d[8], iv[8]);
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state->LFSR_S7 = MAKEU31(k[7], EK_d[7], iv[7]);
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ZUC_LFSR_S9 = MAKEU31(k[9], EK_d[9], iv[9]);
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state->LFSR_S8 = MAKEU31(k[8], EK_d[8], iv[8]);
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ZUC_LFSR_S10 = MAKEU31(k[10], EK_d[10], iv[10]);
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state->LFSR_S9 = MAKEU31(k[9], EK_d[9], iv[9]);
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ZUC_LFSR_S11 = MAKEU31(k[11], EK_d[11], iv[11]);
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state->LFSR_S10 = MAKEU31(k[10], EK_d[10], iv[10]);
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ZUC_LFSR_S12 = MAKEU31(k[12], EK_d[12], iv[12]);
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state->LFSR_S11 = MAKEU31(k[11], EK_d[11], iv[11]);
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ZUC_LFSR_S13 = MAKEU31(k[13], EK_d[13], iv[13]);
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state->LFSR_S12 = MAKEU31(k[12], EK_d[12], iv[12]);
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ZUC_LFSR_S14 = MAKEU31(k[14], EK_d[14], iv[14]);
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state->LFSR_S13 = MAKEU31(k[13], EK_d[13], iv[13]);
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ZUC_LFSR_S15 = MAKEU31(k[15], EK_d[15], iv[15]); /* set F_R1 and F_R2 to zero */
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state->LFSR_S14 = MAKEU31(k[14], EK_d[14], iv[14]);
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F_R1 = 0;
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state->LFSR_S15 = MAKEU31(k[15], EK_d[15], iv[15]);
|
|
|
|
F_R2 = 0;
|
|
|
|
/* set F_R1 and F_R2 to zero */
|
|
|
|
|
|
|
|
state->F_R1 = 0;
|
|
|
|
|
|
|
|
state->F_R2 = 0;
|
|
|
|
nCount = 32;
|
|
|
|
nCount = 32;
|
|
|
|
while (nCount > 0) {
|
|
|
|
while (nCount > 0) {
|
|
|
|
BitReorganization();
|
|
|
|
BitReorganization(state);
|
|
|
|
w = F();
|
|
|
|
w = F(state);
|
|
|
|
LFSRWithInitialisationMode(w >> 1);
|
|
|
|
LFSRWithInitialisationMode(state, w >> 1);
|
|
|
|
nCount--;
|
|
|
|
nCount--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void zuc_generate_keystream(int KeystreamLen, u32* pKeystream)
|
|
|
|
void zuc_generate_keystream(zuc_state_t *state, int key_stream_len, u32* p_keystream)
|
|
|
|
{
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
int i;
|
|
|
|
{
|
|
|
|
{
|
|
|
|
BitReorganization();
|
|
|
|
BitReorganization(state);
|
|
|
|
F(); /* discard the output of F */
|
|
|
|
F(state); /* discard the output of F */
|
|
|
|
LFSRWithWorkMode();
|
|
|
|
LFSRWithWorkMode(state);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
for (i = 0; i < KeystreamLen; i++) {
|
|
|
|
for (i = 0; i < key_stream_len; i++) {
|
|
|
|
BitReorganization();
|
|
|
|
BitReorganization(state);
|
|
|
|
pKeystream[i] = F() ^ BRC_X3;
|
|
|
|
p_keystream[i] = F(state) ^ state->BRC_X3;
|
|
|
|
LFSRWithWorkMode();
|
|
|
|
LFSRWithWorkMode(state);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|