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sched,nr: extend coreset pdcch allocation to UL

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master
Francisco Paisana 4 years ago
parent 5d034b067e
commit f87f898641
11 changed files with 174 additions and 113 deletions
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1
srsenb/hdr/stack/mac/nr/sched_nr.h
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@ -50,6 +50,7 @@ private:
// args // args
sched_nr_impl::sched_params cfg; sched_nr_impl::sched_params cfg;
srslog::basic_logger& logger;
using sched_worker_manager = sched_nr_impl::sched_worker_manager; using sched_worker_manager = sched_nr_impl::sched_worker_manager;
std::unique_ptr<sched_worker_manager> sched_workers; std::unique_ptr<sched_worker_manager> sched_workers;

13
srsenb/hdr/stack/mac/nr/sched_nr_interface.h
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@ -15,6 +15,7 @@
#include "srsran/adt/bounded_bitset.h" #include "srsran/adt/bounded_bitset.h"
#include "srsran/adt/bounded_vector.h" #include "srsran/adt/bounded_vector.h"
#include "srsran/adt/optional.h"
#include "srsran/adt/span.h" #include "srsran/adt/span.h"
#include "srsran/common/phy_cfg_nr.h" #include "srsran/common/phy_cfg_nr.h"
#include "srsran/common/tti_point.h" #include "srsran/common/tti_point.h"
@ -51,8 +52,11 @@ public:
using pusch_td_res_alloc_list = srsran::bounded_vector<pusch_td_res_alloc, SCHED_NR_MAX_UL_ALLOCS>; using pusch_td_res_alloc_list = srsran::bounded_vector<pusch_td_res_alloc, SCHED_NR_MAX_UL_ALLOCS>;
struct bwp_cfg_t { struct bwp_cfg_t {
uint32_t bwp_id = 1;
uint32_t start_rb = 0; uint32_t start_rb = 0;
uint32_t rb_width = 100; uint32_t rb_width = 100;
std::array<srsran::optional<srsran_coreset_t>, SRSRAN_UE_DL_NR_MAX_NOF_CORESET> coresets;
}; };
struct cell_cfg_t { struct cell_cfg_t {
@ -97,15 +101,14 @@ public:
pdsch_list_t pdschs; pdsch_list_t pdschs;
}; };
struct pusch_grant { struct pusch_t {
srsran_dci_ul_nr_t dci; srsran_sch_cfg_nr_t sch = {}; ///< PUSCH configuration
rbg_bitmap bitmap;
}; };
using pusch_list = srsran::bounded_vector<pusch_grant, SCHED_NR_MAX_PDSCH_DATA>; using pusch_list_t = srsran::bounded_vector<pusch_t, SCHED_NR_MAX_PDSCH_DATA>;
struct ul_tti_request_t { struct ul_tti_request_t {
tti_point pusch_tti; tti_point pusch_tti;
srsran::bounded_vector<pusch_grant, SCHED_NR_MAX_UL_ALLOCS> pusch; srsran::bounded_vector<pusch_t, SCHED_NR_MAX_UL_ALLOCS> pusch;
}; };
struct tti_request_t { struct tti_request_t {

24
srsenb/hdr/stack/mac/nr/sched_nr_pdcch.h
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@ -29,6 +29,7 @@ enum class pdcch_grant_type_t { sib, dl_data, ul_data };
class slot_ue; class slot_ue;
using bwp_cfg_t = sched_nr_interface::bwp_cfg_t;
using pdcch_dl_t = sched_nr_interface::pdcch_dl_t; using pdcch_dl_t = sched_nr_interface::pdcch_dl_t;
using pdcch_dl_list_t = sched_nr_interface::pdcch_dl_list_t; using pdcch_dl_list_t = sched_nr_interface::pdcch_dl_list_t;
using pdcch_ul_t = sched_nr_interface::pdcch_ul_t; using pdcch_ul_t = sched_nr_interface::pdcch_ul_t;
@ -37,11 +38,11 @@ using pdcch_ul_list_t = sched_nr_interface::pdcch_ul_list_t;
class coreset_region class coreset_region
{ {
public: public:
coreset_region(uint32_t bwp_id_, coreset_region(const bwp_cfg_t& bwp_cfg_,
uint32_t coreset_id_,
uint32_t slot_idx, uint32_t slot_idx,
uint32_t nof_td_symbols, pdcch_dl_list_t& pdcch_dl_list,
uint32_t nof_freq_resources, pdcch_ul_list_t& pdcch_ul_list);
pdcch_dl_list_t& pdcch_list);
void reset(); void reset();
/** /**
@ -51,24 +52,24 @@ public:
* @param user UE object or null in case of broadcast/RAR/paging allocation * @param user UE object or null in case of broadcast/RAR/paging allocation
* @return if the allocation was successful * @return if the allocation was successful
*/ */
bool alloc_dci(pdcch_grant_type_t alloc_type, uint32_t aggr_idx, uint32_t coreset_id, slot_ue* user = nullptr); bool alloc_dci(pdcch_grant_type_t alloc_type, uint32_t aggr_idx, slot_ue* user = nullptr);
void rem_last_dci(); void rem_last_dci();
uint32_t get_td_symbols() const { return nof_symbols; } uint32_t get_td_symbols() const { return coreset_cfg->duration; }
uint32_t get_freq_resources() const { return nof_freq_res; } uint32_t get_freq_resources() const { return nof_freq_res; }
uint32_t nof_cces() const { return nof_freq_res * nof_symbols; } uint32_t nof_cces() const { return nof_freq_res * get_td_symbols(); }
size_t nof_allocs() const { return dfs_tree.size(); } size_t nof_allocs() const { return dfs_tree.size(); }
private: private:
uint32_t bwp_id; const bwp_cfg_t* bwp_cfg;
const srsran_coreset_t* coreset_cfg;
uint32_t coreset_id;
uint32_t slot_idx; uint32_t slot_idx;
uint32_t nof_symbols; uint32_t nof_freq_res = 0;
uint32_t nof_freq_res;
// List of PDCCH grants // List of PDCCH grants
struct alloc_record { struct alloc_record {
uint32_t coreset_id;
uint32_t aggr_idx; uint32_t aggr_idx;
uint32_t idx; uint32_t idx;
pdcch_grant_type_t alloc_type; pdcch_grant_type_t alloc_type;
@ -76,6 +77,7 @@ private:
}; };
srsran::bounded_vector<alloc_record, MAX_GRANTS> dci_list; srsran::bounded_vector<alloc_record, MAX_GRANTS> dci_list;
pdcch_dl_list_t& pdcch_dl_list; pdcch_dl_list_t& pdcch_dl_list;
pdcch_ul_list_t& pdcch_ul_list;
// DFS decision tree of PDCCH grants // DFS decision tree of PDCCH grants
struct tree_node { struct tree_node {

4
srsenb/hdr/stack/mac/nr/sched_nr_phy_helpers.h
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@ -26,6 +26,10 @@ void bitmap_to_prb_array(const rbgmask_t& bitmap, uint32_t bwp_nof_prb, srsran_s
class slot_ue; class slot_ue;
void fill_dci_ue_cfg(const slot_ue& ue, srsran_dci_dl_nr_t& dci); void fill_dci_ue_cfg(const slot_ue& ue, srsran_dci_dl_nr_t& dci);
void fill_dci_ue_cfg(const slot_ue& ue, srsran_dci_ul_nr_t& dci); void fill_dci_ue_cfg(const slot_ue& ue, srsran_dci_ul_nr_t& dci);
void fill_sch_ue(const slot_ue& ue,
const rbgmask_t& rbgmask,
const sched_cell_params& cc_cfg,
srsran_sch_cfg_nr_t& sch);
} // namespace sched_nr_impl } // namespace sched_nr_impl
} // namespace srsenb } // namespace srsenb

5
srsenb/hdr/stack/mac/nr/sched_nr_rb_grid.h
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@ -28,7 +28,7 @@ using pusch_bitmap = srsran::bounded_bitset<25, true>;
using pdsch_t = sched_nr_interface::pdsch_t; using pdsch_t = sched_nr_interface::pdsch_t;
using pdsch_list_t = sched_nr_interface::pdsch_list_t; using pdsch_list_t = sched_nr_interface::pdsch_list_t;
using pusch_list = sched_nr_interface::pusch_list; using pusch_list = sched_nr_interface::pusch_list_t;
struct pucch_t {}; struct pucch_t {};
@ -36,6 +36,7 @@ const static size_t MAX_CORESET_PER_BWP = 3;
using slot_coreset_list = srsran::bounded_vector<coreset_region, MAX_CORESET_PER_BWP>; using slot_coreset_list = srsran::bounded_vector<coreset_region, MAX_CORESET_PER_BWP>;
struct bwp_slot_grid { struct bwp_slot_grid {
uint32_t bwp_id;
pdcch_dl_list_t pdcch_dl_list; pdcch_dl_list_t pdcch_dl_list;
pdcch_ul_list_t pdcch_ul_list; pdcch_ul_list_t pdcch_ul_list;
slot_coreset_list coresets; slot_coreset_list coresets;
@ -57,6 +58,8 @@ struct bwp_res_grid {
const bwp_slot_grid& operator[](tti_point tti) const { return slots[tti.sf_idx()]; }; const bwp_slot_grid& operator[](tti_point tti) const { return slots[tti.sf_idx()]; };
uint32_t id() const { return bwp_id; } uint32_t id() const { return bwp_id; }
uint32_t nof_prbs() const { return cell_cfg->cell_cfg.nof_prb; } uint32_t nof_prbs() const { return cell_cfg->cell_cfg.nof_prb; }
const sched_cell_params& cell_params() const { return *cell_cfg; }
const bwp_cfg_t& bwp_cfg() const { return cell_cfg->cell_cfg.bwps[id() - 1]; }
private: private:
uint32_t bwp_id; uint32_t bwp_id;

22
srsenb/src/stack/mac/nr/sched_nr.cc
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@ -81,7 +81,9 @@ private:
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
sched_nr::sched_nr(const sched_cfg_t& sched_cfg) : cfg(sched_cfg), pending_events(new ue_event_manager(ue_db)) {} sched_nr::sched_nr(const sched_cfg_t& sched_cfg) :
cfg(sched_cfg), pending_events(new ue_event_manager(ue_db)), logger(srslog::fetch_basic_logger("MAC"))
{}
sched_nr::~sched_nr() {} sched_nr::~sched_nr() {}
@ -156,15 +158,21 @@ void sched_nr::ul_sr_info(tti_point tti_rx, uint16_t rnti)
}); });
} }
#define VERIFY_INPUT(cond, msg, ...) \
do { \
if (not(cond)) { \
srslog::fetch_basic_logger("MAC").warning(msg, ##__VA_ARGS__); \
return SRSRAN_ERROR; \
} \
} while (0)
int assert_ue_cfg_valid(uint16_t rnti, const sched_nr_interface::ue_cfg_t& uecfg) int assert_ue_cfg_valid(uint16_t rnti, const sched_nr_interface::ue_cfg_t& uecfg)
{ {
const srslog::basic_logger& logger = srslog::fetch_basic_logger("MAC"); VERIFY_INPUT(std::count(&uecfg.phy_cfg.pdcch.coreset_present[0],
if (std::count(&uecfg.phy_cfg.pdcch.coreset_present[0],
&uecfg.phy_cfg.pdcch.coreset_present[SRSRAN_UE_DL_NR_MAX_NOF_CORESET], &uecfg.phy_cfg.pdcch.coreset_present[SRSRAN_UE_DL_NR_MAX_NOF_CORESET],
true) == 0) { true) > 0,
logger.warning("Provided rnti=0x%x configuration does not contain any coreset", rnti); "Provided rnti=0x%x configuration does not contain any coreset",
return SRSRAN_ERROR; rnti);
}
return SRSRAN_SUCCESS; return SRSRAN_SUCCESS;
} }

53
srsenb/src/stack/mac/nr/sched_nr_pdcch.cc
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@ -16,22 +16,22 @@
namespace srsenb { namespace srsenb {
namespace sched_nr_impl { namespace sched_nr_impl {
coreset_region::coreset_region(uint32_t bwp_id_, coreset_region::coreset_region(const bwp_cfg_t& bwp_cfg_,
uint32_t coreset_id_,
uint32_t slot_idx_, uint32_t slot_idx_,
uint32_t nof_td_symbols, pdcch_dl_list_t& pdcch_dl_list_,
uint32_t nof_freq_resources, pdcch_ul_list_t& pdcch_ul_list_) :
pdcch_dl_list_t& pdcch_list_) : bwp_cfg(&bwp_cfg_),
bwp_id(bwp_id_), coreset_cfg(&bwp_cfg_.coresets[coreset_id_ - 1].value()),
coreset_id(coreset_id_),
slot_idx(slot_idx_), slot_idx(slot_idx_),
nof_symbols(nof_td_symbols), pdcch_dl_list(pdcch_dl_list_),
nof_freq_res(nof_freq_resources), pdcch_ul_list(pdcch_ul_list_)
pdcch_dl_list(pdcch_list_)
{ {
srsran_assert(nof_td_symbols <= SRSRAN_CORESET_DURATION_MAX, const bool* res_active = &coreset_cfg->freq_resources[0];
nof_freq_res = std::count(res_active, res_active + SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE, true);
srsran_assert(get_td_symbols() <= SRSRAN_CORESET_DURATION_MAX,
"Possible number of time-domain OFDM symbols in CORESET must be within {1,2,3}"); "Possible number of time-domain OFDM symbols in CORESET must be within {1,2,3}");
srsran_assert(nof_freq_resources <= SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE,
"Provided number of CORESET freq domain resources=%d is too high",
nof_freq_resources);
} }
void coreset_region::reset() void coreset_region::reset()
@ -40,9 +40,10 @@ void coreset_region::reset()
saved_dfs_tree.clear(); saved_dfs_tree.clear();
dci_list.clear(); dci_list.clear();
pdcch_dl_list.clear(); pdcch_dl_list.clear();
pdcch_ul_list.clear();
} }
bool coreset_region::alloc_dci(pdcch_grant_type_t alloc_type, uint32_t aggr_idx, uint32_t coreset_id, slot_ue* user) bool coreset_region::alloc_dci(pdcch_grant_type_t alloc_type, uint32_t aggr_idx, slot_ue* user)
{ {
srsran_assert(aggr_idx <= 4, "Invalid DCI aggregation level=%d", 1U << aggr_idx); srsran_assert(aggr_idx <= 4, "Invalid DCI aggregation level=%d", 1U << aggr_idx);
srsran_assert((user == nullptr) xor srsran_assert((user == nullptr) xor
@ -54,9 +55,13 @@ bool coreset_region::alloc_dci(pdcch_grant_type_t alloc_type, uint32_t aggr_idx,
record.ue = user; record.ue = user;
record.aggr_idx = aggr_idx; record.aggr_idx = aggr_idx;
record.alloc_type = alloc_type; record.alloc_type = alloc_type;
if (record.alloc_type == pdcch_grant_type_t::ul_data) {
record.idx = pdcch_ul_list.size();
pdcch_ul_list.emplace_back();
} else {
record.idx = pdcch_dl_list.size(); record.idx = pdcch_dl_list.size();
record.coreset_id = coreset_id;
pdcch_dl_list.emplace_back(); pdcch_dl_list.emplace_back();
}
// Try to allocate grant. If it fails, attempt the same grant, but using a different permutation of past grant DCI // Try to allocate grant. If it fails, attempt the same grant, but using a different permutation of past grant DCI
// positions // positions
@ -74,7 +79,11 @@ bool coreset_region::alloc_dci(pdcch_grant_type_t alloc_type, uint32_t aggr_idx,
// Revert steps to initial state, before dci record allocation was attempted // Revert steps to initial state, before dci record allocation was attempted
dfs_tree = saved_dfs_tree; dfs_tree = saved_dfs_tree;
if (record.alloc_type == pdcch_grant_type_t::ul_data) {
pdcch_ul_list.pop_back();
} else {
pdcch_dl_list.pop_back(); pdcch_dl_list.pop_back();
}
return false; return false;
} }
@ -84,9 +93,13 @@ void coreset_region::rem_last_dci()
// Remove DCI record // Remove DCI record
dfs_tree.pop_back(); dfs_tree.pop_back();
dci_list.pop_back(); if (dci_list.back().alloc_type == pdcch_grant_type_t::ul_data) {
pdcch_ul_list.pop_back();
} else {
pdcch_dl_list.pop_back(); pdcch_dl_list.pop_back();
} }
dci_list.pop_back();
}
bool coreset_region::get_next_dfs() bool coreset_region::get_next_dfs()
{ {
@ -141,8 +154,14 @@ bool coreset_region::alloc_dfs_node(const alloc_record& record, uint32_t start_d
// Allocation successful // Allocation successful
node.total_mask |= node.current_mask; node.total_mask |= node.current_mask;
alloc_dfs.push_back(node); alloc_dfs.push_back(node);
// set new DCI position
if (record.alloc_type == pdcch_grant_type_t::ul_data) {
pdcch_ul_t& pdcch_ul = pdcch_ul_list[record.idx];
pdcch_ul.dci.ctx.location = node.dci_pos;
} else {
pdcch_dl_t& pdcch_dl = pdcch_dl_list[record.idx]; pdcch_dl_t& pdcch_dl = pdcch_dl_list[record.idx];
pdcch_dl.dci.ctx.location = node.dci_pos; pdcch_dl.dci.ctx.location = node.dci_pos;
}
return true; return true;
} }
@ -154,8 +173,8 @@ srsran::span<const uint32_t> coreset_region::get_cce_loc_table(const alloc_recor
switch (record.alloc_type) { switch (record.alloc_type) {
case pdcch_grant_type_t::dl_data: case pdcch_grant_type_t::dl_data:
return record.ue->cfg->cc_params[record.ue->cc] return record.ue->cfg->cc_params[record.ue->cc]
.bwps[bwp_id] .bwps[bwp_cfg->bwp_id - 1]
.coresets[record.coreset_id] .coresets[coreset_id - 1]
.cce_positions[slot_idx][record.aggr_idx]; .cce_positions[slot_idx][record.aggr_idx];
default: default:
break; break;

37
srsenb/src/stack/mac/nr/sched_nr_phy_helpers.cc
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@ -66,36 +66,37 @@ void bitmap_to_prb_array(const rbgmask_t& bitmap, uint32_t bwp_nof_prb, srsran_s
} }
} }
void fill_dci_harq(const harq_proc& h, srsran_dci_dl_nr_t& dci) template <typename DciDlOrUl>
{ void fill_dci_common(const slot_ue& ue, DciDlOrUl& dci)
dci.pid = h.pid;
dci.ndi = h.ndi();
dci.mcs = h.mcs();
}
void fill_dci_ue_cfg(const slot_ue& ue, srsran_dci_dl_nr_t& dci)
{ {
dci.bwp_id = ue.bwp_id; dci.bwp_id = ue.bwp_id;
dci.cc_id = ue.cc; dci.cc_id = ue.cc;
dci.ctx.rnti = ue.rnti; dci.ctx.rnti = ue.rnti;
dci.ctx.rnti_type = srsran_rnti_type_c;
dci.tpc = 1; dci.tpc = 1;
fill_dci_harq(*ue.h_dl, dci); // harq
harq_proc* h = std::is_same<DciDlOrUl, srsran_dci_dl_nr_t>::value ? ue.h_dl : ue.h_ul;
dci.pid = h->pid;
dci.ndi = h->ndi();
dci.mcs = h->mcs();
} }
void fill_dci_harq(const harq_proc& h, srsran_dci_ul_nr_t& dci) void fill_dci_ue_cfg(const slot_ue& ue, srsran_dci_dl_nr_t& dci)
{ {
dci.pid = h.pid; fill_dci_common(ue, dci);
dci.ndi = h.ndi();
dci.mcs = h.mcs();
} }
void fill_dci_ue_cfg(const slot_ue& ue, srsran_dci_ul_nr_t& dci) void fill_dci_ue_cfg(const slot_ue& ue, srsran_dci_ul_nr_t& dci)
{ {
dci.bwp_id = ue.bwp_id; fill_dci_common(ue, dci);
dci.cc_id = ue.cc; }
dci.ctx.rnti = ue.rnti;
dci.tpc = 1; void fill_sch_ue(const slot_ue& ue, const rbgmask_t& rbgmask, const sched_cell_params& cc_cfg, srsran_sch_cfg_nr_t& sch)
fill_dci_harq(*ue.h_ul, dci); {
sch.grant.rnti_type = srsran_rnti_type_c;
sch.grant.rnti = ue.rnti;
sch.grant.nof_layers = 1;
bitmap_to_prb_array(rbgmask, cc_cfg.cell_cfg.nof_prb, sch.grant);
} }
} // namespace sched_nr_impl } // namespace sched_nr_impl

25
srsenb/src/stack/mac/nr/sched_nr_rb_grid.cc
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@ -16,12 +16,13 @@
namespace srsenb { namespace srsenb {
namespace sched_nr_impl { namespace sched_nr_impl {
using pusch_grant = sched_nr_interface::pusch_grant; using pusch_t = sched_nr_interface::pusch_t;
bwp_slot_grid::bwp_slot_grid(const sched_cell_params& cell_params, uint32_t bwp_id_, uint32_t slot_idx_) : bwp_slot_grid::bwp_slot_grid(const sched_cell_params& cell_params, uint32_t bwp_id_, uint32_t slot_idx_) :
dl_rbgs(cell_params.cell_cfg.nof_rbg), ul_rbgs(cell_params.cell_cfg.nof_rbg) dl_rbgs(cell_params.cell_cfg.nof_rbg), ul_rbgs(cell_params.cell_cfg.nof_rbg), bwp_id(bwp_id_)
{ {
coresets.emplace_back(bwp_id_, slot_idx_, 1, cell_params.cell_cfg.bwps[bwp_id_].rb_width / 6, pdcch_dl_list); const uint32_t coreset_id = 1; // Note: for now only one coreset per BWP supported
coresets.emplace_back(cell_params.cell_cfg.bwps[0], coreset_id, slot_idx_, pdcch_dl_list, pdcch_ul_list);
} }
void bwp_slot_grid::reset() void bwp_slot_grid::reset()
@ -72,9 +73,8 @@ alloc_result slot_bwp_sched::alloc_pdsch(slot_ue& ue, const rbgmask_t& dl_mask)
if ((pdsch_mask & dl_mask).any()) { if ((pdsch_mask & dl_mask).any()) {
return alloc_result::sch_collision; return alloc_result::sch_collision;
} }
const uint32_t aggr_idx = 3, coreset_id = 0; const uint32_t aggr_idx = 2, coreset_id = 1;
if (not bwp_grid[ue.pdcch_tti].coresets[coreset_id].alloc_dci( if (not bwp_grid[ue.pdcch_tti].coresets[coreset_id - 1].alloc_dci(pdcch_grant_type_t::dl_data, aggr_idx, &ue)) {
pdcch_grant_type_t::dl_data, aggr_idx, coreset_id, &ue)) {
// Could not find space in PDCCH // Could not find space in PDCCH
return alloc_result::no_cch_space; return alloc_result::no_cch_space;
} }
@ -94,9 +94,7 @@ alloc_result slot_bwp_sched::alloc_pdsch(slot_ue& ue, const rbgmask_t& dl_mask)
pdcch_dl_t& pdcch = bwp_grid[ue.pdcch_tti].pdcch_dl_list.back(); pdcch_dl_t& pdcch = bwp_grid[ue.pdcch_tti].pdcch_dl_list.back();
fill_dci_ue_cfg(ue, pdcch.dci); fill_dci_ue_cfg(ue, pdcch.dci);
pdsch_grants.emplace_back(); pdsch_grants.emplace_back();
pdsch_t& grant = pdsch_grants.back(); fill_sch_ue(ue, dl_mask, bwp_grid.cell_params(), pdsch_grants.back().sch);
grant.sch.grant.rnti = ue.rnti;
bitmap_to_prb_array(dl_mask, bwp_grid.nof_prbs(), grant.sch.grant);
pdsch_mask |= dl_mask; pdsch_mask |= dl_mask;
return alloc_result::success; return alloc_result::success;
@ -117,9 +115,8 @@ alloc_result slot_bwp_sched::alloc_pusch(slot_ue& ue, const rbgmask_t& ul_mask)
if ((pusch_mask & ul_mask).any()) { if ((pusch_mask & ul_mask).any()) {
return alloc_result::sch_collision; return alloc_result::sch_collision;
} }
const uint32_t aggr_idx = 3, coreset_id = 0; const uint32_t aggr_idx = 2, coreset_id = 1;
if (not bwp_grid[ue.pdcch_tti].coresets[coreset_id].alloc_dci( if (not bwp_grid[ue.pdcch_tti].coresets[coreset_id - 1].alloc_dci(pdcch_grant_type_t::ul_data, aggr_idx, &ue)) {
pdcch_grant_type_t::ul_data, aggr_idx, coreset_id, &ue)) {
// Could not find space in PDCCH // Could not find space in PDCCH
return alloc_result::no_cch_space; return alloc_result::no_cch_space;
} }
@ -139,9 +136,7 @@ alloc_result slot_bwp_sched::alloc_pusch(slot_ue& ue, const rbgmask_t& ul_mask)
pdcch_ul_t& pdcch = bwp_grid[ue.pdcch_tti].pdcch_ul_list.back(); pdcch_ul_t& pdcch = bwp_grid[ue.pdcch_tti].pdcch_ul_list.back();
fill_dci_ue_cfg(ue, pdcch.dci); fill_dci_ue_cfg(ue, pdcch.dci);
pusch_grants.emplace_back(); pusch_grants.emplace_back();
pusch_grant& grant = pusch_grants.back(); fill_sch_ue(ue, ul_mask, bwp_grid.cell_params(), pusch_grants.back().sch);
grant.dci.ctx.rnti = ue.rnti;
grant.bitmap = ul_mask;
pusch_mask |= ul_mask; pusch_mask |= ul_mask;
return alloc_result::success; return alloc_result::success;

2
srsenb/src/stack/mac/nr/sched_nr_ue.cc
Unescape Escape View File

@ -34,7 +34,7 @@ ue_cfg_extended::ue_cfg_extended(uint16_t rnti_, const ue_cfg_t& uecfg) : ue_cfg
auto& coreset = bwp.coresets.back(); auto& coreset = bwp.coresets.back();
coreset.cfg = &phy_cfg.pdcch.coreset[csid]; coreset.cfg = &phy_cfg.pdcch.coreset[csid];
for (auto& ss : bwp.search_spaces) { for (auto& ss : bwp.search_spaces) {
if (ss.cfg->coreset_id == csid) { if (ss.cfg->coreset_id == csid + 1) {
coreset.ss_list.push_back(&ss); coreset.ss_list.push_back(&ss);
get_dci_locs(*coreset.cfg, *coreset.ss_list.back()->cfg, rnti, coreset.cce_positions); get_dci_locs(*coreset.cfg, *coreset.ss_list.back()->cfg, rnti, coreset.cce_positions);
} }

71
srsenb/test/mac/nr/sched_nr_test.cc
Unescape Escape View File

@ -17,6 +17,36 @@
namespace srsenb { namespace srsenb {
srsran_coreset_t get_default_coreset()
{
srsran_coreset_t coreset{};
coreset.id = 1;
coreset.duration = 1;
coreset.precoder_granularity = srsran_coreset_precoder_granularity_reg_bundle;
for (uint32_t i = 0; i < SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE; ++i) {
coreset.freq_resources[i] = i < 8;
}
return coreset;
}
sched_nr_interface::cell_cfg_t get_default_cell_cfg()
{
sched_nr_interface::cell_cfg_t cell_cfg{};
cell_cfg.bwps.resize(1);
cell_cfg.bwps[0].coresets[0].emplace(get_default_coreset());
return cell_cfg;
}
std::vector<sched_nr_interface::cell_cfg_t> get_default_cells_cfg(uint32_t nof_sectors)
{
std::vector<sched_nr_interface::cell_cfg_t> cells;
cells.reserve(nof_sectors);
for (uint32_t i = 0; i < nof_sectors; ++i) {
cells.push_back(get_default_cell_cfg());
}
return cells;
}
sched_nr_interface::ue_cfg_t get_default_ue_cfg(uint32_t nof_cc) sched_nr_interface::ue_cfg_t get_default_ue_cfg(uint32_t nof_cc)
{ {
sched_nr_interface::ue_cfg_t uecfg{}; sched_nr_interface::ue_cfg_t uecfg{};
@ -25,22 +55,22 @@ sched_nr_interface::ue_cfg_t get_default_ue_cfg(uint32_t nof_cc)
uecfg.carriers[cc].active = true; uecfg.carriers[cc].active = true;
} }
uecfg.phy_cfg.pdcch.coreset_present[0] = true; uecfg.phy_cfg.pdcch.coreset_present[0] = true;
uecfg.phy_cfg.pdcch.coreset[0].id = 0; uecfg.phy_cfg.pdcch.coreset[0] = get_default_coreset();
for (uint32_t i = 0; i < 100 / 6; ++i) {
uecfg.phy_cfg.pdcch.coreset[0].freq_resources[i] = true;
}
uecfg.phy_cfg.pdcch.coreset[0].duration = 1;
uecfg.phy_cfg.pdcch.search_space_present[0] = true; uecfg.phy_cfg.pdcch.search_space_present[0] = true;
uecfg.phy_cfg.pdcch.search_space[0].id = 0; auto& ss = uecfg.phy_cfg.pdcch.search_space[0];
uecfg.phy_cfg.pdcch.search_space[0].coreset_id = 0; ss.id = 1;
uecfg.phy_cfg.pdcch.search_space[0].duration = 1; ss.coreset_id = 1;
uecfg.phy_cfg.pdcch.search_space[0].type = srsran_search_space_type_common_0; ss.duration = 1;
uecfg.phy_cfg.pdcch.search_space[0].nof_candidates[0] = 1; ss.type = srsran_search_space_type_common_0;
uecfg.phy_cfg.pdcch.search_space[0].nof_candidates[1] = 1; ss.nof_candidates[0] = 1;
uecfg.phy_cfg.pdcch.search_space[0].nof_candidates[2] = 1; ss.nof_candidates[1] = 1;
uecfg.phy_cfg.pdcch.search_space[0].nof_candidates[3] = 1; ss.nof_candidates[2] = 1;
uecfg.phy_cfg.pdcch.search_space[0].nof_formats = 1; ss.nof_candidates[3] = 0;
uecfg.phy_cfg.pdcch.search_space[0].formats[0] = srsran_dci_format_nr_0_0; ss.nof_candidates[4] = 0;
ss.nof_formats = 1;
ss.formats[0] = srsran_dci_format_nr_1_0;
return uecfg; return uecfg;
} }
@ -87,13 +117,11 @@ struct task_job_manager {
void sched_nr_cfg_serialized_test() void sched_nr_cfg_serialized_test()
{ {
auto& mac_logger = srslog::fetch_basic_logger("MAC");
uint32_t max_nof_ttis = 1000, nof_sectors = 2; uint32_t max_nof_ttis = 1000, nof_sectors = 2;
task_job_manager tasks; task_job_manager tasks;
sched_nr_interface::sched_cfg_t cfg; sched_nr_interface::sched_cfg_t cfg;
std::vector<sched_nr_interface::cell_cfg_t> cells_cfg(nof_sectors); std::vector<sched_nr_interface::cell_cfg_t> cells_cfg = get_default_cells_cfg(nof_sectors);
sched_nr_sim_base sched_tester(cfg, cells_cfg, "Serialized Test"); sched_nr_sim_base sched_tester(cfg, cells_cfg, "Serialized Test");
@ -121,13 +149,11 @@ void sched_nr_cfg_serialized_test()
void sched_nr_cfg_parallel_cc_test() void sched_nr_cfg_parallel_cc_test()
{ {
auto& mac_logger = srslog::fetch_basic_logger("MAC");
uint32_t max_nof_ttis = 1000; uint32_t max_nof_ttis = 1000;
task_job_manager tasks; task_job_manager tasks;
sched_nr_interface::sched_cfg_t cfg; sched_nr_interface::sched_cfg_t cfg;
std::vector<sched_nr_interface::cell_cfg_t> cells_cfg(4); std::vector<sched_nr_interface::cell_cfg_t> cells_cfg = get_default_cells_cfg(4);
sched_nr_sim_base sched_tester(cfg, cells_cfg, "Parallel CC Test"); sched_nr_sim_base sched_tester(cfg, cells_cfg, "Parallel CC Test");
@ -162,8 +188,7 @@ void sched_nr_cfg_parallel_sf_test()
sched_nr_interface::sched_cfg_t cfg; sched_nr_interface::sched_cfg_t cfg;
cfg.nof_concurrent_subframes = 2; cfg.nof_concurrent_subframes = 2;
std::vector<sched_nr_interface::cell_cfg_t> cells_cfg; std::vector<sched_nr_interface::cell_cfg_t> cells_cfg = get_default_cells_cfg(nof_sectors);
cells_cfg.resize(nof_sectors);
sched_nr sched(cfg); sched_nr sched(cfg);
sched.cell_cfg(cells_cfg); sched.cell_cfg(cells_cfg);

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