5g-team
/
srsRAN_4G
mirror of https://github.com/pvnis/srsRAN_4G.git
2
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

refactor naming for s/p/cell structs and {enb,ue}_cc_idx

Browse Source
master
Andre Puschmann 5 years ago
parent 639f473042
commit f2e1bfa699
8 changed files with 107 additions and 105 deletions
Show Stats Download Patch File Download Diff File

2
lib/include/srslte/interfaces/enb_interfaces.h
Unescape Escape View File

@ -247,7 +247,7 @@ public:
typedef struct { typedef struct {
bool configured = false; ///< Indicates whether PHY shall consider configuring this cell/carrier bool configured = false; ///< Indicates whether PHY shall consider configuring this cell/carrier
uint32_t cc_idx = 0; ///< eNb Cell index uint32_t enb_cc_idx = 0; ///< eNb Cell index
srslte::phy_cfg_t phy_cfg = {}; ///< Dedicated physical layer configuration srslte::phy_cfg_t phy_cfg = {}; ///< Dedicated physical layer configuration
} phy_rrc_dedicated_t; } phy_rrc_dedicated_t;

23
srsenb/hdr/phy/phy_ue_db.h
Unescape Escape View File

@ -52,28 +52,29 @@ private:
* +-----------------------------------------------------------------------------+ * +-----------------------------------------------------------------------------+
*/ */
typedef enum { typedef enum {
scell_state_default = 0, ///< Default values, not configured, not active cell_state_none = 0, ///< Uninitialized
scell_state_deactivated, ///< Configured from RRC but not activated cell_state_primary, ///< PCell
scell_state_active ///< PCell or activated from MAC cell_state_secondary_inactive, ///< Configured from RRC but not activated
} scell_state_t; cell_state_secondary_active ///< Configured and activated from MAC
} cell_state_t;
/** /**
* SCell information for the UE database * Cell information for the UE database
*/ */
typedef struct { typedef struct {
scell_state_t state = scell_state_default; ///< Configuration state cell_state_t state = cell_state_none; ///< Configuration state
uint32_t cc_idx = 0; ///< Corresponding eNb cell/carrier index uint32_t enb_cc_idx = 0; ///< Corresponding eNb cell/carrier index
uint8_t last_ri = 0; ///< Last reported rank indicator uint8_t last_ri = 0; ///< Last reported rank indicator
srslte_ra_tb_t last_tb[SRSLTE_MAX_HARQ_PROC] = {}; ///< Stores last PUSCH Resource allocation srslte_ra_tb_t last_tb[SRSLTE_MAX_HARQ_PROC] = {}; ///< Stores last PUSCH Resource allocation
srslte::phy_cfg_t phy_cfg; ///< Configuration, it has a default constructor srslte::phy_cfg_t phy_cfg; ///< Configuration, it has a default constructor
} scell_info_t; } cell_info_t;
/** /**
* UE object stored in the PHY common database * UE object stored in the PHY common database
*/ */
struct common_ue { struct common_ue {
srslte_pdsch_ack_t pdsch_ack[TTIMOD_SZ] = {}; ///< Pending acknowledgements for this SCell srslte_pdsch_ack_t pdsch_ack[TTIMOD_SZ] = {}; ///< Pending acknowledgements for this Cell
scell_info_t scell_info[SRSLTE_MAX_CARRIERS]; ///< SCell information, indexed by scell_idx cell_info_t cell_info[SRSLTE_MAX_CARRIERS]; ///< Cell information, indexed by cell_idx
}; };
/** /**
@ -131,7 +132,7 @@ private:
* @param cc_idx the eNb cell/carrier index to look for in the RNTI. * @param cc_idx the eNb cell/carrier index to look for in the RNTI.
* @return the SCell index as described above. * @return the SCell index as described above.
*/ */
inline uint32_t _get_scell_idx(uint16_t rnti, uint32_t cc_idx) const; inline uint32_t _get_cell_idx(uint16_t rnti, uint32_t cc_idx) const;
public: public:
/** /**

3
srsenb/hdr/stack/rrc/rrc.h
Unescape Escape View File

@ -89,6 +89,7 @@ struct rrc_meas_cfg_t {
struct rrc_cfg_t { struct rrc_cfg_t {
uint32_t enb_id; ///< Required to pack SIB1 uint32_t enb_id; ///< Required to pack SIB1
// Per eNB SIBs
asn1::rrc::sib_type1_s sib1; asn1::rrc::sib_type1_s sib1;
asn1::rrc::sib_info_item_c sibs[ASN1_RRC_MAX_SIB]; asn1::rrc::sib_info_item_c sibs[ASN1_RRC_MAX_SIB];
asn1::rrc::mac_main_cfg_s mac_cnfg; asn1::rrc::mac_main_cfg_s mac_cnfg;
@ -340,7 +341,7 @@ public:
* *
* @param phys_cfg_ded ASN1 Physical layer configuration dedicated * @param phys_cfg_ded ASN1 Physical layer configuration dedicated
*/ */
void apply_setup_phy_config(const asn1::rrc::phys_cfg_ded_s& phys_cfg_ded); void apply_setup_phy_config_dedicated(const asn1::rrc::phys_cfg_ded_s& phys_cfg_ded);
/** /**
* Reconfigures the PCell and SCell physical layer dedicated configuration of the UE. This method shall be called * Reconfigures the PCell and SCell physical layer dedicated configuration of the UE. This method shall be called

4
srsenb/src/phy/phy.cc
Unescape Escape View File

@ -157,7 +157,7 @@ int phy::add_rnti(uint16_t rnti, uint32_t pcell_index, bool is_temporal)
if (SRSLTE_RNTI_ISUSER(rnti)) { if (SRSLTE_RNTI_ISUSER(rnti)) {
// Create default PHY configuration with the desired PCell index // Create default PHY configuration with the desired PCell index
phy_interface_rrc_lte::phy_rrc_dedicated_list_t phy_rrc_dedicated_list(1); phy_interface_rrc_lte::phy_rrc_dedicated_list_t phy_rrc_dedicated_list(1);
phy_rrc_dedicated_list[0].cc_idx = pcell_index; phy_rrc_dedicated_list[0].enb_cc_idx = pcell_index;
workers_common.ue_db.addmod_rnti(rnti, phy_rrc_dedicated_list); workers_common.ue_db.addmod_rnti(rnti, phy_rrc_dedicated_list);
} }
@ -239,7 +239,7 @@ void phy::set_config_dedicated(uint16_t rnti, const phy_rrc_dedicated_list_t& de
if (scell_idx != 0 && config.configured) { if (scell_idx != 0 && config.configured) {
// Add RNTI to workers // Add RNTI to workers
for (uint32_t w = 0; w < nof_workers; w++) { for (uint32_t w = 0; w < nof_workers; w++) {
workers[w].add_rnti(rnti, config.cc_idx, false, false); workers[w].add_rnti(rnti, config.enb_cc_idx, false, false);
} }
} }
} }

151
srsenb/src/phy/phy_ue_db.cc
Unescape Escape View File

@ -42,19 +42,19 @@ inline void phy_ue_db::_add_rnti(uint16_t rnti)
} }
// Create new UE by accesing it // Create new UE by accesing it
ue_db[rnti].scell_info[0] = {}; ue_db[rnti].cell_info[0] = {};
// Get UE // Get UE
common_ue& ue = ue_db[rnti]; common_ue& ue = ue_db[rnti];
// Load default values to PCell // Load default values to PCell
ue.scell_info[0].phy_cfg.set_defaults(); ue.cell_info[0].phy_cfg.set_defaults();
// Set constant configuration fields // Set constant configuration fields
_set_common_config_rnti(rnti); _set_common_config_rnti(rnti);
// PCell shall be active by default // Configure as PCell
ue.scell_info[0].state = scell_state_active; ue.cell_info[0].state = cell_state_primary;
// Iterate all pending ACK // Iterate all pending ACK
for (uint32_t tti = 0; tti < TTIMOD_SZ; tti++) { for (uint32_t tti = 0; tti < TTIMOD_SZ; tti++) {
@ -75,17 +75,17 @@ inline void phy_ue_db::_clear_tti_pending_rnti(uint32_t tti, uint16_t rnti)
pdsch_ack = {}; pdsch_ack = {};
uint32_t nof_active_cc = 0; uint32_t nof_active_cc = 0;
for (auto& scell_info : ue.scell_info) { for (auto& cell_info : ue.cell_info) {
if (scell_info.state == scell_state_active) { if (cell_info.state == cell_state_primary or cell_info.state == cell_state_secondary_active) {
nof_active_cc++; nof_active_cc++;
} }
} }
// Copy essentials // Copy essentials
pdsch_ack.transmission_mode = ue.scell_info[0].phy_cfg.dl_cfg.tm; pdsch_ack.transmission_mode = ue.cell_info[0].phy_cfg.dl_cfg.tm;
pdsch_ack.nof_cc = nof_active_cc; pdsch_ack.nof_cc = nof_active_cc;
pdsch_ack.ack_nack_feedback_mode = ue.scell_info[0].phy_cfg.ul_cfg.pucch.ack_nack_feedback_mode; pdsch_ack.ack_nack_feedback_mode = ue.cell_info[0].phy_cfg.ul_cfg.pucch.ack_nack_feedback_mode;
pdsch_ack.simul_cqi_ack = ue.scell_info[0].phy_cfg.ul_cfg.pucch.simul_cqi_ack; pdsch_ack.simul_cqi_ack = ue.cell_info[0].phy_cfg.ul_cfg.pucch.simul_cqi_ack;
} }
inline void phy_ue_db::_set_common_config_rnti(uint16_t rnti) inline void phy_ue_db::_set_common_config_rnti(uint16_t rnti)
@ -96,7 +96,7 @@ inline void phy_ue_db::_set_common_config_rnti(uint16_t rnti)
common_ue& ue = ue_db[rnti]; common_ue& ue = ue_db[rnti];
// Iterate all cells/carriers // Iterate all cells/carriers
for (auto& scell_info : ue.scell_info) { for (auto& scell_info : ue.cell_info) {
scell_info.phy_cfg.dl_cfg.pdsch.rnti = rnti; scell_info.phy_cfg.dl_cfg.pdsch.rnti = rnti;
scell_info.phy_cfg.ul_cfg.pucch.rnti = rnti; scell_info.phy_cfg.ul_cfg.pucch.rnti = rnti;
scell_info.phy_cfg.ul_cfg.pusch.rnti = rnti; scell_info.phy_cfg.ul_cfg.pusch.rnti = rnti;
@ -110,19 +110,19 @@ inline void phy_ue_db::_set_common_config_rnti(uint16_t rnti)
} }
} }
inline uint32_t phy_ue_db::_get_scell_idx(uint16_t rnti, uint32_t cc_idx) const inline uint32_t phy_ue_db::_get_cell_idx(uint16_t rnti, uint32_t cc_idx) const
{ {
uint32_t scell_idx = 0; uint32_t cell_idx = 0;
const common_ue& ue = ue_db.at(rnti); const common_ue& ue = ue_db.at(rnti);
for (scell_idx = 0; scell_idx < SRSLTE_MAX_CARRIERS; scell_idx++) { for (cell_idx = 0; cell_idx < SRSLTE_MAX_CARRIERS; cell_idx++) {
const scell_info_t& scell_info = ue.scell_info[scell_idx]; const cell_info_t& scell_info = ue.cell_info[cell_idx];
if (scell_info.cc_idx == cc_idx && scell_info.state != scell_state_deactivated) { if (scell_info.enb_cc_idx == cc_idx && scell_info.state != cell_state_secondary_inactive) {
return scell_idx; return cell_idx;
} }
} }
return scell_idx; return cell_idx;
} }
void phy_ue_db::clear_tti_pending_ack(uint32_t tti) void phy_ue_db::clear_tti_pending_ack(uint32_t tti)
@ -148,33 +148,34 @@ void phy_ue_db::addmod_rnti(uint16_t
// Get UE by reference // Get UE by reference
common_ue& ue = ue_db[rnti]; common_ue& ue = ue_db[rnti];
// Iterate PHY RRC configuration for each cell/carrier // Iterate PHY RRC configuration for each UE cell/carrier
for (uint32_t scell_idx = 0; scell_idx < phy_rrc_dedicated_list.size() && scell_idx < SRSLTE_MAX_CARRIERS; for (uint32_t ue_cc_idx = 0; ue_cc_idx < phy_rrc_dedicated_list.size() && ue_cc_idx < SRSLTE_MAX_CARRIERS;
scell_idx++) { ue_cc_idx++) {
auto& phy_rrc_dedicated = phy_rrc_dedicated_list[scell_idx]; auto& phy_rrc_dedicated = phy_rrc_dedicated_list[ue_cc_idx];
// Configured, add/modify entry in the scell_info map // Configured, add/modify entry in the scell_info map
auto& scell_info = ue.scell_info[scell_idx]; auto& cell_info = ue.cell_info[ue_cc_idx];
if (phy_rrc_dedicated.configured) { if (phy_rrc_dedicated.configured or cell_info.state == cell_state_primary) {
// Set SCell information // Set cell information
scell_info.cc_idx = phy_rrc_dedicated.cc_idx; cell_info.enb_cc_idx = phy_rrc_dedicated.enb_cc_idx;
scell_info.phy_cfg = phy_rrc_dedicated.phy_cfg; cell_info.phy_cfg = phy_rrc_dedicated.phy_cfg;
// Set constant configuration fields // Set constant configuration fields
_set_common_config_rnti(rnti); _set_common_config_rnti(rnti);
// Set SCell state, all deactivated by default except PCell // Set Cell state, all inactive by default except PCell
scell_info.state = scell_idx == 0 ? scell_state_active : scell_state_deactivated; if (cell_info.state != cell_state_primary) {
cell_info.state = cell_state_secondary_inactive;
}
} else { } else {
// Cell without configuration shall be default except if it PCell // Cell without configuration (except PCell)
scell_info.state = scell_idx == 0 ? scell_state_active : scell_state_default; cell_info.state = cell_state_none;
} }
} }
// Iterate the rest of SCells // Make sure remaining cells are set to none
for (uint32_t scell_idx = phy_rrc_dedicated_list.size(); scell_idx < SRSLTE_MAX_CARRIERS; scell_idx++) { for (uint32_t cell_idx = phy_rrc_dedicated_list.size(); cell_idx < SRSLTE_MAX_CARRIERS; cell_idx++) {
// Set state of these to default ue.cell_info[cell_idx].state = cell_state_none;
ue.scell_info[scell_idx].state = scell_state_default;
} }
} }
@ -207,15 +208,15 @@ void phy_ue_db::rem_rnti(uint16_t rnti)
UE_DB_ASSERT_RNTI(RNTI, RET); \ UE_DB_ASSERT_RNTI(RNTI, RET); \
\ \
/* Check Component Carrier is part of UE SCell map*/ \ /* Check Component Carrier is part of UE SCell map*/ \
if (_get_scell_idx(RNTI, CC_IDX) == SRSLTE_MAX_CARRIERS) { \ if (_get_cell_idx(RNTI, CC_IDX) == SRSLTE_MAX_CARRIERS) { \
ERROR("Trying to access cell/carrier index %d in RNTI x%x. It does not exist.\n", CC_IDX, RNTI); \ ERROR("Trying to access cell/carrier index %d in RNTI x%x. It does not exist.\n", CC_IDX, RNTI); \
return RET; \ return RET; \
} \ } \
\ \
/* Check SCell index is in range */ \ /* Check SCell index is in range */ \
const uint32_t scell_idx = _get_scell_idx(RNTI, CC_IDX); \ const uint32_t cell_idx = _get_cell_idx(RNTI, CC_IDX); \
if (scell_idx == SRSLTE_MAX_CARRIERS) { \ if (cell_idx == SRSLTE_MAX_CARRIERS) { \
ERROR("Corrupted SCell index %d for RNTI x%x and cell/carrier index %d\n", scell_idx, RNTI, CC_IDX); \ ERROR("Corrupted Cell index %d for RNTI x%x and cell/carrier index %d\n", cell_idx, RNTI, CC_IDX); \
return RET; \ return RET; \
} \ } \
} while (false) } while (false)
@ -225,9 +226,9 @@ void phy_ue_db::rem_rnti(uint16_t rnti)
/* Assert RNTI exists and eNb cell/carrier is configured */ \ /* Assert RNTI exists and eNb cell/carrier is configured */ \
UE_DB_ASSERT_CELL(RNTI, CC_IDX, RET); \ UE_DB_ASSERT_CELL(RNTI, CC_IDX, RET); \
\ \
/* Check SCell is active */ \ /* Check Cell is active */ \
auto& scell_info = ue_db.at(RNTI).scell_info[_get_scell_idx(RNTI, CC_IDX)]; \ auto& cell_info = ue_db.at(RNTI).cell_info[_get_cell_idx(RNTI, CC_IDX)]; \
if (scell_info.state != scell_state_active) { \ if (cell_info.state != cell_state_primary and cell_info.state != cell_state_secondary_active) { \
return RET; \ return RET; \
} \ } \
} while (false) } while (false)
@ -238,32 +239,32 @@ void phy_ue_db::rem_rnti(uint16_t rnti)
UE_DB_ASSERT_CELL(RNTI, CC_IDX, RET); \ UE_DB_ASSERT_CELL(RNTI, CC_IDX, RET); \
\ \
/* CC_IDX is the RNTI PCell */ \ /* CC_IDX is the RNTI PCell */ \
if (_get_scell_idx(RNTI, CC_IDX) != 0) { \ if (_get_cell_idx(RNTI, CC_IDX) != 0) { \
return RET; \ return RET; \
} \ } \
} while (false) } while (false)
#define UE_DB_ASSERT_SCELL(RNTI, SCELL_IDX, RET) \ #define UE_DB_ASSERT_SCELL(RNTI, CELL_IDX, RET) \
do { \ do { \
/* Assert RNTI exists and eNb cell/carrier is configured */ \ /* Assert RNTI exists and eNb cell/carrier is configured */ \
UE_DB_ASSERT_RNTI(RNTI, RET); \ UE_DB_ASSERT_RNTI(RNTI, RET); \
\ \
/* Check SCell index is in range */ \ /* Check SCell index is in range */ \
if (SCELL_IDX >= SRSLTE_MAX_CARRIERS) { \ if (CELL_IDX >= SRSLTE_MAX_CARRIERS) { \
ERROR("Out-of-bounds SCell index %d for RNTI x%x.\n", SCELL_IDX, RNTI); \ ERROR("Out-of-bounds SCell index %d for RNTI x%x.\n", CELL_IDX, RNTI); \
return RET; \ return RET; \
} \ } \
} while (false) } while (false)
#define UE_DB_ASSERT_ACTIVE_SCELL(RNTI, SCELL_IDX, RET) \ #define UE_DB_ASSERT_ACTIVE_SCELL(RNTI, CELL_IDX, RET) \
do { \ do { \
/* Assert RNTI exists and eNb cell/carrier is configured */ \ /* Assert RNTI exists and eNb cell/carrier is configured */ \
UE_DB_ASSERT_SCELL(RNTI, SCELL_IDX, RET); \ UE_DB_ASSERT_SCELL(RNTI, CELL_IDX, RET); \
\ \
/* Check SCell is active, ignore PCell state */ \ /* Check SCell is active, ignore PCell state */ \
auto& scell_info = ue_db.at(RNTI).scell_info[SCELL_IDX]; \ auto& cell_info = ue_db.at(RNTI).cell_info[CELL_IDX]; \
if (SCELL_IDX != 0 && scell_info.state != scell_state_active) { \ if (CELL_IDX != 0 && cell_info.state != cell_state_secondary_active) { \
ERROR("Failed to assert active SCell %d for RNTI x%x", SCELL_IDX, RNTI); \ ERROR("Failed to assert active SCell %d for RNTI x%x", CELL_IDX, RNTI); \
return RET; \ return RET; \
} \ } \
} while (false) } while (false)
@ -282,21 +283,21 @@ void phy_ue_db::rem_rnti(uint16_t rnti)
} \ } \
} while (false) } while (false)
void phy_ue_db::activate_deactivate_scell(uint16_t rnti, uint32_t scell_idx, bool activate) void phy_ue_db::activate_deactivate_scell(uint16_t rnti, uint32_t cell_idx, bool activate)
{ {
// Assert RNTI and SCell are valid // Assert RNTI and SCell are valid
UE_DB_ASSERT_SCELL(rnti, scell_idx, /* void */); UE_DB_ASSERT_SCELL(rnti, cell_idx, /* void */);
auto& scell_info = ue_db[rnti].scell_info[scell_idx]; auto& cell_info = ue_db[rnti].cell_info[cell_idx];
// If scell is default only complain // If scell is default only complain
if (activate and scell_info.state == scell_state_default) { if (activate and cell_info.state == cell_state_none) {
ERROR("RNTI x%x SCell %d has received an activation MAC command but it was not configured\n", rnti, scell_idx); ERROR("RNTI x%x SCell %d has received an activation MAC command but it was not configured\n", rnti, cell_idx);
return; return;
} }
// Set scell state // Set scell state
scell_info.state = (activate) ? scell_state_active : scell_state_deactivated; cell_info.state = (activate) ? cell_state_secondary_active : cell_state_secondary_inactive;
} }
srslte::phy_cfg_t phy_ue_db::get_config(uint16_t rnti, uint32_t cc_idx) const srslte::phy_cfg_t phy_ue_db::get_config(uint16_t rnti, uint32_t cc_idx) const
@ -311,7 +312,7 @@ srslte::phy_cfg_t phy_ue_db::get_config(uint16_t rnti, uint32_t cc_idx) const
UE_DB_ASSERT_ACTIVE_CELL(rnti, cc_idx, default_cfg); UE_DB_ASSERT_ACTIVE_CELL(rnti, cc_idx, default_cfg);
return ue_db.at(rnti).scell_info[_get_scell_idx(rnti, cc_idx)].phy_cfg; return ue_db.at(rnti).cell_info[_get_cell_idx(rnti, cc_idx)].phy_cfg;
} }
void phy_ue_db::set_ack_pending(uint32_t tti, uint32_t cc_idx, const srslte_dci_dl_t& dci) void phy_ue_db::set_ack_pending(uint32_t tti, uint32_t cc_idx, const srslte_dci_dl_t& dci)
@ -322,7 +323,7 @@ void phy_ue_db::set_ack_pending(uint32_t tti, uint32_t cc_idx, const srslte_dci_
UE_DB_ASSERT_ACTIVE_CELL(dci.rnti, cc_idx, /* void */); UE_DB_ASSERT_ACTIVE_CELL(dci.rnti, cc_idx, /* void */);
common_ue& ue = ue_db[dci.rnti]; common_ue& ue = ue_db[dci.rnti];
uint32_t scell_idx = _get_scell_idx(dci.rnti, cc_idx); uint32_t scell_idx = _get_cell_idx(dci.rnti, cc_idx);
srslte_pdsch_ack_cc_t& pdsch_ack_cc = ue.pdsch_ack[TTIMOD(tti)].cc[scell_idx]; srslte_pdsch_ack_cc_t& pdsch_ack_cc = ue.pdsch_ack[TTIMOD(tti)].cc[scell_idx];
pdsch_ack_cc.M = 1; ///< Hardcoded for FDD pdsch_ack_cc.M = 1; ///< Hardcoded for FDD
@ -363,7 +364,7 @@ bool phy_ue_db::fill_uci_cfg(uint32_t tti,
UE_DB_ASSERT_CELL_LIST_CFG(false); UE_DB_ASSERT_CELL_LIST_CFG(false);
const auto& ue = ue_db.at(rnti); const auto& ue = ue_db.at(rnti);
const auto& pcell_cfg = ue.scell_info[0].phy_cfg; const auto& pcell_cfg = ue.cell_info[0].phy_cfg;
bool uci_required = false; bool uci_required = false;
// Check if SR opportunity (will only be used in PUCCH) // Check if SR opportunity (will only be used in PUCCH)
@ -372,18 +373,18 @@ bool phy_ue_db::fill_uci_cfg(uint32_t tti,
// Get pending CQI reports for this TTI, stops at first CC reporting // Get pending CQI reports for this TTI, stops at first CC reporting
bool periodic_cqi_required = false; bool periodic_cqi_required = false;
for (uint32_t scell_idx = 0; scell_idx < SRSLTE_MAX_CARRIERS and not periodic_cqi_required; scell_idx++) { for (uint32_t cell_idx = 0; cell_idx < SRSLTE_MAX_CARRIERS and not periodic_cqi_required; cell_idx++) {
const scell_info_t& scell_info = ue.scell_info[scell_idx]; const cell_info_t& cell_info = ue.cell_info[cell_idx];
const srslte_dl_cfg_t& dl_cfg = scell_info.phy_cfg.dl_cfg; const srslte_dl_cfg_t& dl_cfg = cell_info.phy_cfg.dl_cfg;
if (scell_info.state == scell_state_active) { if (cell_info.state == cell_state_primary or cell_info.state == cell_state_secondary_active) {
const srslte_cell_t& cell = cell_cfg_list->at(scell_info.cc_idx).cell; const srslte_cell_t& cell = cell_cfg_list->at(cell_info.enb_cc_idx).cell;
// Check if CQI report is required // Check if CQI report is required
periodic_cqi_required = srslte_enb_dl_gen_cqi_periodic(&cell, &dl_cfg, tti, scell_info.last_ri, &uci_cfg.cqi); periodic_cqi_required = srslte_enb_dl_gen_cqi_periodic(&cell, &dl_cfg, tti, cell_info.last_ri, &uci_cfg.cqi);
// Save SCell index for using it after // Save SCell index for using it after
uci_cfg.cqi.scell_index = scell_idx; uci_cfg.cqi.scell_index = cell_idx;
} }
} }
uci_required |= periodic_cqi_required; uci_required |= periodic_cqi_required;
@ -391,8 +392,8 @@ bool phy_ue_db::fill_uci_cfg(uint32_t tti,
// If no periodic CQI report required, check aperiodic reporting // If no periodic CQI report required, check aperiodic reporting
if ((not periodic_cqi_required) and aperiodic_cqi_request) { if ((not periodic_cqi_required) and aperiodic_cqi_request) {
// Aperiodic only supported for PCell // Aperiodic only supported for PCell
const scell_info_t& pcell_info = ue.scell_info[0]; const cell_info_t& pcell_info = ue.cell_info[0];
const srslte_cell_t& cell = cell_cfg_list->at(pcell_info.cc_idx).cell; const srslte_cell_t& cell = cell_cfg_list->at(pcell_info.enb_cc_idx).cell;
const srslte_dl_cfg_t& dl_cfg = pcell_info.phy_cfg.dl_cfg; const srslte_dl_cfg_t& dl_cfg = pcell_info.phy_cfg.dl_cfg;
uci_required = srslte_enb_dl_gen_cqi_aperiodic(&cell, &dl_cfg, pcell_info.last_ri, &uci_cfg.cqi); uci_required = srslte_enb_dl_gen_cqi_aperiodic(&cell, &dl_cfg, pcell_info.last_ri, &uci_cfg.cqi);
@ -401,7 +402,7 @@ bool phy_ue_db::fill_uci_cfg(uint32_t tti,
// Get pending ACKs from PDSCH // Get pending ACKs from PDSCH
srslte_dl_sf_cfg_t dl_sf_cfg = {}; srslte_dl_sf_cfg_t dl_sf_cfg = {};
dl_sf_cfg.tti = tti; dl_sf_cfg.tti = tti;
const srslte_cell_t& cell = cell_cfg_list->at(ue.scell_info[0].cc_idx).cell; const srslte_cell_t& cell = cell_cfg_list->at(ue.cell_info[0].enb_cc_idx).cell;
srslte_enb_dl_gen_ack(&cell, &dl_sf_cfg, &ue.pdsch_ack[TTIMOD(tti)], &uci_cfg); srslte_enb_dl_gen_ack(&cell, &dl_sf_cfg, &ue.pdsch_ack[TTIMOD(tti)], &uci_cfg);
uci_required |= (srslte_uci_cfg_total_ack(&uci_cfg) > 0); uci_required |= (srslte_uci_cfg_total_ack(&uci_cfg) > 0);
@ -433,7 +434,7 @@ void phy_ue_db::send_uci_data(uint32_t tti,
// Get ACK info // Get ACK info
srslte_pdsch_ack_t& pdsch_ack = ue.pdsch_ack[TTIMOD(tti)]; srslte_pdsch_ack_t& pdsch_ack = ue.pdsch_ack[TTIMOD(tti)];
srslte_enb_dl_get_ack(&cell_cfg_list->at(ue.scell_info[0].cc_idx).cell, &uci_value, &pdsch_ack); srslte_enb_dl_get_ack(&cell_cfg_list->at(ue.cell_info[0].enb_cc_idx).cell, &uci_value, &pdsch_ack);
// Iterate over the ACK information // Iterate over the ACK information
for (uint32_t scell_idx = 0; scell_idx < SRSLTE_MAX_CARRIERS; scell_idx++) { for (uint32_t scell_idx = 0; scell_idx < SRSLTE_MAX_CARRIERS; scell_idx++) {
@ -441,7 +442,7 @@ void phy_ue_db::send_uci_data(uint32_t tti,
for (uint32_t m = 0; m < pdsch_ack_cc.M; m++) { for (uint32_t m = 0; m < pdsch_ack_cc.M; m++) {
if (pdsch_ack_cc.m[m].present) { if (pdsch_ack_cc.m[m].present) {
for (uint32_t tb = 0; tb < pdsch_ack_cc.m[m].k; tb++) { for (uint32_t tb = 0; tb < pdsch_ack_cc.m[m].k; tb++) {
stack->ack_info(tti, rnti, ue.scell_info[scell_idx].cc_idx, tb, pdsch_ack_cc.m[m].value[tb] == 1); stack->ack_info(tti, rnti, ue.cell_info[scell_idx].enb_cc_idx, tb, pdsch_ack_cc.m[m].value[tb] == 1);
} }
} }
} }
@ -451,8 +452,8 @@ void phy_ue_db::send_uci_data(uint32_t tti,
UE_DB_ASSERT_ACTIVE_SCELL(rnti, uci_cfg.cqi.scell_index, /* void */); UE_DB_ASSERT_ACTIVE_SCELL(rnti, uci_cfg.cqi.scell_index, /* void */);
// Get CQI carrier index // Get CQI carrier index
auto& cqi_scell_info = ue_db.at(rnti).scell_info[uci_cfg.cqi.scell_index]; auto& cqi_scell_info = ue_db.at(rnti).cell_info[uci_cfg.cqi.scell_index];
uint32_t cqi_cc_idx = cqi_scell_info.cc_idx; uint32_t cqi_cc_idx = cqi_scell_info.enb_cc_idx;
// Notify CQI only if CRC is valid // Notify CQI only if CRC is valid
if (uci_value.cqi.data_crc) { if (uci_value.cqi.data_crc) {
@ -509,7 +510,7 @@ void phy_ue_db::set_last_ul_tb(uint16_t rnti, uint32_t cc_idx, uint32_t pid, srs
UE_DB_ASSERT_ACTIVE_CELL(rnti, cc_idx, /* void */); UE_DB_ASSERT_ACTIVE_CELL(rnti, cc_idx, /* void */);
// Save resource allocation // Save resource allocation
ue_db.at(rnti).scell_info[_get_scell_idx(rnti, cc_idx)].last_tb[pid % SRSLTE_FDD_NOF_HARQ] = tb; ue_db.at(rnti).cell_info[_get_cell_idx(rnti, cc_idx)].last_tb[pid % SRSLTE_FDD_NOF_HARQ] = tb;
} }
srslte_ra_tb_t phy_ue_db::get_last_ul_tb(uint16_t rnti, uint32_t cc_idx, uint32_t pid) const srslte_ra_tb_t phy_ue_db::get_last_ul_tb(uint16_t rnti, uint32_t cc_idx, uint32_t pid) const
@ -520,5 +521,5 @@ srslte_ra_tb_t phy_ue_db::get_last_ul_tb(uint16_t rnti, uint32_t cc_idx, uint32_
UE_DB_ASSERT_ACTIVE_CELL(rnti, cc_idx, {}); UE_DB_ASSERT_ACTIVE_CELL(rnti, cc_idx, {});
// Returns the latest stored UL transmission grant // Returns the latest stored UL transmission grant
return ue_db.at(rnti).scell_info[_get_scell_idx(rnti, cc_idx)].last_tb[pid % SRSLTE_FDD_NOF_HARQ]; return ue_db.at(rnti).cell_info[_get_cell_idx(rnti, cc_idx)].last_tb[pid % SRSLTE_FDD_NOF_HARQ];
} }

14
srsenb/src/stack/rrc/rrc.cc
Unescape Escape View File

@ -1666,7 +1666,7 @@ void rrc::ue::send_connection_setup(bool is_setup)
parent->pdcp->add_bearer(rnti, 1, srslte::make_srb_pdcp_config_t(1, false)); parent->pdcp->add_bearer(rnti, 1, srslte::make_srb_pdcp_config_t(1, false));
// Configure PHY layer // Configure PHY layer
apply_setup_phy_config(*phy_cfg); // It assumes SCell has not been set before apply_setup_phy_config_dedicated(*phy_cfg); // It assumes SCell has not been set before
parent->mac->phy_config_enabled(rnti, false); parent->mac->phy_config_enabled(rnti, false);
rr_cfg->drb_to_add_mod_list_present = false; rr_cfg->drb_to_add_mod_list_present = false;
@ -2199,23 +2199,23 @@ void rrc::ue::apply_setup_phy_common(const asn1::rrc::rr_cfg_common_sib_s& confi
set_phy_cfg_t_common_srs(&current_phy_cfg, config.srs_ul_cfg_common); set_phy_cfg_t_common_srs(&current_phy_cfg, config.srs_ul_cfg_common);
set_phy_cfg_t_common_pwr_ctrl(&current_phy_cfg, config.ul_pwr_ctrl_common); set_phy_cfg_t_common_pwr_ctrl(&current_phy_cfg, config.ul_pwr_ctrl_common);
// Set PCell index
phy_rrc_dedicated_list[0].configured = true;
phy_rrc_dedicated_list[0].enb_cc_idx = current_sched_ue_cfg.supported_cc_list[0].enb_cc_idx;
// Send configuration to physical layer // Send configuration to physical layer
if (parent->phy != nullptr) { if (parent->phy != nullptr) {
parent->phy->set_config_dedicated(rnti, phy_rrc_dedicated_list); parent->phy->set_config_dedicated(rnti, phy_rrc_dedicated_list);
} }
} }
void rrc::ue::apply_setup_phy_config(const asn1::rrc::phys_cfg_ded_s& phys_cfg_ded) void rrc::ue::apply_setup_phy_config_dedicated(const asn1::rrc::phys_cfg_ded_s& phys_cfg_ded)
{ {
// Return if no cell is supported // Return if no cell is supported
if (phy_rrc_dedicated_list.empty()) { if (phy_rrc_dedicated_list.empty()) {
return; return;
} }
// Set PCell index
phy_rrc_dedicated_list[0].configured = true;
phy_rrc_dedicated_list[0].cc_idx = current_sched_ue_cfg.supported_cc_list[0].enb_cc_idx;
// Load PCell dedicated configuration // Load PCell dedicated configuration
srslte::set_phy_cfg_t_dedicated_cfg(&phy_rrc_dedicated_list[0].phy_cfg, phys_cfg_ded); srslte::set_phy_cfg_t_dedicated_cfg(&phy_rrc_dedicated_list[0].phy_cfg, phys_cfg_ded);
@ -2271,7 +2271,7 @@ void rrc::ue::apply_reconf_phy_config(const asn1::rrc::rrc_conn_recfg_r8_ies_s&
// Set eNb Cell/Carrier index // Set eNb Cell/Carrier index
phy_rrc_dedicated.configured = true; phy_rrc_dedicated.configured = true;
phy_rrc_dedicated.cc_idx = current_sched_ue_cfg.supported_cc_list[scell_idx].enb_cc_idx; phy_rrc_dedicated.enb_cc_idx = current_sched_ue_cfg.supported_cc_list[scell_idx].enb_cc_idx;
// Set SCell configuration // Set SCell configuration
srslte::set_phy_cfg_t_scell_config(&phy_rrc_dedicated.phy_cfg, scell_config); srslte::set_phy_cfg_t_scell_config(&phy_rrc_dedicated.phy_cfg, scell_config);

6
srsenb/test/phy/enb_phy_test.cc
Unescape Escape View File

@ -741,7 +741,7 @@ public:
} }
for (auto& q : phy_rrc_cfg) { for (auto& q : phy_rrc_cfg) {
uint32_t cc_idx = q.cc_idx; uint32_t cc_idx = q.enb_cc_idx;
// Allocate UE DL // Allocate UE DL
auto* ue_dl = (srslte_ue_dl_t*)srslte_vec_malloc(sizeof(srslte_ue_dl_t)); auto* ue_dl = (srslte_ue_dl_t*)srslte_vec_malloc(sizeof(srslte_ue_dl_t));
@ -842,7 +842,7 @@ public:
// Get grants DL/UL, we do not care about Decoding PDSCH // Get grants DL/UL, we do not care about Decoding PDSCH
for (uint32_t i = 0; i < phy_rrc_cfg.size(); i++) { for (uint32_t i = 0; i < phy_rrc_cfg.size(); i++) {
uint32_t cc_idx = phy_rrc_cfg[i].cc_idx; uint32_t cc_idx = phy_rrc_cfg[i].enb_cc_idx;
srslte::phy_cfg_t& dedicated = phy_rrc_cfg[i].phy_cfg; srslte::phy_cfg_t& dedicated = phy_rrc_cfg[i].phy_cfg;
/// Set UCI configuration from PCell only /// Set UCI configuration from PCell only
@ -1100,7 +1100,7 @@ public:
bool activation[SRSLTE_MAX_CARRIERS] = {}; ///< Activation/Deactivation vector bool activation[SRSLTE_MAX_CARRIERS] = {}; ///< Activation/Deactivation vector
phy_rrc_cfg.resize(args.ue_cell_list.size()); phy_rrc_cfg.resize(args.ue_cell_list.size());
for (uint32_t i = 0; i < args.ue_cell_list.size(); i++) { for (uint32_t i = 0; i < args.ue_cell_list.size(); i++) {
phy_rrc_cfg[i].cc_idx = args.ue_cell_list[i]; ///< First element is PCell phy_rrc_cfg[i].enb_cc_idx = args.ue_cell_list[i]; ///< First element is PCell
phy_rrc_cfg[i].configured = true; ///< All configured by default phy_rrc_cfg[i].configured = true; ///< All configured by default
phy_rrc_cfg[i].phy_cfg = dedicated; ///< Load the same in all by default phy_rrc_cfg[i].phy_cfg = dedicated; ///< Load the same in all by default
phy_rrc_cfg[i].phy_cfg.dl_cfg.cqi_report.pmi_idx += i; ///< CQI report depend on SCell index phy_rrc_cfg[i].phy_cfg.dl_cfg.cqi_report.pmi_idx += i; ///< CQI report depend on SCell index

3
srsue/src/stack/rrc/rrc_procedures.cc
Unescape Escape View File

@ -78,7 +78,7 @@ proc_outcome_t rrc::cell_search_proc::step_si_acquire()
proc_outcome_t rrc::cell_search_proc::handle_cell_found(const phy_interface_rrc_lte::phy_cell_t& new_cell) proc_outcome_t rrc::cell_search_proc::handle_cell_found(const phy_interface_rrc_lte::phy_cell_t& new_cell)
{ {
Info("Cell found in this frequency. Setting new serving cell...\n"); Info("Cell found in this frequency. Setting new serving cell EARFCN=%d PCI=%d ...\n", new_cell.earfcn, new_cell.pci);
// Create a cell with NaN RSRP. Will be updated by new_phy_meas() during SIB search. // Create a cell with NaN RSRP. Will be updated by new_phy_meas() during SIB search.
if (not rrc_ptr->add_neighbour_cell(unique_cell_t(new cell_t(new_cell)))) { if (not rrc_ptr->add_neighbour_cell(unique_cell_t(new cell_t(new_cell)))) {
@ -497,7 +497,6 @@ proc_outcome_t rrc::cell_selection_proc::start_cell_selection()
discard_serving = false; discard_serving = false;
Info("Selected cell: %s\n", rrc_ptr->serving_cell->to_string().c_str()); Info("Selected cell: %s\n", rrc_ptr->serving_cell->to_string().c_str());
/* BLOCKING CALL */
state = search_state_t::cell_selection; state = search_state_t::cell_selection;
rrc_ptr->stack->start_cell_select(&rrc_ptr->serving_cell->phy_cell); rrc_ptr->stack->start_cell_select(&rrc_ptr->serving_cell->phy_cell);
return proc_outcome_t::yield; return proc_outcome_t::yield;

Write Preview
Loading…
Cancel
Save