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@ -27,54 +27,56 @@
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#include "srsran/phy/utils/vector.h"
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#include "srsran/phy/utils/vector.h"
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// n_dmrs_2 table 5.5.2.1.1-1 from 36.211
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// n_dmrs_2 table 5.5.2.1.1-1 from 36.211
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uint32_t n_dmrs_2[8] = {0, 6, 3, 4, 2, 8, 10, 9};
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static const uint32_t n_dmrs_2[8] = {0, 6, 3, 4, 2, 8, 10, 9};
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// n_dmrs_1 table 5.5.2.1.1-2 from 36.211
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// n_dmrs_1 table 5.5.2.1.1-2 from 36.211
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uint32_t n_dmrs_1[8] = {0, 2, 3, 4, 6, 8, 9, 10};
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static const uint32_t n_dmrs_1[8] = {0, 2, 3, 4, 6, 8, 9, 10};
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/* Orthogonal sequences for PUCCH formats 1a, 1b and 1c. Table 5.5.2.2.1-2
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/* Orthogonal sequences for PUCCH formats 1a, 1b and 1c. Table 5.5.2.2.1-2
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*/
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*/
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float w_arg_pucch_format1_cpnorm[3][3] = {{0, 0, 0}, {0, 2 * M_PI / 3, 4 * M_PI / 3}, {0, 4 * M_PI / 3, 2 * M_PI / 3}};
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static const float w_arg_pucch_format1_cpnorm[3][3] = {{0, 0, 0},
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{0, 2 * M_PI / 3, 4 * M_PI / 3},
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{0, 4 * M_PI / 3, 2 * M_PI / 3}};
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float w_arg_pucch_format1_cpext[3][2] = {{0, 0}, {0, M_PI}, {0, 0}};
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static const float w_arg_pucch_format1_cpext[3][2] = {{0, 0}, {0, M_PI}, {0, 0}};
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float w_arg_pucch_format2_cpnorm[2] = {0, 0};
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static const float w_arg_pucch_format2_cpnorm[2] = {0, 0};
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float w_arg_pucch_format2_cpext[1] = {0};
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static const float w_arg_pucch_format2_cpext[1] = {0};
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uint32_t pucch_dmrs_symbol_format1_cpnorm[3] = {2, 3, 4};
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static const uint32_t pucch_dmrs_symbol_format1_cpnorm[3] = {2, 3, 4};
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uint32_t pucch_dmrs_symbol_format1_cpext[2] = {2, 3};
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static const uint32_t pucch_dmrs_symbol_format1_cpext[2] = {2, 3};
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uint32_t pucch_dmrs_symbol_format2_cpnorm[2] = {1, 5};
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static const uint32_t pucch_dmrs_symbol_format2_cpnorm[2] = {1, 5};
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uint32_t pucch_dmrs_symbol_format2_cpext[1] = {3};
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static const uint32_t pucch_dmrs_symbol_format2_cpext[1] = {3};
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/* Table 5.5.3.3-1: Frame structure type 1 sounding reference signal subframe configuration. */
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/* Table 5.5.3.3-1: Frame structure type 1 sounding reference signal subframe configuration. */
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uint32_t T_sfc[15] = {1, 2, 2, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10, 10};
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static const uint32_t T_sfc[15] = {1, 2, 2, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10, 10};
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uint32_t Delta_sfc1[7] = {0, 0, 1, 0, 1, 2, 3};
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static const uint32_t Delta_sfc1[7] = {0, 0, 1, 0, 1, 2, 3};
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uint32_t Delta_sfc2[4] = {0, 1, 2, 3};
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static const uint32_t Delta_sfc2[4] = {0, 1, 2, 3};
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uint32_t m_srs_b[4][4][8] = {{/* m_srs for 6<n_rb<40. Table 5.5.3.2-1 */
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static const uint32_t m_srs_b[4][4][8] = {{/* m_srs for 6<n_rb<40. Table 5.5.3.2-1 */
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{36, 32, 24, 20, 16, 12, 8, 4},
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{36, 32, 24, 20, 16, 12, 8, 4},
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{12, 16, 4, 4, 4, 4, 4, 4},
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{12, 16, 4, 4, 4, 4, 4, 4},
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{4, 8, 4, 4, 4, 4, 4, 4},
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{4, 8, 4, 4, 4, 4, 4, 4},
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{4, 4, 4, 4, 4, 4, 4, 4}},
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{4, 4, 4, 4, 4, 4, 4, 4}},
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{/* m_srs for 40<n_rb<60. Table 5.5.3.2-2 */
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{/* m_srs for 40<n_rb<60. Table 5.5.3.2-2 */
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{48, 48, 40, 36, 32, 24, 20, 16},
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{48, 48, 40, 36, 32, 24, 20, 16},
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{24, 16, 20, 12, 16, 4, 4, 4},
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{24, 16, 20, 12, 16, 4, 4, 4},
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{12, 8, 4, 4, 8, 4, 4, 4},
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{12, 8, 4, 4, 8, 4, 4, 4},
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{4, 4, 4, 4, 4, 4, 4, 4}},
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{4, 4, 4, 4, 4, 4, 4, 4}},
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{/* m_srs for 60<n_rb<80. Table 5.5.3.2-3 */
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{/* m_srs for 60<n_rb<80. Table 5.5.3.2-3 */
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{72, 64, 60, 48, 48, 40, 36, 32},
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{72, 64, 60, 48, 48, 40, 36, 32},
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{24, 32, 20, 24, 16, 20, 12, 16},
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{24, 32, 20, 24, 16, 20, 12, 16},
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{12, 16, 4, 12, 8, 4, 4, 8},
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{12, 16, 4, 12, 8, 4, 4, 8},
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{4, 4, 4, 4, 4, 4, 4, 4}},
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{4, 4, 4, 4, 4, 4, 4, 4}},
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{/* m_srs for 80<n_rb<110. Table 5.5.3.2-4 */
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{/* m_srs for 80<n_rb<110. Table 5.5.3.2-4 */
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{96, 96, 80, 72, 64, 60, 48, 48},
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{96, 96, 80, 72, 64, 60, 48, 48},
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{48, 32, 40, 24, 32, 20, 24, 16},
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{48, 32, 40, 24, 32, 20, 24, 16},
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{24, 16, 20, 12, 16, 4, 12, 8},
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{24, 16, 20, 12, 16, 4, 12, 8},
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{4, 4, 4, 4, 4, 4, 4, 4}}};
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{4, 4, 4, 4, 4, 4, 4, 4}}};
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/* Same tables for Nb */
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/* Same tables for Nb */
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uint32_t Nb[4][4][8] = {
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static const uint32_t Nb[4][4][8] = {
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{{1, 1, 1, 1, 1, 1, 1, 1}, {3, 2, 6, 5, 4, 3, 2, 1}, {3, 2, 1, 1, 1, 1, 1, 1}, {1, 2, 1, 1, 1, 1, 1, 1}},
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{{1, 1, 1, 1, 1, 1, 1, 1}, {3, 2, 6, 5, 4, 3, 2, 1}, {3, 2, 1, 1, 1, 1, 1, 1}, {1, 2, 1, 1, 1, 1, 1, 1}},
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{{1, 1, 1, 1, 1, 1, 1, 1}, {2, 3, 2, 3, 2, 6, 5, 4}, {2, 2, 5, 3, 2, 1, 1, 1}, {3, 2, 1, 1, 2, 1, 1, 1}},
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{{1, 1, 1, 1, 1, 1, 1, 1}, {2, 3, 2, 3, 2, 6, 5, 4}, {2, 2, 5, 3, 2, 1, 1, 1}, {3, 2, 1, 1, 2, 1, 1, 1}},
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{{1, 1, 1, 1, 1, 1, 1, 1}, {3, 2, 3, 2, 3, 2, 3, 2}, {2, 2, 5, 2, 2, 5, 3, 2}, {3, 4, 1, 3, 2, 1, 1, 2}},
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{{1, 1, 1, 1, 1, 1, 1, 1}, {3, 2, 3, 2, 3, 2, 3, 2}, {2, 2, 5, 2, 2, 5, 3, 2}, {3, 4, 1, 3, 2, 1, 1, 2}},
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@ -457,7 +459,7 @@ int srsran_refsignal_dmrs_pucch_gen(srsran_refsignal_ul_t* q,
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}
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}
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// Choose number of symbols and orthogonal sequence from Tables 5.5.2.2.1-1 to -3
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// Choose number of symbols and orthogonal sequence from Tables 5.5.2.2.1-1 to -3
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float* w = NULL;
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const float* w = NULL;
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switch (cfg->format) {
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switch (cfg->format) {
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case SRSRAN_PUCCH_FORMAT_1:
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case SRSRAN_PUCCH_FORMAT_1:
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case SRSRAN_PUCCH_FORMAT_1A:
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case SRSRAN_PUCCH_FORMAT_1A:
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