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@ -17,6 +17,9 @@
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#include "srsran/support/srsran_test.h"
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#include "srsran/support/srsran_test.h"
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#include <random>
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#include <random>
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uint32_t seed = 155556739;
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// std::chrono::system_clock::now().time_since_epoch().count();
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namespace srsenb {
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namespace srsenb {
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void test_single_prach()
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void test_single_prach()
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@ -24,20 +27,20 @@ void test_single_prach()
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using namespace sched_nr_impl;
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using namespace sched_nr_impl;
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const uint16_t rnti = 0x1234;
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const uint16_t rnti = 0x1234;
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static srslog::basic_logger& mac_logger = srslog::fetch_basic_logger("MAC");
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static srslog::basic_logger& mac_logger = srslog::fetch_basic_logger("MAC");
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std::random_device r;
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std::default_random_engine rand_gen(seed);
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std::default_random_engine rgen(r());
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std::default_random_engine rgen(rand_gen());
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sched_nr_interface::sched_cfg_t sched_cfg{};
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sched_nr_interface::sched_cfg_t sched_cfg{};
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std::vector<sched_nr_interface::cell_cfg_t> cells_cfg = get_default_cells_cfg(1);
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std::vector<sched_nr_interface::cell_cfg_t> cells_cfg = get_default_cells_cfg(1);
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sched_params schedparams{sched_cfg};
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sched_params schedparams{sched_cfg};
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schedparams.cells.emplace_back(0, cells_cfg[0], sched_cfg);
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schedparams.cells.emplace_back(0, cells_cfg[0], sched_cfg);
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bwp_params bwp_cfg(cells_cfg[0], sched_cfg, 0, 0);
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const bwp_params& bwpparams = schedparams.cells[0].bwps[0];
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slot_ue_map_t slot_ues;
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slot_ue_map_t slot_ues;
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ra_sched rasched(bwp_cfg);
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ra_sched rasched(bwpparams);
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TESTASSERT(rasched.empty());
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TESTASSERT(rasched.empty());
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std::unique_ptr<bwp_res_grid> res_grid(new bwp_res_grid{bwp_cfg});
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std::unique_ptr<bwp_res_grid> res_grid(new bwp_res_grid{bwpparams});
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bwp_slot_allocator alloc(*res_grid);
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bwp_slot_allocator alloc(*res_grid);
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// Create UE
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// Create UE
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@ -54,6 +57,8 @@ void test_single_prach()
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slot_ues.insert(rnti, u.try_reserve(pdcch_slot, 0));
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slot_ues.insert(rnti, u.try_reserve(pdcch_slot, 0));
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alloc.new_slot(pdcch_slot, slot_ues);
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alloc.new_slot(pdcch_slot, slot_ues);
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rasched.run_slot(alloc);
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rasched.run_slot(alloc);
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alloc.log_bwp_sched_result();
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const bwp_slot_grid* result = &alloc.res_grid()[alloc.get_pdcch_tti()];
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const bwp_slot_grid* result = &alloc.res_grid()[alloc.get_pdcch_tti()];
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test_pdcch_consistency(result->dl_pdcchs);
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test_pdcch_consistency(result->dl_pdcchs);
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++pdcch_slot;
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++pdcch_slot;
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@ -77,14 +82,17 @@ void test_single_prach()
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uint16_t ra_rnti = 1 + rainfo.ofdm_symbol_idx + 14 * rainfo.prach_slot.slot_idx() + 14 * 80 * rainfo.freq_idx;
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uint16_t ra_rnti = 1 + rainfo.ofdm_symbol_idx + 14 * rainfo.prach_slot.slot_idx() + 14 * 80 * rainfo.freq_idx;
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// RAR is scheduled
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// RAR is scheduled
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const uint32_t prach_duration = 1;
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while (true) {
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while (true) {
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result = run_slot();
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slot_point current_slot = pdcch_slot;
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if (result->is_dl()) {
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result = run_slot();
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TESTASSERT(result->dl_pdcchs.size() == 1);
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if (bwpparams.slots[current_slot.slot_idx()].is_dl and
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bwpparams.slots[(current_slot + bwpparams.pusch_ra_list[0].msg3_delay).slot_idx()].is_ul) {
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TESTASSERT_EQ(result->dl_pdcchs.size(), 1);
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const auto& pdcch = result->dl_pdcchs[0];
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const auto& pdcch = result->dl_pdcchs[0];
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TESTASSERT_EQ(pdcch.dci.ctx.rnti, ra_rnti);
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TESTASSERT_EQ(pdcch.dci.ctx.rnti, ra_rnti);
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TESTASSERT_EQ(pdcch.dci.ctx.rnti_type, srsran_rnti_type_ra);
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TESTASSERT_EQ(pdcch.dci.ctx.rnti_type, srsran_rnti_type_ra);
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TESTASSERT(pdcch_slot < prach_slot + bwp_cfg.cell_cfg.bwps[0].rar_window_size);
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TESTASSERT(current_slot < prach_slot + prach_duration + bwpparams.cfg.rar_window_size);
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break;
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break;
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} else {
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} else {
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TESTASSERT(result->dl_pdcchs.empty());
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TESTASSERT(result->dl_pdcchs.empty());
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@ -103,5 +111,7 @@ int main(int argc, char** argv)
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srsran::test_init(argc, argv);
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srsran::test_init(argc, argv);
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printf("Test seed=%u\n", seed);
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srsenb::test_single_prach();
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srsenb::test_single_prach();
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}
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}
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