mirror of https://github.com/pvnis/srsRAN_4G.git
SRSENB: Refactor to accomodate 5G NR
Xavier Arteaga
3 years ago
committed by
Xavier Arteaga
parent
e98a6f9eea
commit
d49734b1bc
@ -0,0 +1,101 @@
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/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2020 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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#ifndef SRSENB_PHY_NR_UE_DB_H_
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#define SRSENB_PHY_NR_UE_DB_H_
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#include <map>
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#include <mutex>
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#include <srsenb/hdr/phy/phy_interfaces.h>
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#include <srsran/adt/circular_array.h>
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#include <srsran/interfaces/gnb_interfaces.h>
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#include <srsran/interfaces/rrc_nr_interface_types.h>
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namespace srsenb {
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namespace nr {
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class phy_nr_state
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{
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private:
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/**
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* UE object stored in the PHY common database
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*/
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struct common_ue {
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srsran::phy_cfg_nr_t cfg;
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};
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/**
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* UE database indexed by RNTI
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*/
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std::map<uint16_t, common_ue> ue_db;
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/**
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* Concurrency protection mutex, allowed modifications from const methods.
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*/
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mutable std::mutex mutex;
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/**
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* Stack interface
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*/
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stack_interface_phy_nr& stack;
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/**
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* Cell list
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*/
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const phy_cell_cfg_list_nr_t& cell_cfg_list;
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/**
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* Internal RNTI addition, it is not thread safe protected
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*
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* @param rnti identifier of the UE
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* @return SRSRAN_SUCCESS if the RNTI is not duplicated and is added successfully, SRSRAN_ERROR code if it exists
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*/
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inline int _add_rnti(uint16_t rnti);
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/**
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* Checks if a given RNTI exists in the database
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* @param rnti provides UE identifier
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* @return SRSRAN_SUCCESS if the indicated RNTI exists, otherwise it returns SRSRAN_ERROR
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*/
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inline int _assert_rnti(uint16_t rnti) const;
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/**
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* Internal eNb general configuration getter, returns default configuration if the UE does not exist in the given cell
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*
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* @param rnti provides UE identifier
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* @param[out] phy_cfg The PHY configuration of the indicated UE for the indicated eNb carrier/call index.
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* @return SRSRAN_SUCCESS if provided context is correct, SRSRAN_ERROR code otherwise
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*/
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inline int _get_rnti_config(uint16_t rnti, srsran::phy_cfg_nr_t& phy_cfg) const;
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public:
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phy_nr_state(const phy_cell_cfg_list_nr_t& cell_cfg_list_, stack_interface_phy_nr& stack_);
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void addmod_rnti(uint16_t rnti, const srsran::phy_cfg_nr_t& phy_cfg);
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/**
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* Removes a whole UE entry from the UE database
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*
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* @param rnti identifier of the UE
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* @return SRSRAN_SUCCESS if provided RNTI exists, SRSRAN_ERROR code otherwise
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*/
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int rem_rnti(uint16_t rnti);
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const phy_cell_cfg_list_nr_t& get_carrier_list() const { return cell_cfg_list; }
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stack_interface_phy_nr& get_stack() { return stack; }
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};
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} // namespace nr
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} // namespace srsenb
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#endif // SRSENB_PHY_NR_UE_DB_H_
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@ -0,0 +1,79 @@
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/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2021 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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#include "srsenb/hdr/phy/nr/phy_nr_state.h"
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namespace srsenb {
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namespace nr {
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int phy_nr_state::_add_rnti(uint16_t rnti)
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{
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if (ue_db.count(rnti) > 0) {
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return SRSRAN_ERROR;
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}
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// Access UE to create
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// Set defaults
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ue_db[rnti] = {};
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return SRSRAN_SUCCESS;
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}
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int phy_nr_state::_assert_rnti(uint16_t rnti) const
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{
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return ue_db.count(rnti) > 0 ? SRSRAN_SUCCESS : SRSRAN_ERROR;
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}
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int phy_nr_state::_get_rnti_config(uint16_t rnti, srsran::phy_cfg_nr_t& phy_cfg) const
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{
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std::lock_guard<std::mutex> lock(mutex);
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if (_assert_rnti(rnti) < SRSRAN_SUCCESS) {
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return SRSRAN_ERROR;
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}
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phy_cfg = ue_db.at(rnti).cfg;
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return SRSRAN_SUCCESS;
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}
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phy_nr_state::phy_nr_state(const phy_cell_cfg_list_nr_t& cell_cfg_list_, stack_interface_phy_nr& stack_) :
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cell_cfg_list(cell_cfg_list_), stack(stack_)
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{}
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void phy_nr_state::addmod_rnti(uint16_t rnti, const srsran::phy_cfg_nr_t& phy_cfg)
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{
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std::lock_guard<std::mutex> lock(mutex);
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// Create UE if it does not exist
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if (_assert_rnti(rnti) < SRSRAN_SUCCESS) {
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_add_rnti(rnti);
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}
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// Set UE configuration
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ue_db[rnti].cfg = phy_cfg;
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}
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int phy_nr_state::rem_rnti(uint16_t rnti)
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{
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std::lock_guard<std::mutex> lock(mutex);
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if (_assert_rnti(rnti) < SRSRAN_SUCCESS) {
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return SRSRAN_ERROR;
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}
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ue_db.erase(rnti);
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return SRSRAN_SUCCESS;
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}
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} // namespace nr
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} // namespace srsenb
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@ -0,0 +1,233 @@
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/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2021 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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#ifndef SRSRAN_DUMMY_PHY_COMMON_H
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#define SRSRAN_DUMMY_PHY_COMMON_H
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#include <srsran/common/tti_sempahore.h>
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#include <srsran/interfaces/phy_common_interface.h>
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#include <srsran/srslog/srslog.h>
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#include <srsran/srsran.h>
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#include <vector>
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class phy_common : public srsran::phy_common_interface
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{
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private:
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const uint32_t RINGBUFFER_TIMEOUT_MS = 10;
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bool quit = false;
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srslog::basic_logger& logger;
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double srate_hz;
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uint64_t write_ts = 0;
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uint64_t read_ts = 0;
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std::vector<cf_t> zero_buffer; ///< Zero buffer for Tx
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std::vector<cf_t> sink_buffer; ///< Dummy buffer for Rx
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std::vector<srsran_ringbuffer_t> ringbuffers;
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srsran::tti_semaphore<void*> semaphore;
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void write_zero_padding(uint32_t nof_zeros)
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{
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// Skip if no pading is required
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if (nof_zeros == 0) {
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return;
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}
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logger.debug("Padding %d zeros", nof_zeros);
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// For each ringbuffer, padd zero
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int nof_bytes = (int)(nof_zeros * sizeof(cf_t));
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for (srsran_ringbuffer_t& rb : ringbuffers) {
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// If quit is flagged, return instantly
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if (quit) {
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return;
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}
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// Actual write
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int err = SRSRAN_SUCCESS;
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do {
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err = srsran_ringbuffer_write_timed(&rb, zero_buffer.data(), nof_bytes, RINGBUFFER_TIMEOUT_MS);
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if (err < SRSRAN_SUCCESS and err != SRSRAN_ERROR_TIMEOUT) {
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logger.error("Error writing zeros in ringbuffer");
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}
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} while (err < SRSRAN_SUCCESS and not quit);
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}
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// Increment write timestamp
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write_ts += nof_zeros;
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}
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void write_baseband(srsran::rf_buffer_t& buffer)
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{
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// skip if baseband is not available
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if (buffer.get_nof_samples() == 0) {
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return;
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}
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// For each ringbuffer, write
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int nof_bytes = (int)(buffer.get_nof_samples() * sizeof(cf_t));
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uint32_t channel_idx = 0;
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for (srsran_ringbuffer_t& rb : ringbuffers) {
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// If quit is flagged, return instantly
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if (quit) {
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return;
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}
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// Extract channel buffer pointer
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cf_t* channel_buffer = buffer.get(channel_idx);
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// If the pointer is not set, use the zero buffer
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if (channel_buffer == nullptr) {
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channel_buffer = zero_buffer.data();
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}
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// Actual write
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int err = SRSRAN_SUCCESS;
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do {
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err = srsran_ringbuffer_write_timed(&rb, channel_buffer, nof_bytes, RINGBUFFER_TIMEOUT_MS);
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if (err < SRSRAN_SUCCESS and err != SRSRAN_ERROR_TIMEOUT) {
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logger.error("Error writing zeros in ringbuffer");
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}
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} while (err < SRSRAN_SUCCESS and not quit);
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// Increment channel counter
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channel_idx++;
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}
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// Increment write timestamp
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write_ts += buffer.get_nof_samples();
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}
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void read_baseband(std::vector<cf_t*>& buffers, uint32_t nof_samples)
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{
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// For each ringbuffer, read
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int nof_bytes = (int)(nof_samples * sizeof(cf_t));
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uint32_t channel_idx = 0;
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for (srsran_ringbuffer_t& rb : ringbuffers) {
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// If quit is flagged, return instantly
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if (quit) {
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return;
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}
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// Extract channel buffer pointer
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cf_t* channel_buffer = buffers[channel_idx];
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// If the pointer is not set, use the zero buffer
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if (channel_buffer == nullptr) {
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channel_buffer = sink_buffer.data();
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}
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// Actual write
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int err = SRSRAN_SUCCESS;
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do {
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err = srsran_ringbuffer_read_timed(&rb, channel_buffer, nof_bytes, RINGBUFFER_TIMEOUT_MS);
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if (err < SRSRAN_SUCCESS and err != SRSRAN_ERROR_TIMEOUT) {
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logger.error("Error reading zeros in ringbuffer");
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}
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} while (err < SRSRAN_SUCCESS and not quit);
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// Increment channel counter
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channel_idx++;
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}
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}
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public:
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struct args_t {
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double srate_hz = 11.52e6;
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uint32_t buffer_sz_ms = 10; ///< Buffer size in milliseconds
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uint32_t nof_channels = 1;
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args_t(double srate_hz_, uint32_t buffer_sz_ms_, uint32_t nof_channels_) :
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srate_hz(srate_hz_), buffer_sz_ms(buffer_sz_ms_), nof_channels(nof_channels_)
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{}
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};
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phy_common(const args_t& args, srslog::basic_logger& logger_) : srate_hz(args.srate_hz), logger(logger_)
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{
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uint32_t buffer_sz = std::ceil((double)args.buffer_sz_ms * srate_hz * 1e-3);
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uint32_t buffer_sz_bytes = sizeof(cf_t) * buffer_sz;
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// Allocate data buffer
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zero_buffer.resize(buffer_sz);
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sink_buffer.resize(buffer_sz);
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// Allocate ring buffers
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ringbuffers.resize(args.nof_channels);
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// Initialise buffers
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for (srsran_ringbuffer_t& rb : ringbuffers) {
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if (srsran_ringbuffer_init(&rb, buffer_sz_bytes) < SRSRAN_SUCCESS) {
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logger.error("Error ringbuffer init");
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}
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}
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}
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~phy_common()
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{
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for (srsran_ringbuffer_t& rb : ringbuffers) {
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srsran_ringbuffer_free(&rb);
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}
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}
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void push_semaphore(void* worker_ptr) { semaphore.push(worker_ptr); }
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void
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worker_end(void* h, bool tx_enable, srsran::rf_buffer_t& buffer, srsran::rf_timestamp_t& tx_time, bool is_nr) override
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{
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// Synchronize worker
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semaphore.wait(h);
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uint64_t tx_ts = srsran_timestamp_uint64(&tx_time.get(0), srate_hz);
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// Check transmit timestamp is not in the past
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if (tx_ts < write_ts) {
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logger.error("Tx time is %d samples in the past", (uint32_t)(write_ts - tx_ts));
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semaphore.release();
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return;
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}
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// Write zero padding if necessary
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write_zero_padding((uint32_t)(tx_ts - write_ts));
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// Write baseband
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if (tx_enable) {
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write_baseband(buffer);
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} else {
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write_zero_padding(buffer.get_nof_samples());
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}
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// Release semaphore, so next worker can be used
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semaphore.release();
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}
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void read(std::vector<cf_t*>& buffers, uint32_t nof_samples, srsran::rf_timestamp_t& timestamp)
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{
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// Detect if zero padding is necessary
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if (read_ts + nof_samples > write_ts) {
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uint32_t nof_zero_pading = (uint32_t)((read_ts + nof_samples) - write_ts);
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write_zero_padding(nof_zero_pading);
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}
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// Actual baseband read
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read_baseband(buffers, nof_samples);
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// Write timestamp
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srsran_timestamp_init_uint64(timestamp.get_ptr(0), read_ts, srate_hz);
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// Increment Rx timestamp
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read_ts += nof_samples;
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}
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void stop() {
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quit = true;
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}
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};
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#endif // SRSRAN_DUMMY_PHY_COMMON_H
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@ -0,0 +1,563 @@
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/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2021 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
|
||||
* forth in the LICENSE file which can be found at the top level of
|
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* the distribution.
|
||||
*
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*/
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#include "srsran/common/test_common.h"
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#include "test_bench.h"
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test_bench::args_t::args_t(int argc, char** argv)
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{
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// Flag configuration as valid
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valid = true;
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cell_list.resize(1);
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cell_list[0].carrier.nof_prb = 52;
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phy_cfg.carrier = cell_list[0].carrier;
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phy_cfg.carrier.pci = 500;
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phy_cfg.carrier.absolute_frequency_point_a = 633928;
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phy_cfg.carrier.absolute_frequency_ssb = 634176;
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phy_cfg.carrier.offset_to_carrier = 0;
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phy_cfg.carrier.scs = srsran_subcarrier_spacing_15kHz;
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phy_cfg.carrier.nof_prb = 52;
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phy_cfg.ssb.periodicity_ms = 5;
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phy_cfg.ssb.position_in_burst[0] = true;
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phy_cfg.ssb.scs = srsran_subcarrier_spacing_30kHz;
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phy_cfg.pdcch.coreset_present[1] = true;
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phy_cfg.pdcch.coreset[1].id = 1;
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phy_cfg.pdcch.coreset[1].freq_resources[0] = true;
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phy_cfg.pdcch.coreset[1].freq_resources[1] = true;
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phy_cfg.pdcch.coreset[1].freq_resources[2] = true;
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phy_cfg.pdcch.coreset[1].freq_resources[3] = true;
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phy_cfg.pdcch.coreset[1].freq_resources[4] = true;
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phy_cfg.pdcch.coreset[1].freq_resources[5] = true;
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phy_cfg.pdcch.coreset[1].freq_resources[6] = true;
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phy_cfg.pdcch.coreset[1].freq_resources[7] = true;
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phy_cfg.pdcch.coreset[1].duration = 1;
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phy_cfg.pdcch.coreset[1].mapping_type = srsran_coreset_mapping_type_non_interleaved;
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phy_cfg.pdcch.coreset[1].precoder_granularity = srsran_coreset_precoder_granularity_reg_bundle;
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phy_cfg.pdcch.coreset_present[2] = true;
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phy_cfg.pdcch.coreset[2].id = 2;
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phy_cfg.pdcch.coreset[2].freq_resources[0] = true;
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phy_cfg.pdcch.coreset[2].freq_resources[1] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[2] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[3] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[4] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[5] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[6] = true;
|
||||
phy_cfg.pdcch.coreset[2].freq_resources[7] = true;
|
||||
phy_cfg.pdcch.coreset[2].duration = 1;
|
||||
phy_cfg.pdcch.coreset[2].mapping_type = srsran_coreset_mapping_type_non_interleaved;
|
||||
phy_cfg.pdcch.coreset[2].precoder_granularity = srsran_coreset_precoder_granularity_reg_bundle;
|
||||
|
||||
phy_cfg.pdcch.search_space_present[1] = true;
|
||||
phy_cfg.pdcch.search_space[1].id = 1;
|
||||
phy_cfg.pdcch.search_space[1].coreset_id = 1;
|
||||
phy_cfg.pdcch.search_space[1].duration = 1;
|
||||
phy_cfg.pdcch.search_space[1].nof_candidates[0] = 1;
|
||||
phy_cfg.pdcch.search_space[1].nof_candidates[1] = 1;
|
||||
phy_cfg.pdcch.search_space[1].nof_candidates[2] = 1;
|
||||
phy_cfg.pdcch.search_space[1].nof_candidates[3] = 0;
|
||||
phy_cfg.pdcch.search_space[1].nof_candidates[4] = 0;
|
||||
phy_cfg.pdcch.search_space[1].formats[0] = srsran_dci_format_nr_0_0;
|
||||
phy_cfg.pdcch.search_space[1].formats[1] = srsran_dci_format_nr_1_0;
|
||||
phy_cfg.pdcch.search_space[1].nof_formats = 2;
|
||||
phy_cfg.pdcch.search_space[1].type = srsran_search_space_type_common_3;
|
||||
|
||||
phy_cfg.pdcch.search_space_present[2] = true;
|
||||
phy_cfg.pdcch.search_space[2].id = 2;
|
||||
phy_cfg.pdcch.search_space[2].coreset_id = 2;
|
||||
phy_cfg.pdcch.search_space[2].duration = 1;
|
||||
phy_cfg.pdcch.search_space[2].nof_candidates[0] = 0;
|
||||
phy_cfg.pdcch.search_space[2].nof_candidates[1] = 2;
|
||||
phy_cfg.pdcch.search_space[2].nof_candidates[2] = 1;
|
||||
phy_cfg.pdcch.search_space[2].nof_candidates[3] = 0;
|
||||
phy_cfg.pdcch.search_space[2].nof_candidates[4] = 0;
|
||||
phy_cfg.pdcch.search_space[2].formats[0] = srsran_dci_format_nr_0_0;
|
||||
phy_cfg.pdcch.search_space[2].formats[1] = srsran_dci_format_nr_1_0;
|
||||
phy_cfg.pdcch.search_space[2].nof_formats = 2;
|
||||
phy_cfg.pdcch.search_space[2].type = srsran_search_space_type_ue;
|
||||
|
||||
phy_cfg.pdcch.ra_search_space_present = true;
|
||||
phy_cfg.pdcch.ra_search_space = phy_cfg.pdcch.search_space[1];
|
||||
phy_cfg.pdcch.ra_search_space.type = srsran_search_space_type_common_1;
|
||||
|
||||
phy_cfg.pdsch.common_time_ra[0].mapping_type = srsran_sch_mapping_type_A;
|
||||
phy_cfg.pdsch.common_time_ra[0].sliv = 40;
|
||||
phy_cfg.pdsch.common_time_ra[1].mapping_type = srsran_sch_mapping_type_A;
|
||||
phy_cfg.pdsch.common_time_ra[1].sliv = 57;
|
||||
phy_cfg.pdsch.nof_common_time_ra = 2;
|
||||
|
||||
phy_cfg.pusch.common_time_ra[0].k = 4;
|
||||
phy_cfg.pusch.common_time_ra[0].mapping_type = srsran_sch_mapping_type_A;
|
||||
phy_cfg.pusch.common_time_ra[0].sliv = 27;
|
||||
phy_cfg.pusch.common_time_ra[1].k = 5;
|
||||
phy_cfg.pusch.common_time_ra[1].mapping_type = srsran_sch_mapping_type_A;
|
||||
phy_cfg.pusch.common_time_ra[1].sliv = 27;
|
||||
phy_cfg.pusch.nof_common_time_ra = 2;
|
||||
|
||||
phy_cfg.pdsch.typeA_pos = srsran_dmrs_sch_typeA_pos_2;
|
||||
phy_cfg.pusch.typeA_pos = srsran_dmrs_sch_typeA_pos_2;
|
||||
|
||||
phy_cfg.tdd.pattern1.period_ms = 10;
|
||||
phy_cfg.tdd.pattern1.nof_dl_slots = 7;
|
||||
phy_cfg.tdd.pattern1.nof_dl_symbols = 6;
|
||||
phy_cfg.tdd.pattern1.nof_ul_slots = 4;
|
||||
phy_cfg.tdd.pattern1.nof_ul_symbols = 4;
|
||||
|
||||
phy_cfg.pdsch.dmrs_typeA.additional_pos = srsran_dmrs_sch_add_pos_1;
|
||||
phy_cfg.pdsch.dmrs_typeA.present = true;
|
||||
phy_cfg.pdsch.alloc = srsran_resource_alloc_type1;
|
||||
|
||||
phy_cfg.pucch.enabled = true;
|
||||
srsran_pucch_nr_resource_t& pucch0 = phy_cfg.pucch.sets[0].resources[0];
|
||||
srsran_pucch_nr_resource_t& pucch1 = phy_cfg.pucch.sets[0].resources[1];
|
||||
srsran_pucch_nr_resource_t& pucch2 = phy_cfg.pucch.sets[0].resources[2];
|
||||
srsran_pucch_nr_resource_t& pucch3 = phy_cfg.pucch.sets[0].resources[3];
|
||||
srsran_pucch_nr_resource_t& pucch4 = phy_cfg.pucch.sets[0].resources[4];
|
||||
srsran_pucch_nr_resource_t& pucch5 = phy_cfg.pucch.sets[0].resources[5];
|
||||
srsran_pucch_nr_resource_t& pucch6 = phy_cfg.pucch.sets[0].resources[6];
|
||||
srsran_pucch_nr_resource_t& pucch7 = phy_cfg.pucch.sets[0].resources[7];
|
||||
phy_cfg.pucch.sets[0].nof_resources = 8;
|
||||
srsran_pucch_nr_resource_t& pucch8 = phy_cfg.pucch.sets[1].resources[0];
|
||||
srsran_pucch_nr_resource_t& pucch9 = phy_cfg.pucch.sets[1].resources[1];
|
||||
srsran_pucch_nr_resource_t& pucch10 = phy_cfg.pucch.sets[1].resources[2];
|
||||
srsran_pucch_nr_resource_t& pucch11 = phy_cfg.pucch.sets[1].resources[3];
|
||||
srsran_pucch_nr_resource_t& pucch12 = phy_cfg.pucch.sets[1].resources[4];
|
||||
srsran_pucch_nr_resource_t& pucch13 = phy_cfg.pucch.sets[1].resources[5];
|
||||
srsran_pucch_nr_resource_t& pucch14 = phy_cfg.pucch.sets[1].resources[6];
|
||||
srsran_pucch_nr_resource_t& pucch15 = phy_cfg.pucch.sets[1].resources[7];
|
||||
phy_cfg.pucch.sets[1].nof_resources = 8;
|
||||
|
||||
pucch0.starting_prb = 0;
|
||||
pucch0.format = SRSRAN_PUCCH_NR_FORMAT_1;
|
||||
pucch0.initial_cyclic_shift = 0;
|
||||
pucch0.nof_symbols = 14;
|
||||
pucch0.start_symbol_idx = 0;
|
||||
pucch0.time_domain_occ = 0;
|
||||
pucch1 = pucch0;
|
||||
pucch1.initial_cyclic_shift = 4;
|
||||
pucch1.time_domain_occ = 0;
|
||||
pucch2 = pucch0;
|
||||
pucch2.initial_cyclic_shift = 8;
|
||||
pucch2.time_domain_occ = 0;
|
||||
pucch3 = pucch0;
|
||||
pucch3.initial_cyclic_shift = 0;
|
||||
pucch3.time_domain_occ = 1;
|
||||
pucch4 = pucch0;
|
||||
pucch4.initial_cyclic_shift = 0;
|
||||
pucch4.time_domain_occ = 1;
|
||||
pucch5 = pucch0;
|
||||
pucch5.initial_cyclic_shift = 4;
|
||||
pucch5.time_domain_occ = 1;
|
||||
pucch6 = pucch0;
|
||||
pucch6.initial_cyclic_shift = 0;
|
||||
pucch6.time_domain_occ = 2;
|
||||
pucch7 = pucch0;
|
||||
pucch7.initial_cyclic_shift = 4;
|
||||
pucch7.time_domain_occ = 2;
|
||||
|
||||
pucch8.starting_prb = 51;
|
||||
pucch8.format = SRSRAN_PUCCH_NR_FORMAT_2;
|
||||
pucch8.nof_prb = 1;
|
||||
pucch8.nof_symbols = 2;
|
||||
pucch8.start_symbol_idx = 0;
|
||||
|
||||
pucch9 = pucch8;
|
||||
pucch9.start_symbol_idx = 2;
|
||||
pucch10 = pucch8;
|
||||
pucch10.start_symbol_idx = 4;
|
||||
pucch11 = pucch8;
|
||||
pucch11.start_symbol_idx = 6;
|
||||
pucch12 = pucch8;
|
||||
pucch12.start_symbol_idx = 8;
|
||||
pucch13 = pucch8;
|
||||
pucch13.start_symbol_idx = 10;
|
||||
pucch14 = pucch8;
|
||||
pucch14.start_symbol_idx = 12;
|
||||
pucch15 = pucch8;
|
||||
pucch15.starting_prb = 1;
|
||||
pucch15.start_symbol_idx = 0;
|
||||
|
||||
srsran_pucch_nr_resource_t& pucch16 = phy_cfg.pucch.sr_resources[1].resource;
|
||||
pucch16.starting_prb = 0;
|
||||
pucch16.format = SRSRAN_PUCCH_NR_FORMAT_1;
|
||||
pucch16.initial_cyclic_shift = 8;
|
||||
pucch16.nof_symbols = 14;
|
||||
pucch16.start_symbol_idx = 0;
|
||||
pucch16.time_domain_occ = 2;
|
||||
|
||||
phy_cfg.pucch.sr_resources[1].configured = true;
|
||||
phy_cfg.pucch.sr_resources[1].sr_id = 0;
|
||||
phy_cfg.pucch.sr_resources[1].period = 40;
|
||||
phy_cfg.pucch.sr_resources[1].offset = 8;
|
||||
phy_cfg.pucch.sr_resources[1].resource = pucch16;
|
||||
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[0] = 8;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[1] = 7;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[2] = 6;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[3] = 5;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[4] = 4;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[5] = 12;
|
||||
phy_cfg.harq_ack.dl_data_to_ul_ack[6] = 11;
|
||||
|
||||
phy_cfg.prach.freq_offset = 2;
|
||||
|
||||
// pusch-Config: setup (1)
|
||||
// setup
|
||||
// dmrs-UplinkForPUSCH-MappingTypeA: setup (1)
|
||||
// setup
|
||||
// dmrs-AdditionalPosition: pos1 (1)
|
||||
// transformPrecodingDisabled
|
||||
// pusch-PowerControl
|
||||
// msg3-Alpha: alpha1 (7)
|
||||
// p0-NominalWithoutGrant: -90dBm
|
||||
// p0-AlphaSets: 1 item
|
||||
// Item 0
|
||||
// P0-PUSCH-AlphaSet
|
||||
// p0-PUSCH-AlphaSetId: 0
|
||||
// p0: 0dB
|
||||
// alpha: alpha1 (7)
|
||||
// pathlossReferenceRSToAddModList: 1 item
|
||||
// Item 0
|
||||
// PUSCH-PathlossReferenceRS
|
||||
// pusch-PathlossReferenceRS-Id: 0
|
||||
// referenceSignal: ssb-Index (0)
|
||||
// ssb-Index: 0
|
||||
// sri-PUSCH-MappingToAddModList: 1 item
|
||||
// Item 0
|
||||
// SRI-PUSCH-PowerControl
|
||||
// sri-PUSCH-PowerControlId: 0
|
||||
// sri-PUSCH-PathlossReferenceRS-Id: 0
|
||||
// sri-P0-PUSCH-AlphaSetId: 0
|
||||
// sri-PUSCH-ClosedLoopIndex: i0 (0)
|
||||
// resourceAllocation: resourceAllocationType1 (1)
|
||||
// uci-OnPUSCH: setup (1)
|
||||
// setup
|
||||
// betaOffsets: semiStatic (1)
|
||||
// semiStatic
|
||||
// betaOffsetACK-Index1: 9
|
||||
// betaOffsetACK-Index2: 9
|
||||
// betaOffsetACK-Index3: 9
|
||||
// betaOffsetCSI-Part1-Index1: 6
|
||||
// betaOffsetCSI-Part1-Index2: 6
|
||||
// betaOffsetCSI-Part2-Index1: 6
|
||||
// betaOffsetCSI-Part2-Index2: 6
|
||||
// scaling: f1 (3)
|
||||
// srs-Config: setup (1)
|
||||
// setup
|
||||
// srs-ResourceSetToAddModList: 1 item
|
||||
// Item 0
|
||||
// SRS-ResourceSet
|
||||
// srs-ResourceSetId: 0
|
||||
// srs-ResourceIdList: 1 item
|
||||
// Item 0
|
||||
// SRS-ResourceId: 0
|
||||
// resourceType: aperiodic (0)
|
||||
// aperiodic
|
||||
// aperiodicSRS-ResourceTrigger: 1
|
||||
// slotOffset: 7
|
||||
// usage: codebook (1)
|
||||
// p0: -90dBm
|
||||
// pathlossReferenceRS: ssb-Index (0)
|
||||
// ssb-Index: 0
|
||||
// srs-ResourceToAddModList: 1 item
|
||||
// Item 0
|
||||
// SRS-Resource
|
||||
// srs-ResourceId: 0
|
||||
// nrofSRS-Ports: port1 (0)
|
||||
// transmissionComb: n2 (0)
|
||||
// n2
|
||||
// combOffset-n2: 0
|
||||
// cyclicShift-n2: 0
|
||||
// resourceMapping
|
||||
// startPosition: 0
|
||||
// nrofSymbols: n1 (0)
|
||||
// repetitionFactor: n1 (0)
|
||||
// freqDomainPosition: 0
|
||||
// freqDomainShift: 6
|
||||
// freqHopping
|
||||
// c-SRS: 11
|
||||
// b-SRS: 3
|
||||
// b-hop: 0
|
||||
// groupOrSequenceHopping: neither (0)
|
||||
// resourceType: aperiodic (0)
|
||||
// aperiodic
|
||||
// sequenceId: 500
|
||||
// firstActiveUplinkBWP-Id: 0
|
||||
// pusch-ServingCellConfig: setup (1)
|
||||
// setup
|
||||
// pdcch-ServingCellConfig: setup (1)
|
||||
// setup
|
||||
// pdsch-ServingCellConfig: setup (1)
|
||||
// setup
|
||||
// nrofHARQ-ProcessesForPDSCH: n16 (5)
|
||||
// csi-MeasConfig: setup (1)
|
||||
// setup
|
||||
// nzp-CSI-RS-ResourceToAddModList: 5 items
|
||||
// Item 0
|
||||
// NZP-CSI-RS-Resource
|
||||
// nzp-CSI-RS-ResourceId: 0
|
||||
// resourceMapping
|
||||
// frequencyDomainAllocation: row2 (1)
|
||||
// row2: 8000 [bit length 12, 4 LSB pad bits, 1000 0000 0000
|
||||
// .... decimal value 2048]
|
||||
// nrofPorts: p1 (0)
|
||||
// firstOFDMSymbolInTimeDomain: 4
|
||||
// cdm-Type: noCDM (0)
|
||||
// density: one (1)
|
||||
// one: NULL
|
||||
// freqBand
|
||||
// startingRB: 0
|
||||
// nrofRBs: 52
|
||||
// powerControlOffset: 0dB
|
||||
// powerControlOffsetSS: db0 (1)
|
||||
// scramblingID: 0
|
||||
// periodicityAndOffset: slots80 (9)
|
||||
// slots80: 1
|
||||
// qcl-InfoPeriodicCSI-RS: 0
|
||||
// Item 1
|
||||
// NZP-CSI-RS-Resource
|
||||
// nzp-CSI-RS-ResourceId: 1
|
||||
// resourceMapping
|
||||
// frequencyDomainAllocation: row1 (0)
|
||||
// row1: 10 [bit length 4, 4 LSB pad bits, 0001 .... decimal
|
||||
// value 1]
|
||||
// nrofPorts: p1 (0)
|
||||
// firstOFDMSymbolInTimeDomain: 4
|
||||
// cdm-Type: noCDM (0)
|
||||
// density: three (2)
|
||||
// three: NULL
|
||||
// freqBand
|
||||
// startingRB: 0
|
||||
// nrofRBs: 52
|
||||
// powerControlOffset: 0dB
|
||||
// powerControlOffsetSS: db0 (1)
|
||||
// scramblingID: 0
|
||||
// periodicityAndOffset: slots40 (7)
|
||||
// slots40: 11
|
||||
// qcl-InfoPeriodicCSI-RS: 0
|
||||
// Item 2
|
||||
// NZP-CSI-RS-Resource
|
||||
// nzp-CSI-RS-ResourceId: 2
|
||||
// resourceMapping
|
||||
// frequencyDomainAllocation: row1 (0)
|
||||
// row1: 10 [bit length 4, 4 LSB pad bits, 0001 .... decimal
|
||||
// value 1]
|
||||
// nrofPorts: p1 (0)
|
||||
// firstOFDMSymbolInTimeDomain: 8
|
||||
// cdm-Type: noCDM (0)
|
||||
// density: three (2)
|
||||
// three: NULL
|
||||
// freqBand
|
||||
// startingRB: 0
|
||||
// nrofRBs: 52
|
||||
// powerControlOffset: 0dB
|
||||
// powerControlOffsetSS: db0 (1)
|
||||
// scramblingID: 0
|
||||
// periodicityAndOffset: slots40 (7)
|
||||
// slots40: 11
|
||||
// qcl-InfoPeriodicCSI-RS: 0
|
||||
// Item 3
|
||||
// NZP-CSI-RS-Resource
|
||||
// nzp-CSI-RS-ResourceId: 3
|
||||
// resourceMapping
|
||||
// frequencyDomainAllocation: row1 (0)
|
||||
// row1: 10 [bit length 4, 4 LSB pad bits, 0001 .... decimal
|
||||
// value 1]
|
||||
// nrofPorts: p1 (0)
|
||||
// firstOFDMSymbolInTimeDomain: 4
|
||||
// cdm-Type: noCDM (0)
|
||||
// density: three (2)
|
||||
// three: NULL
|
||||
// freqBand
|
||||
// startingRB: 0
|
||||
// nrofRBs: 52
|
||||
// powerControlOffset: 0dB
|
||||
// powerControlOffsetSS: db0 (1)
|
||||
// scramblingID: 0
|
||||
// periodicityAndOffset: slots40 (7)
|
||||
// slots40: 12
|
||||
// qcl-InfoPeriodicCSI-RS: 0
|
||||
// Item 4
|
||||
// NZP-CSI-RS-Resource
|
||||
// nzp-CSI-RS-ResourceId: 4
|
||||
// resourceMapping
|
||||
// frequencyDomainAllocation: row1 (0)
|
||||
// row1: 10 [bit length 4, 4 LSB pad bits, 0001 .... decimal
|
||||
// value 1]
|
||||
// nrofPorts: p1 (0)
|
||||
// firstOFDMSymbolInTimeDomain: 8
|
||||
// cdm-Type: noCDM (0)
|
||||
// density: three (2)
|
||||
// three: NULL
|
||||
// freqBand
|
||||
// startingRB: 0
|
||||
// nrofRBs: 52
|
||||
// powerControlOffset: 0dB
|
||||
// powerControlOffsetSS: db0 (1)
|
||||
// scramblingID: 0
|
||||
// periodicityAndOffset: slots40 (7)
|
||||
// slots40: 12
|
||||
// qcl-InfoPeriodicCSI-RS: 0
|
||||
// nzp-CSI-RS-ResourceSetToAddModList: 2 items
|
||||
// Item 0
|
||||
// NZP-CSI-RS-ResourceSet
|
||||
// nzp-CSI-ResourceSetId: 0
|
||||
// nzp-CSI-RS-Resources: 1 item
|
||||
// Item 0
|
||||
// NZP-CSI-RS-ResourceId: 0
|
||||
// Item 1
|
||||
// NZP-CSI-RS-ResourceSet
|
||||
// nzp-CSI-ResourceSetId: 1
|
||||
// nzp-CSI-RS-Resources: 4 items
|
||||
// Item 0
|
||||
// NZP-CSI-RS-ResourceId: 1
|
||||
// Item 1
|
||||
// NZP-CSI-RS-ResourceId: 2
|
||||
// Item 2
|
||||
// NZP-CSI-RS-ResourceId: 3
|
||||
// Item 3
|
||||
// NZP-CSI-RS-ResourceId: 4
|
||||
// trs-Info: true (0)
|
||||
// csi-IM-ResourceToAddModList: 1 item
|
||||
// Item 0
|
||||
// CSI-IM-Resource
|
||||
// csi-IM-ResourceId: 0
|
||||
// csi-IM-ResourceElementPattern: pattern1 (1)
|
||||
// pattern1
|
||||
// subcarrierLocation-p1: s8 (2)
|
||||
// symbolLocation-p1: 8
|
||||
// freqBand
|
||||
// startingRB: 0
|
||||
// nrofRBs: 52
|
||||
// periodicityAndOffset: slots80 (9)
|
||||
// slots80: 1
|
||||
// csi-IM-ResourceSetToAddModList: 1 item
|
||||
// Item 0
|
||||
// CSI-IM-ResourceSet
|
||||
// csi-IM-ResourceSetId: 0
|
||||
// csi-IM-Resources: 1 item
|
||||
// Item 0
|
||||
// CSI-IM-ResourceId: 0
|
||||
// csi-ResourceConfigToAddModList: 3 items
|
||||
// Item 0
|
||||
// CSI-ResourceConfig
|
||||
// csi-ResourceConfigId: 0
|
||||
// csi-RS-ResourceSetList: nzp-CSI-RS-SSB (0)
|
||||
// nzp-CSI-RS-SSB
|
||||
// nzp-CSI-RS-ResourceSetList: 1 item
|
||||
// Item 0
|
||||
// NZP-CSI-RS-ResourceSetId: 0
|
||||
// bwp-Id: 0
|
||||
// resourceType: periodic (2)
|
||||
// Item 1
|
||||
// CSI-ResourceConfig
|
||||
// csi-ResourceConfigId: 1
|
||||
// csi-RS-ResourceSetList: csi-IM-ResourceSetList (1)
|
||||
// csi-IM-ResourceSetList: 1 item
|
||||
// Item 0
|
||||
// CSI-IM-ResourceSetId: 0
|
||||
// bwp-Id: 0
|
||||
// resourceType: periodic (2)
|
||||
// Item 2
|
||||
// CSI-ResourceConfig
|
||||
// csi-ResourceConfigId: 2
|
||||
// csi-RS-ResourceSetList: nzp-CSI-RS-SSB (0)
|
||||
// nzp-CSI-RS-SSB
|
||||
// nzp-CSI-RS-ResourceSetList: 1 item
|
||||
// Item 0
|
||||
// NZP-CSI-RS-ResourceSetId: 1
|
||||
// bwp-Id: 0
|
||||
// resourceType: periodic (2)
|
||||
// csi-ReportConfigToAddModList: 1 item
|
||||
// Item 0
|
||||
// CSI-ReportConfig
|
||||
// reportConfigId: 0
|
||||
// resourcesForChannelMeasurement: 0
|
||||
// csi-IM-ResourcesForInterference: 1
|
||||
// reportConfigType: periodic (0)
|
||||
// periodic
|
||||
// reportSlotConfig: slots80 (7)
|
||||
// slots80: 9
|
||||
// pucch-CSI-ResourceList: 1 item
|
||||
// Item 0
|
||||
// PUCCH-CSI-Resource
|
||||
// uplinkBandwidthPartId: 0
|
||||
// pucch-Resource: 17
|
||||
// reportQuantity: cri-RI-PMI-CQI (1)
|
||||
// cri-RI-PMI-CQI: NULL
|
||||
// reportFreqConfiguration
|
||||
// cqi-FormatIndicator: widebandCQI (0)
|
||||
// timeRestrictionForChannelMeasurements: notConfigured (1)
|
||||
// timeRestrictionForInterferenceMeasurements: notConfigured (1)
|
||||
// groupBasedBeamReporting: disabled (1)
|
||||
// disabled
|
||||
// cqi-Table: table2 (1)
|
||||
// subbandSize: value1 (0)
|
||||
// tag-Id: 0
|
||||
}
|
||||
|
||||
class ue_dummy_stack : public srsue::stack_interface_phy_nr
|
||||
{
|
||||
public:
|
||||
void in_sync() override {}
|
||||
void out_of_sync() override {}
|
||||
void run_tti(const uint32_t tti) override {}
|
||||
int sf_indication(const uint32_t tti) override { return 0; }
|
||||
sched_rnti_t get_dl_sched_rnti_nr(const uint32_t tti) override { return sched_rnti_t(); }
|
||||
sched_rnti_t get_ul_sched_rnti_nr(const uint32_t tti) override { return sched_rnti_t(); }
|
||||
void new_grant_dl(const uint32_t cc_idx, const mac_nr_grant_dl_t& grant, tb_action_dl_t* action) override {}
|
||||
void tb_decoded(const uint32_t cc_idx, const mac_nr_grant_dl_t& grant, tb_action_dl_result_t result) override {}
|
||||
void new_grant_ul(const uint32_t cc_idx, const mac_nr_grant_ul_t& grant, tb_action_ul_t* action) override {}
|
||||
void prach_sent(uint32_t tti, uint32_t s_id, uint32_t t_id, uint32_t f_id, uint32_t ul_carrier_id) override {}
|
||||
bool sr_opportunity(uint32_t tti, uint32_t sr_id, bool meas_gap, bool ul_sch_tx) override { return false; }
|
||||
};
|
||||
|
||||
class gnb_dummy_stack : public srsenb::stack_interface_phy_nr
|
||||
{
|
||||
public:
|
||||
int sf_indication(const uint32_t tti) override { return 0; }
|
||||
int rx_data_indication(rx_data_ind_t& grant) override { return 0; }
|
||||
int get_dl_sched(uint32_t tti, dl_sched_list_t& dl_sched_res) override
|
||||
{
|
||||
dl_sched_res[0].nof_grants = 0;
|
||||
return SRSRAN_SUCCESS;
|
||||
}
|
||||
int get_ul_sched(uint32_t tti, ul_sched_list_t& ul_sched_res) override { return 0; }
|
||||
};
|
||||
|
||||
int main(int argc, char** argv)
|
||||
{
|
||||
test_bench::args_t args(argc, argv);
|
||||
|
||||
// Parse arguments
|
||||
TESTASSERT(args.valid);
|
||||
|
||||
ue_dummy_stack ue_stack;
|
||||
gnb_dummy_stack gnb_stack;
|
||||
|
||||
// Create test bench
|
||||
test_bench tb(args, gnb_stack, ue_stack);
|
||||
|
||||
// Assert bench is initialised correctly
|
||||
TESTASSERT(tb.is_initialised());
|
||||
|
||||
for (uint32_t i = 0; i < 1000; i++) {
|
||||
TESTASSERT(tb.run_tti());
|
||||
}
|
||||
|
||||
// If reached here, the test is successful
|
||||
return SRSRAN_SUCCESS;
|
||||
}
|
||||
@ -1,113 +0,0 @@
|
||||
/**
|
||||
*
|
||||
* \section COPYRIGHT
|
||||
*
|
||||
* Copyright 2013-2021 Software Radio Systems Limited
|
||||
*
|
||||
* By using this file, you agree to the terms and conditions set
|
||||
* forth in the LICENSE file which can be found at the top level of
|
||||
* the distribution.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "srsenb/hdr/phy/nr/worker_pool.h"
|
||||
#include "srsran/common/test_common.h"
|
||||
#include "srsue/hdr/phy/nr/worker_pool.h"
|
||||
|
||||
class phy_common : public srsran::phy_common_interface
|
||||
{
|
||||
public:
|
||||
void
|
||||
worker_end(void* h, bool tx_enable, srsran::rf_buffer_t& buffer, srsran::rf_timestamp_t& tx_time, bool is_nr) override
|
||||
{}
|
||||
};
|
||||
|
||||
class ue_dummy_stack : public srsue::stack_interface_phy_nr
|
||||
{
|
||||
public:
|
||||
void in_sync() override {}
|
||||
void out_of_sync() override {}
|
||||
void run_tti(const uint32_t tti) override {}
|
||||
int sf_indication(const uint32_t tti) override { return 0; }
|
||||
sched_rnti_t get_dl_sched_rnti_nr(const uint32_t tti) override { return sched_rnti_t(); }
|
||||
sched_rnti_t get_ul_sched_rnti_nr(const uint32_t tti) override { return sched_rnti_t(); }
|
||||
void new_grant_dl(const uint32_t cc_idx, const mac_nr_grant_dl_t& grant, tb_action_dl_t* action) override {}
|
||||
void tb_decoded(const uint32_t cc_idx, const mac_nr_grant_dl_t& grant, tb_action_dl_result_t result) override {}
|
||||
void new_grant_ul(const uint32_t cc_idx, const mac_nr_grant_ul_t& grant, tb_action_ul_t* action) override {}
|
||||
void prach_sent(uint32_t tti, uint32_t s_id, uint32_t t_id, uint32_t f_id, uint32_t ul_carrier_id) override {}
|
||||
bool sr_opportunity(uint32_t tti, uint32_t sr_id, bool meas_gap, bool ul_sch_tx) override { return false; }
|
||||
};
|
||||
|
||||
class test_bench
|
||||
{
|
||||
private:
|
||||
srsenb::nr::worker_pool gnb_phy;
|
||||
phy_common gnb_phy_com;
|
||||
srsue::nr::worker_pool ue_phy;
|
||||
phy_common ue_phy_com;
|
||||
ue_dummy_stack ue_stack;
|
||||
bool initialised = false;
|
||||
|
||||
public:
|
||||
struct args_t {
|
||||
uint32_t nof_threads = 6;
|
||||
uint32_t nof_prb = 52;
|
||||
|
||||
bool parse(int argc, char** argv);
|
||||
};
|
||||
|
||||
test_bench(const args_t& args) : ue_phy(args.nof_threads), gnb_phy(args.nof_threads)
|
||||
{
|
||||
// Prepare cell list
|
||||
srsenb::phy_cell_cfg_list_nr_t cell_list(1);
|
||||
cell_list[0].carrier.nof_prb = args.nof_prb;
|
||||
|
||||
// Prepare gNb PHY arguments
|
||||
srsenb::phy_args_t gnb_phy_args = {};
|
||||
|
||||
// Initialise gnb
|
||||
if (not gnb_phy.init(cell_list, gnb_phy_args, gnb_phy_com, srslog::get_default_sink(), 31)) {
|
||||
return;
|
||||
}
|
||||
|
||||
// Prepare PHY
|
||||
srsue::phy_args_nr_t ue_phy_args = {};
|
||||
|
||||
// Initialise UE PHY
|
||||
if (not ue_phy.init(ue_phy_args, ue_phy_com, &ue_stack, 31)) {
|
||||
return;
|
||||
}
|
||||
|
||||
initialised = true;
|
||||
}
|
||||
|
||||
~test_bench()
|
||||
{
|
||||
gnb_phy.stop();
|
||||
ue_phy.stop();
|
||||
}
|
||||
|
||||
bool is_initialised() const { return initialised; }
|
||||
};
|
||||
|
||||
bool test_bench::args_t::parse(int argc, char** argv)
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
int main(int argc, char** argv)
|
||||
{
|
||||
test_bench::args_t args = {};
|
||||
|
||||
// Parse arguments
|
||||
TESTASSERT(args.parse(argc, argv));
|
||||
|
||||
// Create test bench
|
||||
test_bench tb(args);
|
||||
|
||||
// Assert bench is initialised correctly
|
||||
TESTASSERT(tb.is_initialised());
|
||||
|
||||
// If reached here, the test is successful
|
||||
return SRSRAN_SUCCESS;
|
||||
}
|
||||
@ -0,0 +1,131 @@
|
||||
/**
|
||||
*
|
||||
* \section COPYRIGHT
|
||||
*
|
||||
* Copyright 2013-2021 Software Radio Systems Limited
|
||||
*
|
||||
* By using this file, you agree to the terms and conditions set
|
||||
* forth in the LICENSE file which can be found at the top level of
|
||||
* the distribution.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SRSRAN_TEST_BENCH_H
|
||||
#define SRSRAN_TEST_BENCH_H
|
||||
|
||||
#include "dummy_phy_common.h"
|
||||
#include "srsenb/hdr/phy/nr/worker_pool.h"
|
||||
#include "srsue/hdr/phy/nr/worker_pool.h"
|
||||
|
||||
class test_bench
|
||||
{
|
||||
private:
|
||||
uint32_t tti = 0;
|
||||
srsenb::nr::worker_pool gnb_phy;
|
||||
phy_common gnb_phy_com;
|
||||
srsue::nr::worker_pool ue_phy;
|
||||
phy_common ue_phy_com;
|
||||
bool initialised = false;
|
||||
uint32_t sf_sz = 0;
|
||||
|
||||
public:
|
||||
struct args_t {
|
||||
double srate_hz = 11.52e6;
|
||||
uint32_t nof_threads = 6;
|
||||
uint32_t nof_channels = 1;
|
||||
uint32_t buffer_sz_ms = 10;
|
||||
bool valid = false;
|
||||
srsran::phy_cfg_nr_t phy_cfg = {};
|
||||
srsenb::phy_cell_cfg_list_nr_t cell_list = {};
|
||||
srsenb::nr::worker_pool::args_t gnb_args;
|
||||
uint16_t rnti = 0x1234;
|
||||
|
||||
args_t(int argc, char** argv);
|
||||
};
|
||||
|
||||
test_bench(const args_t& args, srsenb::stack_interface_phy_nr& gnb_stack, srsue::stack_interface_phy_nr& ue_stack) :
|
||||
ue_phy(args.nof_threads),
|
||||
gnb_phy(args.cell_list, args.gnb_args, gnb_phy_com, gnb_stack, srslog::get_default_sink()),
|
||||
ue_phy_com(phy_common::args_t(args.srate_hz, args.buffer_sz_ms, args.nof_channels),
|
||||
srslog::fetch_basic_logger("UE /PHY/COM")),
|
||||
gnb_phy_com(phy_common::args_t(args.srate_hz, args.buffer_sz_ms, args.nof_channels),
|
||||
srslog::fetch_basic_logger("GNB/PHY/COM"))
|
||||
{
|
||||
// Calculate subframe length
|
||||
sf_sz = (uint32_t)std::round(args.srate_hz * 1e-3);
|
||||
|
||||
// Prepare PHY
|
||||
srsue::phy_args_nr_t ue_phy_args = {};
|
||||
|
||||
// Initialise UE PHY
|
||||
if (not ue_phy.init(ue_phy_args, ue_phy_com, &ue_stack, 31)) {
|
||||
return;
|
||||
}
|
||||
|
||||
// Set UE configuration
|
||||
if (not ue_phy.set_config(args.phy_cfg)) {
|
||||
return;
|
||||
}
|
||||
|
||||
initialised = true;
|
||||
}
|
||||
|
||||
~test_bench()
|
||||
{
|
||||
ue_phy_com.stop();
|
||||
gnb_phy_com.stop();
|
||||
gnb_phy.stop();
|
||||
ue_phy.stop();
|
||||
}
|
||||
|
||||
bool is_initialised() const { return initialised; }
|
||||
|
||||
bool run_tti()
|
||||
{
|
||||
// Get gNb worker
|
||||
srsenb::nr::sf_worker* gnb_worker = gnb_phy.wait_worker(tti);
|
||||
if (gnb_worker == nullptr) {
|
||||
return false;
|
||||
}
|
||||
|
||||
// Feed gNb the UE transmitted signal
|
||||
srsran::rf_timestamp_t gnb_time = {};
|
||||
std::vector<cf_t*> gnb_rx_buffers(1);
|
||||
gnb_rx_buffers[0] = gnb_worker->get_buffer_rx(0, 0);
|
||||
ue_phy_com.read(gnb_rx_buffers, sf_sz, gnb_time);
|
||||
|
||||
// Set gNb time
|
||||
gnb_time.add(TX_ENB_DELAY * 1e-3);
|
||||
gnb_worker->set_time(tti, gnb_time);
|
||||
|
||||
// Start gNb work
|
||||
gnb_phy_com.push_semaphore(gnb_worker);
|
||||
gnb_phy.start_worker(gnb_worker);
|
||||
|
||||
// Get UE worker
|
||||
srsue::nr::sf_worker* ue_worker = ue_phy.wait_worker(tti);
|
||||
if (ue_worker == nullptr) {
|
||||
return false;
|
||||
}
|
||||
|
||||
// Feed UE the gNb transmitted signal
|
||||
srsran::rf_timestamp_t ue_time = {};
|
||||
std::vector<cf_t*> ue_rx_buffers(1);
|
||||
ue_rx_buffers[0] = ue_worker->get_buffer(0, 0);
|
||||
gnb_phy_com.read(ue_rx_buffers, sf_sz, ue_time);
|
||||
|
||||
// Set UE time
|
||||
ue_time.add(TX_ENB_DELAY * 1e-3);
|
||||
ue_worker->set_tti(tti);
|
||||
ue_worker->set_tx_time(ue_time);
|
||||
|
||||
// Start gNb work
|
||||
ue_phy_com.push_semaphore(ue_worker);
|
||||
ue_phy.start_worker(ue_worker);
|
||||
|
||||
tti++;
|
||||
return true;
|
||||
}
|
||||
};
|
||||
|
||||
#endif // SRSRAN_TEST_BENCH_H
|
||||
Loading…
Reference in New Issue