5g-team
/
srsRAN_4G
mirror of https://github.com/pvnis/srsRAN_4G.git
2
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add packing of dci format 1A for pdcch orders.

Browse Source
master
Fabian Eckermann 3 years ago committed by Andre Puschmann
parent adec23cbc5
commit d0c07fc86e
4 changed files with 142 additions and 114 deletions
Show Stats Download Patch File Download Diff File

10
lib/include/srsran/phy/phch/dci.h
Unescape Escape View File

@ -70,7 +70,6 @@ typedef struct SRSRAN_API {
} srsran_dci_tb_t;
typedef struct SRSRAN_API {
uint16_t rnti;
srsran_dci_format_t format;
srsran_dci_location_t location;
@ -94,10 +93,10 @@ typedef struct SRSRAN_API {
bool power_offset;
uint8_t tpc_pucch;
// RA order
bool is_ra_order;
uint32_t ra_preamble;
uint32_t ra_mask_idx;
// PDCCH order
bool is_pdcch_order;
uint32_t preamble_idx;
uint32_t prach_mask_idx;
// Release 10
uint32_t cif;
@ -121,7 +120,6 @@ typedef struct SRSRAN_API {
/** Unpacked DCI Format0 message */
typedef struct SRSRAN_API {
uint16_t rnti;
srsran_dci_format_t format;
srsran_dci_location_t location;

44
lib/src/phy/phch/dci.c
Unescape Escape View File

@ -696,7 +696,7 @@ static int dci_format1_unpack(srsran_cell_t* cell,
/* Packs DCI format 1A for compact scheduling of PDSCH words according to 36.212 5.3.3.1.3
*
* TODO: RA procedure initiated by PDCCH, TPC commands
* TODO: TPC commands
*/
static int dci_format1As_pack(srsran_cell_t* cell,
srsran_dl_sf_cfg_t* sf,
@ -714,6 +714,21 @@ static int dci_format1As_pack(srsran_cell_t* cell,
*y++ = 1; // format differentiation
// random access procedure initiated by a PDCCH order
if (dci->is_pdcch_order) {
*y++ = 0; // localized or distributed VRB assignment is always 0 for PDCCH order
// RIV values all set to 1 for PDCCH order
int nof_bits = riv_nbits(cell->nof_prb);
int i = 0;
while (i < nof_bits) {
*y++ = 1;
i++;
}
srsran_bit_unpack(dci->preamble_idx, &y, 6); // preamble index
srsran_bit_unpack(dci->prach_mask_idx, &y, 4); // PRACH mask index
} else {
if (dci->alloc_type != SRSRAN_RA_ALLOC_TYPE2) {
ERROR("Format 1A accepts type2 resource allocation only");
return SRSRAN_ERROR;
@ -756,7 +771,7 @@ static int dci_format1As_pack(srsran_cell_t* cell,
y++; // MSB of TPC is reserved
*y++ = dci->type2_alloc.n_prb1a; // LSB indicates N_prb_1a for TBS
}
}
// Padding with zeros
uint32_t n = srsran_dci_format_sizeof(cell, sf, cfg, SRSRAN_DCI_FORMAT1A);
while (y - msg->payload < n) {
@ -810,16 +825,16 @@ static int dci_format1As_unpack(srsran_cell_t* cell,
// This is a Random access order
y += 1 + nof_bits;
dci->is_ra_order = true;
dci->ra_preamble = srsran_bit_pack(&y, 6);
dci->ra_mask_idx = srsran_bit_pack(&y, 4);
dci->is_pdcch_order = true;
dci->preamble_idx = srsran_bit_pack(&y, 6);
dci->prach_mask_idx = srsran_bit_pack(&y, 4);
return SRSRAN_SUCCESS;
}
}
}
dci->is_ra_order = false;
dci->is_pdcch_order = false;
dci->alloc_type = SRSRAN_RA_ALLOC_TYPE2;
dci->type2_alloc.mode = *y++;
@ -1544,6 +1559,14 @@ static char* freq_hop_fl_string(int freq_hop)
void srsran_dci_dl_fprint(FILE* f, srsran_dci_dl_t* dci, uint32_t nof_prb)
{
if (dci->is_pdcch_order) {
fprintf(f, "PDCCH order:\n");
if (dci->cif_present) {
fprintf(f, " - Carrier idx:\t\t\t\t%d\n", dci->cif);
}
fprintf(f, " - Preamble index:\t\t%d\n", dci->preamble_idx);
fprintf(f, " - PRACH mask index:\t\t%d\n", dci->prach_mask_idx);
} else {
fprintf(f, " - Resource Allocation Type:\t\t%s\n", ra_type_string(dci->alloc_type));
switch (dci->alloc_type) {
case SRSRAN_RA_ALLOC_TYPE0:
@ -1557,7 +1580,8 @@ void srsran_dci_dl_fprint(FILE* f, srsran_dci_dl_t* dci, uint32_t nof_prb)
fprintf(f, " + RBG Shift:\t\t\t\t%s\n", dci->type1_alloc.shift ? "Yes" : "No");
break;
case SRSRAN_RA_ALLOC_TYPE2:
fprintf(f, " + Type:\t\t\t\t%s\n", dci->type2_alloc.mode == SRSRAN_RA_TYPE2_LOC ? "Localized" : "Distributed");
fprintf(
f, " + Type:\t\t\t\t%s\n", dci->type2_alloc.mode == SRSRAN_RA_TYPE2_LOC ? "Localized" : "Distributed");
fprintf(f, " + Resource Indicator Value:\t\t%d\n", dci->type2_alloc.riv);
break;
}
@ -1576,6 +1600,7 @@ void srsran_dci_dl_fprint(FILE* f, srsran_dci_dl_t* dci, uint32_t nof_prb)
fprintf(f, " + Redundancy version:\t\t\t%d\n", dci->tb[i].rv);
}
}
}
}
static uint32_t print_multi(char* info_str, uint32_t n, uint32_t len, const srsran_dci_dl_t* dci_dl, uint32_t value_id)
@ -1618,6 +1643,10 @@ uint32_t srsran_dci_dl_info(const srsran_dci_dl_t* dci_dl, char* info_str, uint3
n = srsran_print_check(info_str, len, n, ", cif=%d", dci_dl->cif);
}
if (dci_dl->is_pdcch_order) {
n = srsran_print_check(info_str, len, n, ", preamb_idx=%d", dci_dl->preamble_idx);
n = srsran_print_check(info_str, len, n, ", prach_mask_idx=%d", dci_dl->prach_mask_idx);
} else {
switch (dci_dl->alloc_type) {
case SRSRAN_RA_ALLOC_TYPE0:
n = srsran_print_check(info_str, len, n, ", rbg=0x%x", dci_dl->type0_alloc.rbg_bitmask);
@ -1659,6 +1688,7 @@ uint32_t srsran_dci_dl_info(const srsran_dci_dl_t* dci_dl, char* info_str, uint3
dci_dl->format == SRSRAN_DCI_FORMAT2B) {
n = srsran_print_check(info_str, len, n, ", tb_sw=%d, pinfo=%d", dci_dl->tb_cw_swap, dci_dl->pinfo);
}
}
#if SRSRAN_DCI_HEXDEBUG
n = srsran_print_check(info_str, len, n, ", len=%d, hex=%s", dci_dl->nof_bits, dci_dl->hex_str);

6
lib/test/phy/phy_dl_test.c
Unescape Escape View File

@ -457,13 +457,13 @@ int main(int argc, char** argv)
dci.rnti = rnti;
dci.is_tdd = false;
dci.is_dwpts = false;
dci.is_ra_order = false;
dci.is_pdcch_order = false;
dci.tb_cw_swap = false;
dci.pconf = false;
dci.power_offset = false;
dci.tpc_pucch = false;
dci.ra_preamble = false;
dci.ra_mask_idx = false;
dci.preamble_idx = 0;
dci.prach_mask_idx = 0;
dci.srs_request = false;
dci.srs_request_present = false;

6
srsue/src/phy/test/scell_search_test.cc
Unescape Escape View File

@ -627,13 +627,13 @@ int main(int argc, char** argv)
dci.rnti = serving_cell_pdsch_rnti;
dci.is_tdd = false;
dci.is_dwpts = false;
dci.is_ra_order = false;
dci.is_pdcch_order = false;
dci.tb_cw_swap = false;
dci.pconf = false;
dci.power_offset = false;
dci.tpc_pucch = 0;
dci.ra_preamble = 0;
dci.ra_mask_idx = 0;
dci.preamble_idx = 0;
dci.prach_mask_idx = 0;
dci.srs_request = false;
dci.srs_request_present = false;
dci.cif_present = false;

Write Preview
Loading…
Cancel
Save