gnb,rrc,sched: backporting tiny fixes to make COTS UE PRACH

* use carrier PCI instead of cell_id
* fix coreset0 config
* use hard-coded SSB subcarrier offset

srsgnb/src/stack/mac/sched_nr_grant_allocator.cc

@@ -90,8 +90,9 @@ alloc_result bwp_slot_allocator::alloc_si(uint32_t            aggr_idx,
 
   // RAR allocation successful.
   bwp_pdcch_slot.dl_prbs |= prbs;
-  // Generate DCI for RAR with given RA-RNTI
+  // Generate DCI for SIB
   pdcch_dl_t& pdcch = bwp_pdcch_slot.dl.phy.pdcch_dl.back();
+  pdcch.dci_cfg.coreset0_bw = srsran_coreset_get_bw(&cfg.cfg.pdcch.coreset[0]);
   if (not fill_dci_sib(prbs, si_idx, si_ntx, *bwp_grid.cfg, pdcch.dci)) {
     // Cancel on-going PDCCH allocation
     bwp_pdcch_slot.coresets[coreset_id]->rem_last_dci();

srsgnb/src/stack/rrc/cell_asn1_config.cc

@@ -928,7 +928,7 @@ int fill_mib_from_enb_cfg(const rrc_cell_cfg_nr_t& cell_cfg, asn1::rrc_nr::mib_s
     default:
       srsran_terminate("Invalid carrier SCS=%d Hz", SRSRAN_SUBC_SPACING_NR(cell_cfg.phy_cell.carrier.scs));
   }
-  mib.ssb_subcarrier_offset            = 0;
+  mib.ssb_subcarrier_offset            = 6; // FIXME: currently hard-coded
   mib.dmrs_type_a_position.value       = mib_s::dmrs_type_a_position_opts::pos2;
   mib.pdcch_cfg_sib1.search_space_zero = 0;
   mib.pdcch_cfg_sib1.ctrl_res_set_zero = cell_cfg.coreset0_idx;

srsgnb/src/stack/rrc/rrc_nr_config_utils.cc

@@ -111,7 +111,7 @@ int derive_coreset0_params(rrc_cell_cfg_nr_t& cell)
   // Calculate integer SSB to pointA frequency offset in Hz
   uint32_t ssb_pointA_freq_offset_Hz =
       (ssb_abs_freq_Hz > pointA_abs_freq_Hz) ? (uint32_t)(ssb_abs_freq_Hz - pointA_abs_freq_Hz) : 0;
-  int ret = srsran_coreset_zero(cell.phy_cell.cell_id,
+  int ret = srsran_coreset_zero(cell.phy_cell.carrier.pci,
                                 ssb_pointA_freq_offset_Hz,
                                 cell.ssb_cfg.scs,
                                 cell.phy_cell.carrier.scs,