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@ -27,11 +27,11 @@ target_link_libraries(rlc_am_control_test srslte_upper srslte_phy)
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add_test(rlc_am_control_test rlc_am_control_test)
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add_test(rlc_am_control_test rlc_am_control_test)
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add_executable(rlc_am_test rlc_am_test.cc)
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add_executable(rlc_am_test rlc_am_test.cc)
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target_link_libraries(rlc_am_test srslte_upper srslte_phy srslte_common rrc_asn1)
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target_link_libraries(rlc_am_test srslte_upper srslte_phy srslte_common)
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add_test(rlc_am_test rlc_am_test)
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add_test(rlc_am_test rlc_am_test)
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add_executable(rlc_stress_test rlc_stress_test.cc)
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add_executable(rlc_stress_test rlc_stress_test.cc)
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target_link_libraries(rlc_stress_test srslte_upper srslte_phy srslte_common rrc_asn1 ${Boost_LIBRARIES})
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target_link_libraries(rlc_stress_test srslte_upper srslte_phy srslte_common ${Boost_LIBRARIES})
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add_test(rlc_am_stress_test rlc_stress_test --mode=AM --loglevel 1 --sdu_gen_delay 250)
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add_test(rlc_am_stress_test rlc_stress_test --mode=AM --loglevel 1 --sdu_gen_delay 250)
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add_test(rlc_um_stress_test rlc_stress_test --mode=UM --loglevel 1)
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add_test(rlc_um_stress_test rlc_stress_test --mode=UM --loglevel 1)
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add_test(rlc_tm_stress_test rlc_stress_test --mode=TM --loglevel 1 --random_opp=false)
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add_test(rlc_tm_stress_test rlc_stress_test --mode=TM --loglevel 1 --random_opp=false)
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@ -44,7 +44,7 @@ target_link_libraries(rlc_um_data_test srslte_upper srslte_phy srslte_common)
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add_test(rlc_um_data_test rlc_um_data_test)
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add_test(rlc_um_data_test rlc_um_data_test)
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add_executable(rlc_um_test rlc_um_test.cc)
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add_executable(rlc_um_test rlc_um_test.cc)
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target_link_libraries(rlc_um_test srslte_upper srslte_phy rrc_asn1)
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target_link_libraries(rlc_um_test srslte_upper srslte_phy)
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add_test(rlc_um_test rlc_um_test)
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add_test(rlc_um_test rlc_um_test)
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########################################################################
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########################################################################
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