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sched,nr: redesign the order available search spaces/coresets are found in the scheduler

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master
Francisco Paisana 4 years ago
parent dd3c9b4d7e
commit b81cbd1334
12 changed files with 154 additions and 85 deletions
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41
srsenb/hdr/stack/mac/nr/sched_nr_cfg.h
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@ -83,30 +83,57 @@ void get_dci_locs(const srsran_coreset_t& coreset,
using ue_cfg_t = sched_nr_interface::ue_cfg_t;
using ue_cc_cfg_t = sched_nr_interface::ue_cc_cfg_t;
class bwp_ue_cfg
{
public:
bwp_ue_cfg() = default;
explicit bwp_ue_cfg(uint16_t rnti, const bwp_params& bwp_cfg, const ue_cfg_t& uecfg_);
const ue_cfg_t* ue_cfg() const { return cfg_; }
const srsran::phy_cfg_nr_t& cfg() const { return cfg_->phy_cfg; }
const bwp_cce_pos_list& cce_pos_list(uint32_t search_id) const
{
return cce_positions_list[ss_id_to_cce_idx[search_id]];
}
private:
uint16_t rnti = SRSRAN_INVALID_RNTI;
const bwp_params* bwp_cfg = nullptr;
const ue_cfg_t* cfg_ = nullptr;
std::vector<bwp_cce_pos_list> cce_positions_list;
std::array<uint32_t, SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE> ss_id_to_cce_idx;
};
class ue_cfg_extended : public ue_cfg_t
{
public:
struct search_space_params {
srsran_search_space_t* cfg = nullptr;
const srsran_search_space_t* cfg;
bwp_cce_pos_list cce_positions;
};
struct coreset_params {
srsran_coreset_t* cfg = nullptr;
std::vector<search_space_params*> ss_list;
bwp_cce_pos_list cce_positions;
std::vector<uint32_t> ss_list;
};
struct bwp_params {
std::vector<search_space_params> search_spaces;
std::array<srsran::optional<search_space_params>, SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE> ss_list;
std::vector<coreset_params> coresets;
};
struct cc_params {
srsran::bounded_vector<bwp_params, SCHED_NR_MAX_BWP_PER_CELL> bwps;
};
uint16_t rnti;
std::vector<cc_params> cc_params;
ue_cfg_extended() = default;
explicit ue_cfg_extended(uint16_t rnti, const ue_cfg_t& uecfg);
const bwp_cce_pos_list& get_dci_pos_list(uint32_t cc, uint32_t bwp_id, uint32_t search_space_id) const
{
return cc_params[cc].bwps[bwp_id].ss_list[search_space_id]->cce_positions;
}
uint16_t rnti;
std::vector<cc_params> cc_params;
};
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

3
srsenb/hdr/stack/mac/nr/sched_nr_interface.h
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@ -51,11 +51,10 @@ public:
struct bwp_cfg_t {
uint32_t start_rb = 0;
uint32_t rb_width = 100;
srsran_pdcch_cfg_nr_t pdcch = {};
srsran_sch_hl_cfg_nr_t pdsch = {};
srsran_sch_hl_cfg_nr_t pusch = {};
uint32_t rar_window_size = 3;
std::array<srsran::optional<srsran_coreset_t>, SRSRAN_UE_DL_NR_MAX_NOF_CORESET> coresets;
};
struct cell_cfg_t {

3
srsenb/hdr/stack/mac/nr/sched_nr_pdcch.h
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@ -52,7 +52,7 @@ public:
* @param user UE object or null in case of broadcast/RAR/paging allocation
* @return if the allocation was successful
*/
bool alloc_dci(pdcch_grant_type_t alloc_type, uint32_t aggr_idx, slot_ue* user = nullptr);
bool alloc_dci(pdcch_grant_type_t alloc_type, uint32_t aggr_idx, uint32_t search_space_id, slot_ue* user = nullptr);
void rem_last_dci();
@ -71,6 +71,7 @@ private:
// List of PDCCH grants
struct alloc_record {
uint32_t aggr_idx;
uint32_t search_space_id;
uint32_t idx;
pdcch_grant_type_t alloc_type;
slot_ue* ue;

2
srsenb/hdr/stack/mac/nr/sched_nr_rb_grid.h
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@ -28,7 +28,7 @@ struct pending_rar_t;
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
const static size_t MAX_CORESET_PER_BWP = 3;
using slot_coreset_list = srsran::bounded_vector<coreset_region, MAX_CORESET_PER_BWP>;
using slot_coreset_list = std::array<srsran::optional<coreset_region>, MAX_CORESET_PER_BWP>;
struct bwp_slot_grid {
uint32_t slot_idx;

8
srsenb/hdr/stack/mac/nr/sched_nr_ue.h
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@ -41,7 +41,7 @@ public:
uint32_t cc = SCHED_NR_MAX_CARRIERS;
// UE parameters common to all sectors
const ue_cfg_extended* cfg = nullptr;
const bwp_ue_cfg* cfg = nullptr;
bool pending_sr;
// UE parameters that are sector specific
@ -64,7 +64,7 @@ class ue_carrier
{
public:
ue_carrier(uint16_t rnti, const ue_cfg_t& cfg, const sched_cell_params& cell_params_);
slot_ue try_reserve(tti_point pdcch_tti, const ue_cfg_extended& cfg);
slot_ue try_reserve(tti_point pdcch_tti, const ue_cfg_t& cfg);
void push_feedback(srsran::move_callback<void(ue_carrier&)> callback);
const uint16_t rnti;
@ -77,7 +77,7 @@ public:
harq_entity harq_ent;
private:
const ue_cfg_t* cfg = nullptr;
bwp_ue_cfg bwp_cfg;
const sched_cell_params& cell_params;
resource_guard busy;
@ -106,7 +106,7 @@ private:
bool pending_sr = false;
int current_idx = 0;
std::array<ue_cfg_extended, 4> ue_cfgs;
std::array<ue_cfg_t, 4> ue_cfgs;
};
using ue_map_t = srsran::static_circular_map<uint16_t, std::unique_ptr<ue>, SCHED_NR_MAX_USERS>;

42
srsenb/src/stack/mac/nr/sched_nr_cfg.cc
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@ -21,7 +21,8 @@ bwp_params::bwp_params(const cell_cfg_t& cell, const sched_cfg_t& sched_cfg_, ui
{
P = get_P(cfg.rb_width, cfg.pdsch.rbg_size_cfg_1);
N_rbg = get_nof_rbgs(cfg.rb_width, cfg.start_rb, cfg.pdsch.rbg_size_cfg_1);
srsran_assert(cfg.coresets[0].has_value(), "At least one coreset has to be active per BWP");
srsran_assert(bwp_id != 0 or cfg.pdcch.coreset_present[0], "CORESET#0 has to be active for initial BWP");
}
sched_cell_params::sched_cell_params(uint32_t cc_, const cell_cfg_t& cell, const sched_cfg_t& sched_cfg_) :
@ -56,6 +57,26 @@ void get_dci_locs(const srsran_coreset_t& coreset,
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
bwp_ue_cfg::bwp_ue_cfg(uint16_t rnti_, const bwp_params& bwp_cfg_, const ue_cfg_t& uecfg_) :
rnti(rnti_), cfg_(&uecfg_), bwp_cfg(&bwp_cfg_)
{
std::fill(ss_id_to_cce_idx.begin(), ss_id_to_cce_idx.end(), SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE);
const auto& pdcch = cfg().pdcch;
for (uint32_t i = 0; i < SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE; ++i) {
if (pdcch.search_space_present[i]) {
const auto& ss = pdcch.search_space[i];
srsran_assert(pdcch.coreset_present[ss.coreset_id],
"Invalid mapping search space id=%d to coreset id=%d",
ss.id,
ss.coreset_id);
const auto& coreset = pdcch.coreset[ss.coreset_id];
cce_positions_list.emplace_back();
get_dci_locs(coreset, ss, rnti, cce_positions_list.back());
ss_id_to_cce_idx[ss.id] = cce_positions_list.size() - 1;
}
}
}
ue_cfg_extended::ue_cfg_extended(uint16_t rnti_, const ue_cfg_t& uecfg) : ue_cfg_t(uecfg), rnti(rnti_)
{
cc_params.resize(carriers.size());
@ -64,19 +85,20 @@ ue_cfg_extended::ue_cfg_extended(uint16_t rnti_, const ue_cfg_t& uecfg) : ue_cfg
auto& bwp = cc_params[cc].bwps[0];
for (uint32_t ssid = 0; ssid < SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE; ++ssid) {
if (phy_cfg.pdcch.search_space_present[ssid]) {
bwp.search_spaces.emplace_back();
bwp.search_spaces.back().cfg = &phy_cfg.pdcch.search_space[ssid];
auto& ss = phy_cfg.pdcch.search_space[ssid];
bwp.ss_list[ss.id].emplace();
bwp.ss_list[ss.id]->cfg = &ss;
get_dci_locs(phy_cfg.pdcch.coreset[ss.coreset_id], ss, rnti, bwp.ss_list[ss.id]->cce_positions);
}
}
for (uint32_t csid = 0; csid < SRSRAN_UE_DL_NR_MAX_NOF_CORESET; ++csid) {
if (phy_cfg.pdcch.coreset_present[csid]) {
for (uint32_t idx = 0; idx < SRSRAN_UE_DL_NR_MAX_NOF_CORESET; ++idx) {
if (phy_cfg.pdcch.coreset_present[idx]) {
bwp.coresets.emplace_back();
auto& coreset = bwp.coresets.back();
coreset.cfg = &phy_cfg.pdcch.coreset[csid];
for (auto& ss : bwp.search_spaces) {
if (ss.cfg->coreset_id == csid + 1) {
coreset.ss_list.push_back(&ss);
get_dci_locs(*coreset.cfg, *coreset.ss_list.back()->cfg, rnti, coreset.cce_positions);
coreset.cfg = &phy_cfg.pdcch.coreset[idx];
for (auto& ss : bwp.ss_list) {
if (ss.has_value() and ss->cfg->coreset_id == coreset.cfg->id) {
coreset.ss_list.push_back(ss->cfg->id);
}
}
}

15
srsenb/src/stack/mac/nr/sched_nr_pdcch.cc
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@ -22,7 +22,7 @@ coreset_region::coreset_region(const bwp_params& bwp_cfg_,
pdcch_dl_list_t& dl_list_,
pdcch_ul_list_t& ul_list_) :
bwp_cfg(&bwp_cfg_),
coreset_cfg(&bwp_cfg_.cfg.coresets[coreset_id_].value()),
coreset_cfg(&bwp_cfg_.cfg.pdcch.coreset[coreset_id_]),
coreset_id(coreset_id_),
slot_idx(slot_idx_),
pdcch_dl_list(dl_list_),
@ -43,7 +43,10 @@ void coreset_region::reset()
pdcch_ul_list.clear();
}
bool coreset_region::alloc_dci(pdcch_grant_type_t alloc_type, uint32_t aggr_idx, slot_ue* user)
bool coreset_region::alloc_dci(pdcch_grant_type_t alloc_type,
uint32_t aggr_idx,
uint32_t search_space_id,
slot_ue* user)
{
srsran_assert(aggr_idx <= 4, "Invalid DCI aggregation level=%d", 1U << aggr_idx);
srsran_assert((user == nullptr) xor
@ -54,6 +57,7 @@ bool coreset_region::alloc_dci(pdcch_grant_type_t alloc_type, uint32_t aggr_idx,
alloc_record record;
record.ue = user;
record.aggr_idx = aggr_idx;
record.search_space_id = search_space_id;
record.alloc_type = alloc_type;
if (record.alloc_type == pdcch_grant_type_t::ul_data) {
record.idx = pdcch_ul_list.size();
@ -172,10 +176,9 @@ srsran::span<const uint32_t> coreset_region::get_cce_loc_table(const alloc_recor
{
switch (record.alloc_type) {
case pdcch_grant_type_t::dl_data:
return record.ue->cfg->cc_params[record.ue->cc]
.bwps[bwp_cfg->bwp_id]
.coresets[coreset_id]
.cce_positions[slot_idx][record.aggr_idx];
return record.ue->cfg->cce_pos_list(record.search_space_id)[slot_idx][record.aggr_idx];
case pdcch_grant_type_t::ul_data:
return record.ue->cfg->cce_pos_list(record.search_space_id)[slot_idx][record.aggr_idx];
default:
break;
}

4
srsenb/src/stack/mac/nr/sched_nr_phy.cc
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@ -171,9 +171,9 @@ void fill_pusch_ue(const slot_ue& ue, const rbgmask_t& rbgmask, const bwp_params
pucch_resource_grant find_pucch_resource(const slot_ue& ue, const rbgmask_t& rbgs, uint32_t tbs)
{
if (ue.cfg->phy_cfg.pucch.enabled) {
if (ue.cfg->cfg().pucch.enabled) {
for (uint32_t i = 0; i < SRSRAN_PUCCH_NR_MAX_NOF_SETS; ++i) {
const auto& rset = ue.cfg->phy_cfg.pucch.sets[i];
const auto& rset = ue.cfg->cfg().pucch.sets[i];
if (rset.max_payload_size >= tbs) {
for (uint32_t sid = 0; sid < rset.nof_resources; ++sid) {
return pucch_resource_grant{ue.rnti, i, sid};

36
srsenb/src/stack/mac/nr/sched_nr_rb_grid.cc
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@ -26,14 +26,20 @@ bwp_slot_grid::bwp_slot_grid(const bwp_params& bwp_cfg_, uint32_t slot_idx_) :
is_dl(srsran_tdd_nr_is_dl(&bwp_cfg_.cell_cfg.tdd, NUMEROLOGY_IDX, slot_idx_)),
is_ul(srsran_tdd_nr_is_ul(&bwp_cfg_.cell_cfg.tdd, NUMEROLOGY_IDX, slot_idx_))
{
const uint32_t coreset_id = 0; // Note: for now only one coreset per BWP supported
coresets.emplace_back(*cfg, coreset_id, slot_idx_, dl_pdcchs, ul_pdcchs);
for (uint32_t cs_idx = 0; cs_idx < SRSRAN_UE_DL_NR_MAX_NOF_CORESET; ++cs_idx) {
if (cfg->cfg.pdcch.coreset_present[cs_idx]) {
uint32_t cs_id = cfg->cfg.pdcch.coreset[cs_idx].id;
coresets[cs_id].emplace(*cfg, cs_id, slot_idx_, dl_pdcchs, ul_pdcchs);
}
}
}
void bwp_slot_grid::reset()
{
for (auto& coreset : coresets) {
coreset.reset();
if (coreset.has_value()) {
coreset->reset();
}
}
dl_rbgs.reset();
ul_rbgs.reset();
@ -89,8 +95,9 @@ alloc_result bwp_slot_allocator::alloc_rar(uint32_t
}
// Find PDCCH position
const uint32_t coreset_id = 0;
if (not bwp_pdcch_slot.coresets[coreset_id].alloc_dci(pdcch_grant_type_t::rar, aggr_idx, nullptr)) {
const uint32_t coreset_id = cfg.cfg.pdcch.ra_search_space.coreset_id;
const uint32_t search_space_id = cfg.cfg.pdcch.ra_search_space.id;
if (not bwp_pdcch_slot.coresets[coreset_id]->alloc_dci(pdcch_grant_type_t::rar, aggr_idx, search_space_id, nullptr)) {
// Could not find space in PDCCH
logger.debug("SCHED: No space in PDCCH for DL tx.");
return alloc_result::no_cch_space;
@ -100,7 +107,7 @@ alloc_result bwp_slot_allocator::alloc_rar(uint32_t
pdcch_dl_t& pdcch = bwp_pdcch_slot.dl_pdcchs.back();
if (not fill_dci_rar(interv, *bwp_grid.cfg, pdcch.dci)) {
// Cancel on-going PDCCH allocation
bwp_pdcch_slot.coresets[coreset_id].rem_last_dci();
bwp_pdcch_slot.coresets[coreset_id]->rem_last_dci();
return alloc_result::invalid_coderate;
}
@ -132,8 +139,9 @@ alloc_result bwp_slot_allocator::alloc_pdsch(slot_ue& ue, const rbgmask_t& dl_ma
if ((pdsch_mask & dl_mask).any()) {
return alloc_result::sch_collision;
}
const uint32_t aggr_idx = 2, coreset_id = 0;
if (not bwp_pdcch_slot.coresets[coreset_id].alloc_dci(pdcch_grant_type_t::dl_data, aggr_idx, &ue)) {
const uint32_t aggr_idx = 2, search_space_id = 1;
uint32_t coreset_id = ue.cfg->cfg().pdcch.search_space[search_space_id].coreset_id;
if (not bwp_pdcch_slot.coresets[coreset_id]->alloc_dci(pdcch_grant_type_t::dl_data, aggr_idx, search_space_id, &ue)) {
// Could not find space in PDCCH
return alloc_result::no_cch_space;
}
@ -152,7 +160,7 @@ alloc_result bwp_slot_allocator::alloc_pdsch(slot_ue& ue, const rbgmask_t& dl_ma
pucch_resource_grant pucch_res = find_pucch_resource(ue, bwp_uci_slot.ul_rbgs, tbs);
if (pucch_res.rnti != SRSRAN_INVALID_RNTI) {
// Could not find space in PUCCH for HARQ-ACK
bwp_pdcch_slot.coresets[coreset_id].rem_last_dci();
bwp_pdcch_slot.coresets[coreset_id]->rem_last_dci();
return alloc_result::no_cch_space;
}
@ -164,7 +172,7 @@ alloc_result bwp_slot_allocator::alloc_pdsch(slot_ue& ue, const rbgmask_t& dl_ma
pucch_grant& pucch = bwp_uci_slot.pucchs.back();
pucch.resource = pucch_res;
bwp_uci_slot.ul_rbgs.set(
ue.cfg->phy_cfg.pucch.sets[pucch_res.resource_set_id].resources[pucch_res.resource_id].starting_prb);
ue.cfg->cfg().pucch.sets[pucch_res.resource_set_id].resources[pucch_res.resource_id].starting_prb);
return alloc_result::success;
}
@ -190,8 +198,10 @@ alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, const rbgmask_t& ul_ma
if ((pusch_mask & ul_mask).any()) {
return alloc_result::sch_collision;
}
const uint32_t aggr_idx = 2, coreset_id = 0;
if (not bwp_pdcch_slot.coresets[coreset_id].alloc_dci(pdcch_grant_type_t::ul_data, aggr_idx, &ue)) {
const uint32_t aggr_idx = 2, search_space_id = 1;
uint32_t coreset_id = ue.cfg->cfg().pdcch.search_space[search_space_id].coreset_id;
if (not bwp_pdcch_slot.coresets[coreset_id].value().alloc_dci(
pdcch_grant_type_t::ul_data, aggr_idx, search_space_id, &ue)) {
// Could not find space in PDCCH
return alloc_result::no_cch_space;
}
@ -200,7 +210,7 @@ alloc_result bwp_slot_allocator::alloc_pusch(slot_ue& ue, const rbgmask_t& ul_ma
if (ue.h_ul->empty()) {
mcs = 20;
tbs = 100;
bool ret = ue.h_ul->new_tx(ue.pusch_tti, ue.pusch_tti, ul_mask, mcs, tbs, ue.cfg->maxharq_tx);
bool ret = ue.h_ul->new_tx(ue.pusch_tti, ue.pusch_tti, ul_mask, mcs, tbs, ue.cfg->ue_cfg()->maxharq_tx);
srsran_assert(ret, "Failed to allocate UL HARQ");
} else {
srsran_assert(ue.h_ul->new_retx(ue.pusch_tti, ue.pusch_tti, ul_mask, &mcs, &tbs),

12
srsenb/src/stack/mac/nr/sched_nr_ue.cc
Unescape Escape View File

@ -23,7 +23,7 @@ slot_ue::slot_ue(resource_guard::token ue_token_, uint16_t rnti_, tti_point tti_
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
ue_carrier::ue_carrier(uint16_t rnti_, const ue_cfg_t& uecfg_, const sched_cell_params& cell_params_) :
rnti(rnti_), cc(cell_params_.cc), cfg(&uecfg_), cell_params(cell_params_)
rnti(rnti_), cc(cell_params_.cc), bwp_cfg(rnti_, cell_params_.bwps[0], uecfg_), cell_params(cell_params_)
{}
void ue_carrier::push_feedback(srsran::move_callback<void(ue_carrier&)> callback)
@ -31,14 +31,16 @@ void ue_carrier::push_feedback(srsran::move_callback<void(ue_carrier&)> callback
pending_feedback.push_back(std::move(callback));
}
slot_ue ue_carrier::try_reserve(tti_point tti_rx, const ue_cfg_extended& uecfg_)
slot_ue ue_carrier::try_reserve(tti_point tti_rx, const ue_cfg_t& uecfg_)
{
slot_ue sfu(busy, rnti, tti_rx, cc);
if (sfu.empty()) {
return sfu;
}
// successfully acquired. Process any CC-specific pending feedback
cfg = &uecfg_;
if (bwp_cfg.ue_cfg() != &uecfg_) {
bwp_cfg = bwp_ue_cfg(rnti, cell_params.bwps[0], uecfg_);
}
while (not pending_feedback.empty()) {
pending_feedback.front()(*this);
pending_feedback.pop_front();
@ -53,7 +55,7 @@ slot_ue ue_carrier::try_reserve(tti_point tti_rx, const ue_cfg_extended& uecfg_)
}
// set UE parameters common to all carriers
sfu.cfg = &uecfg_;
sfu.cfg = &bwp_cfg;
// copy cc-specific parameters and find available HARQs
sfu.cc_cfg = &uecfg_.carriers[cc];
@ -92,7 +94,7 @@ slot_ue ue_carrier::try_reserve(tti_point tti_rx, const ue_cfg_extended& uecfg_)
ue::ue(uint16_t rnti_, const ue_cfg_t& cfg, const sched_params& sched_cfg_) : rnti(rnti_), sched_cfg(sched_cfg_)
{
ue_cfgs[0] = ue_cfg_extended(rnti, cfg);
ue_cfgs[0] = cfg;
for (uint32_t cc = 0; cc < cfg.carriers.size(); ++cc) {
if (cfg.carriers[cc].active) {
carriers[cc].reset(new ue_carrier(rnti, cfg, sched_cfg.cells[cc]));

7
srsenb/src/stack/mac/nr/sched_nr_worker.cc
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@ -49,14 +49,9 @@ void slot_cc_worker::run()
// Allocate pending RARs
cell.bwps[0].ra.run_slot(bwp_alloc);
// Prioritize PDCCH scheduling for DL and UL data in a Round-Robin fashion
if ((tti_rx.to_uint() & 0x1u) == 0) {
// TODO: Prioritize PDCCH scheduling for DL and UL data in a Round-Robin fashion
alloc_dl_ues();
alloc_ul_ues();
} else {
alloc_ul_ues();
alloc_dl_ues();
}
}
void slot_cc_worker::end_tti()

48
srsenb/test/mac/nr/sched_nr_test.cc
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@ -12,6 +12,7 @@
#include "sched_nr_sim_ue.h"
#include "srsenb/hdr/stack/mac/nr/sched_nr.h"
#include "srsran/common/phy_cfg_nr_default.h"
#include "srsran/common/test_common.h"
#include "srsran/common/thread_pool.h"
@ -19,7 +20,10 @@ namespace srsenb {
using dl_sched_t = sched_nr_interface::dl_sched_t;
srsran_coreset_t get_default_coreset()
static const srsran::phy_cfg_nr_t default_phy_cfg =
srsran::phy_cfg_nr_default_t{srsran::phy_cfg_nr_default_t::reference_cfg_t{}};
srsran_coreset_t get_default_coreset0()
{
srsran_coreset_t coreset{};
coreset.id = 0;
@ -45,7 +49,29 @@ sched_nr_interface::cell_cfg_t get_default_cell_cfg()
cell_cfg.tdd.pattern2.period_ms = 0;
cell_cfg.bwps.resize(1);
cell_cfg.bwps[0].coresets[0].emplace(get_default_coreset());
cell_cfg.bwps[0].pdcch.coreset_present[0] = true;
cell_cfg.bwps[0].pdcch.coreset[0] = get_default_coreset0();
cell_cfg.bwps[0].pdcch.coreset_present[1] = true;
cell_cfg.bwps[0].pdcch.coreset[1] = default_phy_cfg.pdcch.coreset[1];
cell_cfg.bwps[0].pdcch.search_space_present[0] = true;
auto& ss = cell_cfg.bwps[0].pdcch.search_space[0];
ss.id = 0;
ss.coreset_id = 0;
ss.duration = 1;
ss.type = srsran_search_space_type_common_0;
ss.nof_candidates[0] = 1;
ss.nof_candidates[1] = 1;
ss.nof_candidates[2] = 1;
ss.nof_candidates[3] = 0;
ss.nof_candidates[4] = 0;
ss.nof_formats = 1;
ss.formats[0] = srsran_dci_format_nr_1_0;
cell_cfg.bwps[0].pdcch.search_space_present[1] = true;
cell_cfg.bwps[0].pdcch.search_space[1] = default_phy_cfg.pdcch.search_space[1];
cell_cfg.bwps[0].pdcch.ra_search_space_present = true;
cell_cfg.bwps[0].pdcch.ra_search_space = cell_cfg.bwps[0].pdcch.search_space[1];
return cell_cfg;
}
std::vector<sched_nr_interface::cell_cfg_t> get_default_cells_cfg(uint32_t nof_sectors)
@ -65,23 +91,7 @@ sched_nr_interface::ue_cfg_t get_default_ue_cfg(uint32_t nof_cc)
for (uint32_t cc = 0; cc < nof_cc; ++cc) {
uecfg.carriers[cc].active = true;
}
uecfg.phy_cfg.pdcch.coreset_present[0] = true;
uecfg.phy_cfg.pdcch.coreset[0] = get_default_coreset();
uecfg.phy_cfg.pdcch.coreset[0].id = 1;
uecfg.phy_cfg.pdcch.search_space_present[0] = true;
auto& ss = uecfg.phy_cfg.pdcch.search_space[0];
ss.id = 1;
ss.coreset_id = 1;
ss.duration = 1;
ss.type = srsran_search_space_type_common_0;
ss.nof_candidates[0] = 1;
ss.nof_candidates[1] = 1;
ss.nof_candidates[2] = 1;
ss.nof_candidates[3] = 0;
ss.nof_candidates[4] = 0;
ss.nof_formats = 1;
ss.formats[0] = srsran_dci_format_nr_1_0;
uecfg.phy_cfg = default_phy_cfg;
return uecfg;
}

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