SRSENB: Schedule RI reporting

srsenb/hdr/stack/rrc/rrc.h

@@ -54,10 +54,11 @@ typedef enum {
 static const char rrc_cfg_cqi_mode_text[RRC_CFG_CQI_MODE_N_ITEMS][20] = {"periodic", "aperiodic"};
 
 typedef struct {
-  uint32_t           sf_mapping[80]; 
+  uint32_t           sf_mapping[80];
-  uint32_t           nof_subframes; 
+  uint32_t           nof_subframes;
-  uint32_t           nof_prb; 
+  uint32_t           nof_prb;
-  uint32_t           period; 
+  uint32_t           period;
+  uint32_t           m_ri;
   bool               simultaneousAckCQI;
   rrc_cfg_cqi_mode_t mode; 
 } rrc_cfg_cqi_t; 
@@ -245,6 +246,8 @@ public:
     void cqi_get(uint16_t* pmi_idx, uint16_t* n_pucch);
     int  cqi_free();
 
+    int ri_get(uint32_t m_ri, uint16_t* ri_idx);
+
     bool select_security_algorithms();
     void send_dl_ccch(asn1::rrc::dl_ccch_msg_s* dl_ccch_msg);
     void send_dl_dcch(asn1::rrc::dl_dcch_msg_s*    dl_dcch_msg,

srsenb/rr.conf.example

@@ -46,5 +46,6 @@ phy_cnfg =
     period = 40; // in ms
     subframe = [0];
     nof_prb = 2; 
+    m_ri = 8; // RI period in CQI period
   };
 };

srsenb/src/enb_cfg_parser.cc

@@ -935,6 +935,7 @@ int enb::parse_rr(all_args_t* args, rrc_cfg_t* rrc_cfg)
   cqi_report_cnfg.add_field(new parser::field_enum_str<rrc_cfg_cqi_mode_t>(
       "mode", &rrc_cfg->cqi_cfg.mode, rrc_cfg_cqi_mode_text, RRC_CFG_CQI_MODE_N_ITEMS));
   cqi_report_cnfg.add_field(new parser::field<uint32>("period", &rrc_cfg->cqi_cfg.period));
+  cqi_report_cnfg.add_field(new parser::field<uint32>("m_ri", &rrc_cfg->cqi_cfg.m_ri));
   cqi_report_cnfg.add_field(new parser::field<uint32>("nof_prb", &rrc_cfg->cqi_cfg.nof_prb));
   cqi_report_cnfg.add_field(new parser::field<bool>("simultaneousAckCQI", &rrc_cfg->cqi_cfg.simultaneousAckCQI));
   cqi_report_cnfg.add_field(new field_sf_mapping(rrc_cfg->cqi_cfg.sf_mapping, &rrc_cfg->cqi_cfg.nof_subframes));

srsenb/src/stack/rrc/rrc.cc

@@ -1780,10 +1780,14 @@ void rrc::ue::send_connection_reconf(srslte::unique_byte_buffer_t pdu)
     if (phy_cfg->ant_info_present and
         ((phy_cfg->ant_info.explicit_value().tx_mode == ant_info_ded_s::tx_mode_e_::tm3) ||
          (phy_cfg->ant_info.explicit_value().tx_mode == ant_info_ded_s::tx_mode_e_::tm4))) {
-      phy_cfg->cqi_report_cfg.cqi_report_periodic.set_setup();
+      uint16_t ri_idx = 0;
-      phy_cfg->cqi_report_cfg.cqi_report_periodic.setup().ri_cfg_idx_present = true;
+      if (ri_get(parent->cfg.cqi_cfg.m_ri, &ri_idx) == SRSLTE_SUCCESS) {
-      phy_cfg->cqi_report_cfg.cqi_report_periodic.setup().ri_cfg_idx         = 483;
+        phy_cfg->cqi_report_cfg.cqi_report_periodic.set_setup();
-      parent->rrc_log->console("\nWarning: Only 1 user is supported in TM3 and TM4\n\n");
+        phy_cfg->cqi_report_cfg.cqi_report_periodic.setup().ri_cfg_idx_present = true;
+        phy_cfg->cqi_report_cfg.cqi_report_periodic.setup().ri_cfg_idx         = ri_idx;
+      } else {
+        parent->rrc_log->console("\nWarning: Configured wrong M_ri parameter.\n\n");
+      }
     } else {
       phy_cfg->cqi_report_cfg.cqi_report_periodic.setup().ri_cfg_idx_present = false;
     }
@@ -2300,4 +2304,43 @@ int rrc::ue::cqi_allocate(uint32_t period, uint16_t* pmi_idx, uint16_t* n_pucch)
   return 0; 
 }
 
+int rrc::ue::ri_get(uint32_t m_ri, uint16_t* ri_idx)
+{
+  int32_t ret = SRSLTE_SUCCESS;
+
+  uint32_t I_ri        = 0;
+  int32_t  N_offset_ri = 0; // Naivest approach: overlap RI with PMI
+  switch (m_ri) {
+    case 0:
+      // Disabled
+      break;
+    case 1:
+      I_ri = -N_offset_ri;
+      break;
+    case 2:
+      I_ri = 161 - N_offset_ri;
+      break;
+    case 4:
+      I_ri = 322 - N_offset_ri;
+      break;
+    case 8:
+      I_ri = 483 - N_offset_ri;
+      break;
+    case 16:
+      I_ri = 644 - N_offset_ri;
+      break;
+    case 32:
+      I_ri = 805 - N_offset_ri;
+      break;
+    default:
+      parent->rrc_log->error("Allocating RI: invalid m_ri=%d\n", m_ri);
+  }
+
+  // If ri_dix is available, copy
+  if (ri_idx) {
+    *ri_idx = I_ri;
+  }
+
+  return ret;
+}
 }