5g-team
/
srsRAN_4G
mirror of https://github.com/pvnis/srsRAN_4G.git
2
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sched,nr: fix failing sched test due to misconfiguration

Browse Source
master
Francisco 3 years ago committed by Francisco Paisana
parent 7ef206e15b
commit b25814de27
8 changed files with 49 additions and 46 deletions
Show Stats Download Patch File Download Diff File

57
lib/src/asn1/rrc_nr_utils.cc
Unescape Escape View File

@ -334,41 +334,38 @@ bool make_phy_tdd_cfg(const tdd_ul_dl_cfg_common_s& tdd_ul_dl_cfg_common,
srsran_duplex_config_nr.tdd.pattern1.nof_dl_symbols = tdd_ul_dl_cfg_common.pattern1.nrof_dl_symbols;
srsran_duplex_config_nr.tdd.pattern1.nof_ul_slots = tdd_ul_dl_cfg_common.pattern1.nrof_ul_slots;
srsran_duplex_config_nr.tdd.pattern1.nof_ul_symbols = tdd_ul_dl_cfg_common.pattern1.nrof_ul_symbols;
// Copy and return struct
*in_srsran_duplex_config_nr = srsran_duplex_config_nr;
if (not tdd_ul_dl_cfg_common.pattern2_present) {
return true;
}
if (tdd_ul_dl_cfg_common.pattern2_present) {
switch (tdd_ul_dl_cfg_common.pattern2.dl_ul_tx_periodicity) {
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms1:
srsran_duplex_config_nr.tdd.pattern2.period_ms = 1;
break;
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms2:
srsran_duplex_config_nr.tdd.pattern2.period_ms = 2;
break;
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms5:
srsran_duplex_config_nr.tdd.pattern2.period_ms = 5;
break;
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms10:
srsran_duplex_config_nr.tdd.pattern2.period_ms = 10;
break;
switch (tdd_ul_dl_cfg_common.pattern2.dl_ul_tx_periodicity) {
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms1:
srsran_duplex_config_nr.tdd.pattern2.period_ms = 1;
break;
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms2:
srsran_duplex_config_nr.tdd.pattern2.period_ms = 2;
break;
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms5:
srsran_duplex_config_nr.tdd.pattern2.period_ms = 5;
break;
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms10:
srsran_duplex_config_nr.tdd.pattern2.period_ms = 10;
break;
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms1p25:
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms0p5:
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms0p625:
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms2p5:
default:
asn1::log_warning("Invalid option for pattern2 dl_ul_tx_periodicity_opts %s",
tdd_ul_dl_cfg_common.pattern2.dl_ul_tx_periodicity.to_string());
return false;
}
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms1p25:
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms0p5:
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms0p625:
case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms2p5:
default:
asn1::log_warning("Invalid option for pattern2 dl_ul_tx_periodicity_opts %s",
tdd_ul_dl_cfg_common.pattern2.dl_ul_tx_periodicity.to_string());
return false;
srsran_duplex_config_nr.tdd.pattern2.nof_dl_slots = tdd_ul_dl_cfg_common.pattern2.nrof_dl_slots;
srsran_duplex_config_nr.tdd.pattern2.nof_dl_symbols = tdd_ul_dl_cfg_common.pattern2.nrof_dl_symbols;
srsran_duplex_config_nr.tdd.pattern2.nof_ul_slots = tdd_ul_dl_cfg_common.pattern2.nrof_ul_slots;
srsran_duplex_config_nr.tdd.pattern2.nof_ul_symbols = tdd_ul_dl_cfg_common.pattern2.nrof_ul_symbols;
}
srsran_duplex_config_nr.tdd.pattern2.nof_dl_slots = tdd_ul_dl_cfg_common.pattern2.nrof_dl_slots;
srsran_duplex_config_nr.tdd.pattern2.nof_dl_symbols = tdd_ul_dl_cfg_common.pattern2.nrof_dl_symbols;
srsran_duplex_config_nr.tdd.pattern2.nof_ul_slots = tdd_ul_dl_cfg_common.pattern2.nrof_ul_slots;
srsran_duplex_config_nr.tdd.pattern2.nof_ul_symbols = tdd_ul_dl_cfg_common.pattern2.nrof_ul_symbols;
// Copy and return struct
*in_srsran_duplex_config_nr = srsran_duplex_config_nr;

3
srsgnb/src/stack/mac/sched_nr_cfg.cc
Unescape Escape View File

@ -143,7 +143,8 @@ cell_params_t::cell_params_t(uint32_t cc_, const sched_nr_cell_cfg_t& cell, cons
// Conversion 36.331 ASN1 TDD-UL-DL-ConfigCommon to srsran_duplex_config_nr_t
duplex.mode = SRSRAN_DUPLEX_MODE_FDD;
if (cell.tdd_ul_dl_cfg_common.is_present()) {
srsran_assert(srsran::make_phy_tdd_cfg(*cell.tdd_ul_dl_cfg_common, &duplex), "Failed to generate Cell TDD config");
bool success = srsran::make_phy_tdd_cfg(*cell.tdd_ul_dl_cfg_common, &duplex);
srsran_assert(success, "Failed to generate Cell TDD config");
}
bwps.reserve(cell.bwps.size());

7
srsgnb/src/stack/mac/sched_nr_grant_allocator.cc
Unescape Escape View File

@ -337,9 +337,8 @@ alloc_result bwp_slot_allocator::alloc_pdsch(slot_ue& ue, uint32_t ss_id, const
srsran_assert(success, "Failed to allocate DL HARQ retx");
}
srsran_slot_cfg_t slot_cfg;
slot_cfg.idx = ue.pdsch_slot.to_uint();
slot_cfg.idx = ue.pdsch_slot.to_uint();
// Value 0.95 is from TS 38.214 v15.14.00, Section 5.1.3, page 17
const static float max_R = 0.95;
while (true) {
@ -371,8 +370,8 @@ alloc_result bwp_slot_allocator::alloc_pdsch(slot_ue& ue, uint32_t ss_id, const
// Generate PUCCH
bwp_uci_slot.pending_acks.emplace_back();
bwp_uci_slot.pending_acks.back().phy_cfg = &ue->phy();
srsran_assert(ue->phy().get_pdsch_ack_resource(pdcch.dci, bwp_uci_slot.pending_acks.back().res),
"Error getting ack resource");
bool success = ue->phy().get_pdsch_ack_resource(pdcch.dci, bwp_uci_slot.pending_acks.back().res);
srsran_assert(success, "Error getting ack resource");
return alloc_result::success;
}

4
srsgnb/src/stack/mac/sched_nr_interface_utils.cc
Unescape Escape View File

@ -49,8 +49,8 @@ srsran::phy_cfg_nr_t get_common_ue_phy_cfg(const sched_nr_cell_cfg_t& cfg)
// TDD UL-DL config
ue_phy_cfg.duplex.mode = SRSRAN_DUPLEX_MODE_FDD;
if (cfg.tdd_ul_dl_cfg_common.is_present()) {
srsran_sanity_check(srsran::make_phy_tdd_cfg(*cfg.tdd_ul_dl_cfg_common, &ue_phy_cfg.duplex),
"Failed to convert Cell TDDConfig to UEPHYConfig");
bool success = srsran::make_phy_tdd_cfg(*cfg.tdd_ul_dl_cfg_common, &ue_phy_cfg.duplex);
srsran_sanity_check(success, "Failed to convert Cell TDDConfig to UEPHYConfig");
}
return ue_phy_cfg;

2
srsgnb/src/stack/mac/test/sched_nr_sim_ue.cc
Unescape Escape View File

@ -208,7 +208,7 @@ void sched_nr_base_test_bench::stop()
}
}
srsran::const_span<sched_nr_base_test_bench::cc_result_t> sched_nr_base_test_bench::get_slot_results() const
std::vector<sched_nr_base_test_bench::cc_result_t> sched_nr_base_test_bench::get_slot_results() const
{
sem_wait(&slot_sem);
auto ret = cc_results;

2
srsgnb/src/stack/mac/test/sched_nr_sim_ue.h
Unescape Escape View File

@ -125,7 +125,7 @@ public:
slot_point get_slot_tx() const { return current_slot_tx; }
/// may block waiting for scheduler to finish generating slot result
srsran::const_span<cc_result_t> get_slot_results() const;
std::vector<cc_result_t> get_slot_results() const;
int rach_ind(uint16_t rnti, uint32_t cc, slot_point tti_rx, uint32_t preamble_idx);

18
srsgnb/src/stack/mac/test/sched_nr_test.cc
Unescape Escape View File

@ -165,10 +165,10 @@ void test_sched_nr_no_data(sim_args_t args)
void test_sched_nr_data(sim_args_t args)
{
uint32_t max_nof_ttis = 100000, nof_sectors = 1;
uint16_t rnti = 0x4601;
uint32_t nof_sectors = 1;
uint16_t rnti = 0x4601;
uint32_t nof_dl_bytes_to_tx =
std::uniform_int_distribution<int>{0, 9}(rand_gen)*pow(10, std::uniform_int_distribution<int>{1, 7}(rand_gen));
std::uniform_int_distribution<int>{1, 9}(rand_gen)*pow(10, std::uniform_int_distribution<int>{1, 7}(rand_gen));
sched_nr_interface::sched_args_t cfg;
cfg.auto_refill_buffer = false;
@ -185,8 +185,13 @@ void test_sched_nr_data(sim_args_t args)
events.push_back(add_rlc_dl_bytes(50, rnti, 0, nof_dl_bytes_to_tx));
/* Run Test */
auto finish_condition = [max_nof_ttis, rnti, nof_dl_bytes_to_tx, &tester](uint32_t nof_slots) {
return nof_slots >= max_nof_ttis or tester.ue_metrics[rnti].nof_dl_bytes > nof_dl_bytes_to_tx;
uint32_t stop_tti = std::numeric_limits<uint32_t>::max();
auto finish_condition = [&stop_tti, rnti, nof_dl_bytes_to_tx, &tester](uint32_t nof_slots) mutable {
if (stop_tti == std::numeric_limits<uint32_t>::max() and
tester.ue_metrics[rnti].nof_dl_bytes >= nof_dl_bytes_to_tx) {
stop_tti = nof_slots + 10;
}
return nof_slots >= std::min(stop_tti, 100000u);
};
for (uint32_t nof_slots = 0; not finish_condition(nof_slots); ++nof_slots) {
slot_point slot_rx(0, nof_slots % 10240);
@ -214,8 +219,9 @@ void test_sched_nr_data(sim_args_t args)
fmt::print("Enqueued RLC DL bytes: {}\n", nof_dl_bytes_to_tx);
tester.print_results();
TESTASSERT(tester.ue_metrics[rnti].nof_dl_txs > 1);
TESTASSERT(tester.ue_metrics[rnti].nof_dl_txs > 0);
TESTASSERT(tester.ue_metrics[rnti].nof_dl_bytes >= nof_dl_bytes_to_tx);
TESTASSERT(tester.ue_metrics[rnti].nof_dl_bytes < nof_dl_bytes_to_tx + 20000);
// Since UL buffers were not externally updated, we should only see Msg3 as UL tx
TESTASSERT_EQ(1, tester.ue_metrics[rnti].nof_ul_txs);
}

2
srsgnb/src/stack/mac/test/sched_nr_ue_ded_test_suite.cc
Unescape Escape View File

@ -42,7 +42,7 @@ void test_dl_sched_result(const sim_nr_enb_ctxt_t& enb_ctxt, const sched_nr_cc_r
// CHECK: UCI
if (pdcch.dci.ctx.format == srsran_dci_format_nr_1_0) {
TESTASSERT(pdcch.dci.harq_feedback == k1 - 1);
TESTASSERT_EQ(k1 - 1, pdcch.dci.harq_feedback);
} else {
TESTASSERT(pdcch.dci.harq_feedback == pdcch_slot.slot_idx());
}

Write Preview
Loading…
Cancel
Save