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@ -19,10 +19,11 @@ test_bench::args_t::args_t(int argc, char** argv)
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valid = true;
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cell_list.resize(1);
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cell_list[0].carrier.nof_prb = 52;
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cell_list[0].carrier.nof_prb = 52;
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cell_list[0].carrier.max_mimo_layers = 1;
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cell_list[0].carrier.pci = 500;
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phy_cfg.carrier = cell_list[0].carrier;
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phy_cfg.carrier.pci = 500;
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phy_cfg.carrier = cell_list[0].carrier;
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phy_cfg.carrier.absolute_frequency_point_a = 633928;
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phy_cfg.carrier.absolute_frequency_ssb = 634176;
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@ -213,340 +214,307 @@ test_bench::args_t::args_t(int argc, char** argv)
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phy_cfg.harq_ack.dl_data_to_ul_ack[6] = 11;
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phy_cfg.prach.freq_offset = 2;
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// pusch-Config: setup (1)
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// setup
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// dmrs-UplinkForPUSCH-MappingTypeA: setup (1)
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// setup
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// dmrs-AdditionalPosition: pos1 (1)
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// transformPrecodingDisabled
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// pusch-PowerControl
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// msg3-Alpha: alpha1 (7)
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// p0-NominalWithoutGrant: -90dBm
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// p0-AlphaSets: 1 item
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// Item 0
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// P0-PUSCH-AlphaSet
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// p0-PUSCH-AlphaSetId: 0
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// p0: 0dB
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// alpha: alpha1 (7)
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// pathlossReferenceRSToAddModList: 1 item
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// Item 0
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// PUSCH-PathlossReferenceRS
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// pusch-PathlossReferenceRS-Id: 0
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// referenceSignal: ssb-Index (0)
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// ssb-Index: 0
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// sri-PUSCH-MappingToAddModList: 1 item
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// Item 0
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// SRI-PUSCH-PowerControl
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// sri-PUSCH-PowerControlId: 0
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// sri-PUSCH-PathlossReferenceRS-Id: 0
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// sri-P0-PUSCH-AlphaSetId: 0
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// sri-PUSCH-ClosedLoopIndex: i0 (0)
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// resourceAllocation: resourceAllocationType1 (1)
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// uci-OnPUSCH: setup (1)
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// setup
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// betaOffsets: semiStatic (1)
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// semiStatic
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// betaOffsetACK-Index1: 9
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// betaOffsetACK-Index2: 9
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// betaOffsetACK-Index3: 9
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// betaOffsetCSI-Part1-Index1: 6
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// betaOffsetCSI-Part1-Index2: 6
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// betaOffsetCSI-Part2-Index1: 6
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// betaOffsetCSI-Part2-Index2: 6
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// scaling: f1 (3)
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// srs-Config: setup (1)
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// setup
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// srs-ResourceSetToAddModList: 1 item
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// Item 0
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// SRS-ResourceSet
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// srs-ResourceSetId: 0
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// srs-ResourceIdList: 1 item
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// Item 0
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// SRS-ResourceId: 0
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// resourceType: aperiodic (0)
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// aperiodic
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// aperiodicSRS-ResourceTrigger: 1
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// slotOffset: 7
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// usage: codebook (1)
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// p0: -90dBm
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// pathlossReferenceRS: ssb-Index (0)
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// ssb-Index: 0
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// srs-ResourceToAddModList: 1 item
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// Item 0
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// SRS-Resource
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// srs-ResourceId: 0
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// nrofSRS-Ports: port1 (0)
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// transmissionComb: n2 (0)
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// n2
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// combOffset-n2: 0
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// cyclicShift-n2: 0
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// resourceMapping
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// startPosition: 0
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// nrofSymbols: n1 (0)
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// repetitionFactor: n1 (0)
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// freqDomainPosition: 0
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// freqDomainShift: 6
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// freqHopping
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// c-SRS: 11
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// b-SRS: 3
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// b-hop: 0
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// groupOrSequenceHopping: neither (0)
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// resourceType: aperiodic (0)
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// aperiodic
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// sequenceId: 500
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// firstActiveUplinkBWP-Id: 0
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// pusch-ServingCellConfig: setup (1)
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// setup
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// pdcch-ServingCellConfig: setup (1)
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// setup
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// pdsch-ServingCellConfig: setup (1)
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// setup
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// nrofHARQ-ProcessesForPDSCH: n16 (5)
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// csi-MeasConfig: setup (1)
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// setup
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// nzp-CSI-RS-ResourceToAddModList: 5 items
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// Item 0
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// NZP-CSI-RS-Resource
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// nzp-CSI-RS-ResourceId: 0
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// resourceMapping
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// frequencyDomainAllocation: row2 (1)
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// row2: 8000 [bit length 12, 4 LSB pad bits, 1000 0000 0000
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// .... decimal value 2048]
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// nrofPorts: p1 (0)
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// firstOFDMSymbolInTimeDomain: 4
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// cdm-Type: noCDM (0)
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// density: one (1)
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// one: NULL
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// freqBand
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// startingRB: 0
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// nrofRBs: 52
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// powerControlOffset: 0dB
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// powerControlOffsetSS: db0 (1)
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// scramblingID: 0
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// periodicityAndOffset: slots80 (9)
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// slots80: 1
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// qcl-InfoPeriodicCSI-RS: 0
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// Item 1
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// NZP-CSI-RS-Resource
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// nzp-CSI-RS-ResourceId: 1
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// resourceMapping
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// frequencyDomainAllocation: row1 (0)
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// row1: 10 [bit length 4, 4 LSB pad bits, 0001 .... decimal
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// value 1]
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// nrofPorts: p1 (0)
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// firstOFDMSymbolInTimeDomain: 4
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// cdm-Type: noCDM (0)
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// density: three (2)
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// three: NULL
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// freqBand
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// startingRB: 0
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// nrofRBs: 52
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// powerControlOffset: 0dB
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// powerControlOffsetSS: db0 (1)
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// scramblingID: 0
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// periodicityAndOffset: slots40 (7)
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// slots40: 11
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// qcl-InfoPeriodicCSI-RS: 0
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// Item 2
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// NZP-CSI-RS-Resource
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// nzp-CSI-RS-ResourceId: 2
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// resourceMapping
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// frequencyDomainAllocation: row1 (0)
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// row1: 10 [bit length 4, 4 LSB pad bits, 0001 .... decimal
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// value 1]
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// nrofPorts: p1 (0)
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// firstOFDMSymbolInTimeDomain: 8
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// cdm-Type: noCDM (0)
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// density: three (2)
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// three: NULL
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// freqBand
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// startingRB: 0
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// nrofRBs: 52
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// powerControlOffset: 0dB
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// powerControlOffsetSS: db0 (1)
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// scramblingID: 0
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// periodicityAndOffset: slots40 (7)
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// slots40: 11
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// qcl-InfoPeriodicCSI-RS: 0
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// Item 3
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// NZP-CSI-RS-Resource
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// nzp-CSI-RS-ResourceId: 3
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// resourceMapping
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// frequencyDomainAllocation: row1 (0)
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// row1: 10 [bit length 4, 4 LSB pad bits, 0001 .... decimal
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// value 1]
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// nrofPorts: p1 (0)
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// firstOFDMSymbolInTimeDomain: 4
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// cdm-Type: noCDM (0)
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// density: three (2)
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// three: NULL
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// freqBand
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// startingRB: 0
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// nrofRBs: 52
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// powerControlOffset: 0dB
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// powerControlOffsetSS: db0 (1)
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// scramblingID: 0
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// periodicityAndOffset: slots40 (7)
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// slots40: 12
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// qcl-InfoPeriodicCSI-RS: 0
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// Item 4
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// NZP-CSI-RS-Resource
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// nzp-CSI-RS-ResourceId: 4
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// resourceMapping
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// frequencyDomainAllocation: row1 (0)
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// row1: 10 [bit length 4, 4 LSB pad bits, 0001 .... decimal
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// value 1]
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// nrofPorts: p1 (0)
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// firstOFDMSymbolInTimeDomain: 8
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// cdm-Type: noCDM (0)
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// density: three (2)
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// three: NULL
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// freqBand
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// startingRB: 0
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// nrofRBs: 52
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// powerControlOffset: 0dB
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// powerControlOffsetSS: db0 (1)
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// scramblingID: 0
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// periodicityAndOffset: slots40 (7)
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// slots40: 12
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// qcl-InfoPeriodicCSI-RS: 0
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// nzp-CSI-RS-ResourceSetToAddModList: 2 items
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// Item 0
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// NZP-CSI-RS-ResourceSet
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// nzp-CSI-ResourceSetId: 0
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// nzp-CSI-RS-Resources: 1 item
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// Item 0
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// NZP-CSI-RS-ResourceId: 0
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// Item 1
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// NZP-CSI-RS-ResourceSet
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// nzp-CSI-ResourceSetId: 1
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// nzp-CSI-RS-Resources: 4 items
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// Item 0
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// NZP-CSI-RS-ResourceId: 1
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// Item 1
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// NZP-CSI-RS-ResourceId: 2
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// Item 2
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// NZP-CSI-RS-ResourceId: 3
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// Item 3
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// NZP-CSI-RS-ResourceId: 4
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// trs-Info: true (0)
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// csi-IM-ResourceToAddModList: 1 item
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// Item 0
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// CSI-IM-Resource
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// csi-IM-ResourceId: 0
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// csi-IM-ResourceElementPattern: pattern1 (1)
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// pattern1
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// subcarrierLocation-p1: s8 (2)
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// symbolLocation-p1: 8
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// freqBand
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// startingRB: 0
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// nrofRBs: 52
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// periodicityAndOffset: slots80 (9)
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// slots80: 1
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// csi-IM-ResourceSetToAddModList: 1 item
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// Item 0
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// CSI-IM-ResourceSet
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// csi-IM-ResourceSetId: 0
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// csi-IM-Resources: 1 item
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// Item 0
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// CSI-IM-ResourceId: 0
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// csi-ResourceConfigToAddModList: 3 items
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// Item 0
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// CSI-ResourceConfig
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// csi-ResourceConfigId: 0
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// csi-RS-ResourceSetList: nzp-CSI-RS-SSB (0)
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// nzp-CSI-RS-SSB
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// nzp-CSI-RS-ResourceSetList: 1 item
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// Item 0
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// NZP-CSI-RS-ResourceSetId: 0
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// bwp-Id: 0
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// resourceType: periodic (2)
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// Item 1
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// CSI-ResourceConfig
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// csi-ResourceConfigId: 1
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// csi-RS-ResourceSetList: csi-IM-ResourceSetList (1)
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// csi-IM-ResourceSetList: 1 item
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// Item 0
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// CSI-IM-ResourceSetId: 0
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// bwp-Id: 0
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// resourceType: periodic (2)
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// Item 2
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// CSI-ResourceConfig
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// csi-ResourceConfigId: 2
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// csi-RS-ResourceSetList: nzp-CSI-RS-SSB (0)
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// nzp-CSI-RS-SSB
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// nzp-CSI-RS-ResourceSetList: 1 item
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// Item 0
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// NZP-CSI-RS-ResourceSetId: 1
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// bwp-Id: 0
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// resourceType: periodic (2)
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// csi-ReportConfigToAddModList: 1 item
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// Item 0
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// CSI-ReportConfig
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// reportConfigId: 0
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// resourcesForChannelMeasurement: 0
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// csi-IM-ResourcesForInterference: 1
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// reportConfigType: periodic (0)
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// periodic
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// reportSlotConfig: slots80 (7)
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// slots80: 9
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// pucch-CSI-ResourceList: 1 item
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// Item 0
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// PUCCH-CSI-Resource
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// uplinkBandwidthPartId: 0
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// pucch-Resource: 17
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// reportQuantity: cri-RI-PMI-CQI (1)
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// cri-RI-PMI-CQI: NULL
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// reportFreqConfiguration
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// cqi-FormatIndicator: widebandCQI (0)
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// timeRestrictionForChannelMeasurements: notConfigured (1)
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// timeRestrictionForInterferenceMeasurements: notConfigured (1)
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// groupBasedBeamReporting: disabled (1)
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// disabled
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// cqi-Table: table2 (1)
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// subbandSize: value1 (0)
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// tag-Id: 0
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}
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class ue_dummy_stack : public srsue::stack_interface_phy_nr
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|
{
|
|
|
|
|
private:
|
|
|
|
|
uint16_t rnti = 0;
|
|
|
|
|
bool valid = false;
|
|
|
|
|
|
|
|
|
|
struct dummy_harq_proc {
|
|
|
|
|
static const uint32_t MAX_TB_SZ = SRSRAN_LDPC_MAX_LEN_CB * SRSRAN_SCH_NR_MAX_NOF_CB_LDPC;
|
|
|
|
|
srsran_softbuffer_rx_t softbuffer = {};
|
|
|
|
|
|
|
|
|
|
dummy_harq_proc()
|
|
|
|
|
{
|
|
|
|
|
// Initialise softbuffer
|
|
|
|
|
if (srsran_softbuffer_rx_init_guru(&softbuffer, SRSRAN_SCH_NR_MAX_NOF_CB_LDPC, SRSRAN_LDPC_MAX_LEN_ENCODED_CB) <
|
|
|
|
|
SRSRAN_SUCCESS) {
|
|
|
|
|
ERROR("Error Tx buffer");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
~dummy_harq_proc() { srsran_softbuffer_rx_free(&softbuffer); }
|
|
|
|
|
};
|
|
|
|
|
srsran::circular_array<dummy_harq_proc, SRSRAN_MAX_HARQ_PROC_DL_NR> rx_harq_proc;
|
|
|
|
|
|
|
|
|
|
public:
|
|
|
|
|
struct args_t {
|
|
|
|
|
uint16_t rnti = 0x1234;
|
|
|
|
|
};
|
|
|
|
|
ue_dummy_stack(const args_t& args) : rnti(args.rnti) { valid = true; }
|
|
|
|
|
void in_sync() override {}
|
|
|
|
|
void out_of_sync() override {}
|
|
|
|
|
void run_tti(const uint32_t tti) override {}
|
|
|
|
|
int sf_indication(const uint32_t tti) override { return 0; }
|
|
|
|
|
sched_rnti_t get_dl_sched_rnti_nr(const uint32_t tti) override { return sched_rnti_t(); }
|
|
|
|
|
sched_rnti_t get_ul_sched_rnti_nr(const uint32_t tti) override { return sched_rnti_t(); }
|
|
|
|
|
void new_grant_dl(const uint32_t cc_idx, const mac_nr_grant_dl_t& grant, tb_action_dl_t* action) override {}
|
|
|
|
|
sched_rnti_t get_dl_sched_rnti_nr(const uint32_t tti) override { return {rnti, srsran_rnti_type_c}; }
|
|
|
|
|
sched_rnti_t get_ul_sched_rnti_nr(const uint32_t tti) override { return {rnti, srsran_rnti_type_c}; }
|
|
|
|
|
void new_grant_dl(const uint32_t cc_idx, const mac_nr_grant_dl_t& grant, tb_action_dl_t* action) override
|
|
|
|
|
{
|
|
|
|
|
action->tb.enabled = true;
|
|
|
|
|
action->tb.softbuffer = &rx_harq_proc[grant.pid].softbuffer;
|
|
|
|
|
}
|
|
|
|
|
void tb_decoded(const uint32_t cc_idx, const mac_nr_grant_dl_t& grant, tb_action_dl_result_t result) override {}
|
|
|
|
|
void new_grant_ul(const uint32_t cc_idx, const mac_nr_grant_ul_t& grant, tb_action_ul_t* action) override {}
|
|
|
|
|
void prach_sent(uint32_t tti, uint32_t s_id, uint32_t t_id, uint32_t f_id, uint32_t ul_carrier_id) override {}
|
|
|
|
|
bool sr_opportunity(uint32_t tti, uint32_t sr_id, bool meas_gap, bool ul_sch_tx) override { return false; }
|
|
|
|
|
bool is_valid() const { return valid; }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
class gnb_dummy_stack : public srsenb::stack_interface_phy_nr
|
|
|
|
|
{
|
|
|
|
|
private:
|
|
|
|
|
srslog::basic_logger& logger = srslog::fetch_basic_logger("GNB STK");
|
|
|
|
|
const uint16_t rnti = 0x1234;
|
|
|
|
|
const uint32_t mcs = 1;
|
|
|
|
|
const srsran::circular_array<bool, SRSRAN_NOF_SF_X_FRAME> pdsch_mask;
|
|
|
|
|
srsran::circular_array<srsran_dci_location_t, SRSRAN_NOF_SF_X_FRAME> dci_dl_location;
|
|
|
|
|
srsran::circular_array<srsran_dci_location_t, SRSRAN_NOF_SF_X_FRAME> dci_ul_location;
|
|
|
|
|
srsran::circular_array<uint32_t, SRSRAN_NOF_SF_X_FRAME> dl_data_to_ul_ack;
|
|
|
|
|
bool valid = false;
|
|
|
|
|
srsran_search_space_t ss = {};
|
|
|
|
|
srsran_dci_format_nr_t dci_format_ul = SRSRAN_DCI_FORMAT_NR_COUNT;
|
|
|
|
|
srsran_dci_format_nr_t dci_format_dl = SRSRAN_DCI_FORMAT_NR_COUNT;
|
|
|
|
|
uint32_t dl_freq_res = 0;
|
|
|
|
|
uint32_t dl_time_res = 0;
|
|
|
|
|
srsran_random_t random_gen = nullptr;
|
|
|
|
|
|
|
|
|
|
struct dummy_harq_proc {
|
|
|
|
|
static const uint32_t MAX_TB_SZ = SRSRAN_LDPC_MAX_LEN_CB * SRSRAN_SCH_NR_MAX_NOF_CB_LDPC;
|
|
|
|
|
std::vector<uint8_t> data;
|
|
|
|
|
srsran_softbuffer_tx_t softbuffer = {};
|
|
|
|
|
|
|
|
|
|
dummy_harq_proc()
|
|
|
|
|
{
|
|
|
|
|
// Allocate data
|
|
|
|
|
data.resize(MAX_TB_SZ);
|
|
|
|
|
|
|
|
|
|
// Initialise softbuffer
|
|
|
|
|
if (srsran_softbuffer_tx_init_guru(&softbuffer, SRSRAN_SCH_NR_MAX_NOF_CB_LDPC, SRSRAN_LDPC_MAX_LEN_ENCODED_CB) <
|
|
|
|
|
SRSRAN_SUCCESS) {
|
|
|
|
|
ERROR("Error Tx buffer");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
~dummy_harq_proc() { srsran_softbuffer_tx_free(&softbuffer); }
|
|
|
|
|
};
|
|
|
|
|
srsran::circular_array<dummy_harq_proc, SRSRAN_MAX_HARQ_PROC_DL_NR> tx_harq_proc;
|
|
|
|
|
|
|
|
|
|
public:
|
|
|
|
|
struct args_t {
|
|
|
|
|
srsran::phy_cfg_nr_t phy_cfg; ///< Physical layer configuration
|
|
|
|
|
uint16_t rnti = 0x1234; ///< C-RNTI
|
|
|
|
|
uint32_t mcs = 10; ///< Modulation code scheme
|
|
|
|
|
srsran::circular_array<bool, SRSRAN_NOF_SF_X_FRAME> pdsch_mask = {}; ///< PDSCH scheduling mask
|
|
|
|
|
uint32_t ss_id = 1; ///< Search Space identifier
|
|
|
|
|
uint32_t pdcch_aggregation_level = 0; ///< PDCCH aggregation level
|
|
|
|
|
uint32_t pdcch_dl_candidate_index = 0; ///< PDCCH DL DCI candidate index
|
|
|
|
|
uint32_t pdcch_ul_candidate_index = 0; ///< PDCCH UL DCI candidate index
|
|
|
|
|
uint32_t dl_start_rb = 0; ///< Start resource block
|
|
|
|
|
uint32_t dl_length_rb = 0l; ///< Number of resource blocks
|
|
|
|
|
uint32_t dl_time_res = 0; ///< PDSCH time resource
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gnb_dummy_stack(args_t args) :
|
|
|
|
|
pdsch_mask(args.pdsch_mask),
|
|
|
|
|
mcs(args.mcs),
|
|
|
|
|
rnti(args.rnti),
|
|
|
|
|
dl_time_res(args.dl_time_res)
|
|
|
|
|
{
|
|
|
|
|
random_gen = srsran_random_init(0x1234);
|
|
|
|
|
|
|
|
|
|
// Select search space
|
|
|
|
|
if (args.ss_id >= SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE) {
|
|
|
|
|
logger.error("Search Space Id (%d) is out-of-range (%d)", args.ss_id, SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (not args.phy_cfg.pdcch.search_space_present[args.ss_id]) {
|
|
|
|
|
logger.error("Search Space Id (%d) is not present", args.ss_id);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
ss = args.phy_cfg.pdcch.search_space[args.ss_id];
|
|
|
|
|
|
|
|
|
|
// Select CORESET
|
|
|
|
|
if (ss.coreset_id >= SRSRAN_UE_DL_NR_MAX_NOF_CORESET) {
|
|
|
|
|
logger.error("CORESET Id (%d) is out-of-range (%d)", ss.coreset_id, SRSRAN_UE_DL_NR_MAX_NOF_CORESET);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (not args.phy_cfg.pdcch.coreset_present[ss.coreset_id]) {
|
|
|
|
|
logger.error("CORESET Id (%d) is not present", args.ss_id);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
const srsran_coreset_t& coreset = args.phy_cfg.pdcch.coreset[ss.coreset_id];
|
|
|
|
|
|
|
|
|
|
// Select DCI locations
|
|
|
|
|
for (uint32_t slot = 0; slot < SRSRAN_NOF_SF_X_FRAME; slot++) {
|
|
|
|
|
std::array<uint32_t, SRSRAN_SEARCH_SPACE_MAX_NOF_CANDIDATES_NR> ncce = {};
|
|
|
|
|
int n = srsran_pdcch_nr_locations_coreset(&coreset, &ss, rnti, args.pdcch_aggregation_level, slot++, ncce.data());
|
|
|
|
|
if (n < SRSRAN_SUCCESS) {
|
|
|
|
|
logger.error(
|
|
|
|
|
"Error generating locations for slot %d and aggregation level %d", slot, args.pdcch_aggregation_level);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
uint32_t nof_candidates = (uint32_t)n;
|
|
|
|
|
|
|
|
|
|
// DCI DL
|
|
|
|
|
if (args.pdcch_dl_candidate_index >= nof_candidates or
|
|
|
|
|
args.pdcch_dl_candidate_index >= SRSRAN_SEARCH_SPACE_MAX_NOF_CANDIDATES_NR) {
|
|
|
|
|
logger.error("Candidate index %d exceeds the number of candidates %d for aggregation level %d",
|
|
|
|
|
args.pdcch_dl_candidate_index,
|
|
|
|
|
n,
|
|
|
|
|
args.pdcch_aggregation_level);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
dci_dl_location[slot].L = args.pdcch_aggregation_level;
|
|
|
|
|
dci_dl_location[slot].ncce = ncce[args.pdcch_dl_candidate_index];
|
|
|
|
|
|
|
|
|
|
// DCI UL
|
|
|
|
|
if (args.pdcch_ul_candidate_index >= nof_candidates or
|
|
|
|
|
args.pdcch_ul_candidate_index >= SRSRAN_SEARCH_SPACE_MAX_NOF_CANDIDATES_NR) {
|
|
|
|
|
logger.error("Candidate index %d exceeds the number of candidates %d for aggregation level %d",
|
|
|
|
|
args.pdcch_ul_candidate_index,
|
|
|
|
|
n,
|
|
|
|
|
args.pdcch_aggregation_level);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
dci_ul_location[slot].L = args.pdcch_aggregation_level;
|
|
|
|
|
dci_ul_location[slot].ncce = ncce[args.pdcch_ul_candidate_index];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Select DCI formats
|
|
|
|
|
for (uint32_t i = 0; i < ss.nof_formats; i++) {
|
|
|
|
|
// Select DL format
|
|
|
|
|
if (ss.formats[i] == srsran_dci_format_nr_1_0 or ss.formats[i] == srsran_dci_format_nr_1_1) {
|
|
|
|
|
dci_format_dl = ss.formats[i];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Select DL format
|
|
|
|
|
if (ss.formats[i] == srsran_dci_format_nr_0_0 or ss.formats[i] == srsran_dci_format_nr_0_1) {
|
|
|
|
|
dci_format_ul = ss.formats[i];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Validate that a DCI format is selected
|
|
|
|
|
if (dci_format_dl == SRSRAN_DCI_FORMAT_NR_COUNT or dci_format_ul == SRSRAN_DCI_FORMAT_NR_COUNT) {
|
|
|
|
|
logger.error("Missing valid DL or UL DCI format in search space");
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Select DL frequency domain resources
|
|
|
|
|
dl_freq_res = srsran_ra_nr_type1_riv(args.phy_cfg.carrier.nof_prb, args.dl_start_rb, args.dl_length_rb);
|
|
|
|
|
|
|
|
|
|
// Setup DL Data to ACK timing
|
|
|
|
|
for (uint32_t i = 0; i < SRSRAN_NOF_SF_X_FRAME; i++) {
|
|
|
|
|
dl_data_to_ul_ack[i] = args.phy_cfg.harq_ack.dl_data_to_ul_ack[i % SRSRAN_MAX_NOF_DL_DATA_TO_UL];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// If reached this point the configuration is valid
|
|
|
|
|
valid = true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
~gnb_dummy_stack() { srsran_random_free(random_gen); }
|
|
|
|
|
|
|
|
|
|
bool is_valid() const { return valid; }
|
|
|
|
|
|
|
|
|
|
int sf_indication(const uint32_t tti) override { return 0; }
|
|
|
|
|
int rx_data_indication(rx_data_ind_t& grant) override { return 0; }
|
|
|
|
|
|
|
|
|
|
int get_dl_sched(uint32_t tti, dl_sched_list_t& dl_sched_res) override
|
|
|
|
|
{
|
|
|
|
|
dl_sched_res[0].nof_grants = 0;
|
|
|
|
|
// Check input
|
|
|
|
|
if (dl_sched_res.size() == 0) {
|
|
|
|
|
return SRSRAN_ERROR;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Check PDSCH mask, if no PDSCH shall be scheduled, do not set any grant and skip
|
|
|
|
|
if (not pdsch_mask[tti]) {
|
|
|
|
|
dl_sched_res[0].nof_grants = 0;
|
|
|
|
|
return SRSRAN_SUCCESS;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Select grant and set data
|
|
|
|
|
dl_sched_grant_t& grant = dl_sched_res[0].pdsch[0];
|
|
|
|
|
grant.data[0] = tx_harq_proc[tti].data.data();
|
|
|
|
|
grant.softbuffer_tx[0] = &tx_harq_proc[tti].softbuffer;
|
|
|
|
|
|
|
|
|
|
// Second TB is not used
|
|
|
|
|
grant.data[1] = nullptr;
|
|
|
|
|
grant.softbuffer_tx[1] = nullptr;
|
|
|
|
|
|
|
|
|
|
// Reset Tx softbuffer always
|
|
|
|
|
srsran_softbuffer_tx_reset(grant.softbuffer_tx[0]);
|
|
|
|
|
|
|
|
|
|
// Generate random data
|
|
|
|
|
srsran_random_byte_vector(random_gen, grant.data[0], SRSRAN_LDPC_MAX_LEN_CB * SRSRAN_SCH_NR_MAX_NOF_CB_LDPC / 8);
|
|
|
|
|
|
|
|
|
|
// It currently support only one grant
|
|
|
|
|
dl_sched_res[0].nof_grants = 1;
|
|
|
|
|
|
|
|
|
|
// Fill DCI
|
|
|
|
|
srsran_dci_dl_nr_t& dci = grant.dci;
|
|
|
|
|
dci.ctx.location = dci_dl_location[tti];
|
|
|
|
|
dci.ctx.ss_type = ss.type;
|
|
|
|
|
dci.ctx.coreset_id = ss.coreset_id;
|
|
|
|
|
dci.ctx.rnti_type = srsran_rnti_type_c;
|
|
|
|
|
dci.ctx.format = dci_format_dl;
|
|
|
|
|
dci.ctx.rnti = rnti;
|
|
|
|
|
dci.freq_domain_assigment = dl_freq_res;
|
|
|
|
|
dci.time_domain_assigment = dl_time_res;
|
|
|
|
|
dci.mcs = mcs;
|
|
|
|
|
dci.rv = 0;
|
|
|
|
|
dci.ndi = (tti / SRSRAN_NOF_SF_X_FRAME) % 2;
|
|
|
|
|
dci.pid = tti % SRSRAN_NOF_SF_X_FRAME;
|
|
|
|
|
dci.dai = tti % SRSRAN_NOF_SF_X_FRAME;
|
|
|
|
|
dci.tpc = 1;
|
|
|
|
|
dci.pucch_resource = 0;
|
|
|
|
|
dci.harq_feedback = dl_data_to_ul_ack[tti];
|
|
|
|
|
|
|
|
|
|
return SRSRAN_SUCCESS;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int get_ul_sched(uint32_t tti, ul_sched_list_t& ul_sched_res) override { return 0; }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
int main(int argc, char** argv)
|
|
|
|
|
{
|
|
|
|
|
srslog::init();
|
|
|
|
|
|
|
|
|
|
// Parse test bench arguments
|
|
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test_bench::args_t args(argc, argv);
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args.gnb_args.log_id_preamble = "GNB/";
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args.gnb_args.log_level = "warning";
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args.gnb_args.nof_workers = 1;
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args.ue_args.log.id_preamble = " UE/";
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args.ue_args.log.phy_level = "warning";
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args.ue_args.log.phy_hex_limit = 0;
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args.ue_args.nof_phy_threads = 1;
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// Parse arguments
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TESTASSERT(args.valid);
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ue_dummy_stack ue_stack;
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gnb_dummy_stack gnb_stack;
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// Create UE stack arguments
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ue_dummy_stack::args_t ue_stack_args = {};
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ue_stack_args.rnti = 0x1234;
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// Create UE stack
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ue_dummy_stack ue_stack(ue_stack_args);
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TESTASSERT(ue_stack.is_valid());
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// Create GNB stack arguments
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gnb_dummy_stack::args_t gnb_stack_args = {};
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gnb_stack_args.rnti = 0x1234;
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gnb_stack_args.mcs = 10;
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for (bool& mask : gnb_stack_args.pdsch_mask) {
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mask = true;
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}
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gnb_stack_args.phy_cfg = args.phy_cfg;
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gnb_stack_args.dl_start_rb = 0;
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gnb_stack_args.dl_length_rb = args.phy_cfg.carrier.nof_prb;
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// Create GNB stack
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gnb_dummy_stack gnb_stack(gnb_stack_args);
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TESTASSERT(gnb_stack.is_valid());
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// Create test bench
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test_bench tb(args, gnb_stack, ue_stack);
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@ -554,10 +522,10 @@ int main(int argc, char** argv)
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// Assert bench is initialised correctly
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TESTASSERT(tb.is_initialised());
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for (uint32_t i = 0; i < 1000; i++) {
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for (uint32_t i = 0; i < 20; i++) {
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TESTASSERT(tb.run_tti());
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}
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// If reached here, the test is successful
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return SRSRAN_SUCCESS;
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}
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}
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Xavier Arteaga
4 years ago
committed by
Xavier Arteaga