set minimum snr under which the UL SNR estimate is not updated

master
Francisco 4 years ago committed by Ismael Gomez
parent 8df6ed07c6
commit a17e3b71e7

@ -43,6 +43,9 @@ struct sched_ue_cell {
const sched_interface::ue_cfg_t* get_ue_cfg() const { return configured() ? ue_cfg : nullptr; } const sched_interface::ue_cfg_t* get_ue_cfg() const { return configured() ? ue_cfg : nullptr; }
cc_st cc_state() const { return cc_state_; } cc_st cc_state() const { return cc_state_; }
int set_ul_crc(tti_point tti_rx, bool crc_res);
int set_ul_snr(tti_point tti_rx, float ul_snr, uint32_t ul_ch_code);
const uint16_t rnti; const uint16_t rnti;
/// Cell const configuration /// Cell const configuration

@ -55,6 +55,11 @@ public:
void set_snr(float snr, uint32_t ul_ch_code) void set_snr(float snr, uint32_t ul_ch_code)
{ {
static const float MIN_UL_SNR = -4.0f;
if (snr < MIN_UL_SNR) {
// Assume signal was not sent
return;
}
if (ul_ch_code < nof_ul_ch_code) { if (ul_ch_code < nof_ul_ch_code) {
snr_estim_list[ul_ch_code].pending_snr = snr; snr_estim_list[ul_ch_code].pending_snr = snr;
} }

@ -245,14 +245,7 @@ int sched_ue::set_ack_info(tti_point tti_rx, uint32_t enb_cc_idx, uint32_t tb_id
void sched_ue::set_ul_crc(tti_point tti_rx, uint32_t enb_cc_idx, bool crc_res) void sched_ue::set_ul_crc(tti_point tti_rx, uint32_t enb_cc_idx, bool crc_res)
{ {
if (cells[enb_cc_idx].cc_state() != cc_st::idle) { cells[enb_cc_idx].set_ul_crc(tti_rx, crc_res);
int ret = cells[enb_cc_idx].harq_ent.set_ul_crc(tti_rx, 0, crc_res);
if (ret < 0) {
logger.warning("Received UL CRC for invalid tti_rx=%d", (int)tti_rx.to_uint());
}
} else {
logger.warning("Received UL CRC for invalid cell index %d", enb_cc_idx);
}
} }
void sched_ue::set_dl_ri(tti_point tti_rx, uint32_t enb_cc_idx, uint32_t ri) void sched_ue::set_dl_ri(tti_point tti_rx, uint32_t enb_cc_idx, uint32_t ri)
@ -286,15 +279,7 @@ void sched_ue::set_dl_cqi(tti_point tti_rx, uint32_t enb_cc_idx, uint32_t cqi)
void sched_ue::set_ul_snr(tti_point tti_rx, uint32_t enb_cc_idx, float snr, uint32_t ul_ch_code) void sched_ue::set_ul_snr(tti_point tti_rx, uint32_t enb_cc_idx, float snr, uint32_t ul_ch_code)
{ {
if (cells[enb_cc_idx].cc_state() != cc_st::idle) { cells[enb_cc_idx].set_ul_snr(tti_rx, snr, ul_ch_code);
cells[enb_cc_idx].tpc_fsm.set_snr(snr, ul_ch_code);
if (ul_ch_code == tpc::PUSCH_CODE) {
cells[enb_cc_idx].ul_cqi = srsran_cqi_from_snr(snr);
cells[enb_cc_idx].ul_cqi_tti_rx = tti_rx;
}
} else {
logger.warning("Received SNR info for invalid cell index %d", enb_cc_idx);
}
} }
/******************************************************* /*******************************************************

@ -16,6 +16,14 @@
#include "srsenb/hdr/stack/mac/schedulers/sched_base.h" #include "srsenb/hdr/stack/mac/schedulers/sched_base.h"
#include <numeric> #include <numeric>
#define CHECK_INVALID_FEEDBACK(feedback_type) \
do { \
if (cc_state() == cc_st::idle) { \
logger.warning("SCHED: rnti=0x%x received " feedback_type " for idle cc=%d", cell_cfg->enb_cc_idx); \
return SRSRAN_ERROR; \
} \
} while (0)
namespace srsenb { namespace srsenb {
/******************************************************* /*******************************************************
@ -160,6 +168,29 @@ void sched_ue_cell::set_dl_wb_cqi(tti_point tti_rx, uint32_t dl_cqi_)
} }
} }
int sched_ue_cell::set_ul_crc(tti_point tti_rx, bool crc_res)
{
CHECK_INVALID_FEEDBACK("UL CRC");
// Update HARQ process
int pid = harq_ent.set_ul_crc(tti_rx, 0, crc_res);
if (pid < 0) {
logger.warning("SCHED: rnti=0x%x received UL CRC for invalid tti_rx=%d", (int)tti_rx.to_uint());
return SRSRAN_ERROR;
}
return pid;
}
int sched_ue_cell::set_ul_snr(tti_point tti_rx, float ul_snr, uint32_t ul_ch_code)
{
CHECK_INVALID_FEEDBACK("UL SNR estimate");
tpc_fsm.set_snr(ul_snr, ul_ch_code);
if (ul_ch_code == tpc::PUSCH_CODE) {
ul_cqi = srsran_cqi_from_snr(ul_snr);
ul_cqi_tti_rx = tti_rx;
}
return SRSRAN_SUCCESS;
}
/************************************************************* /*************************************************************
* TBS/MCS derivation * TBS/MCS derivation
************************************************************/ ************************************************************/

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