sched,nr: change ra nr sched and bwp allocator interfaces

master
Francisco Paisana 3 years ago
parent 3d810bc88a
commit 8f00c9363c

@ -54,7 +54,7 @@ public:
explicit ra_sched(const bwp_params& bwp_cfg_);
int dl_rach_info(const dl_sched_rar_info_t& rar_info);
void run_slot(bwp_slot_allocator& slot_grid, slot_ue_map_t& slot_ues);
void run_slot(bwp_slot_allocator& slot_grid);
bool empty() const { return pending_rars.empty(); }
private:
@ -65,10 +65,8 @@ private:
srsran::bounded_vector<dl_sched_rar_info_t, sched_interface::MAX_RAR_LIST> msg3_grant;
};
alloc_result allocate_pending_rar(bwp_slot_allocator& slot_grid,
const pending_rar_t& rar,
slot_ue_map_t& slot_ues,
uint32_t& nof_grants_alloc);
alloc_result
allocate_pending_rar(bwp_slot_allocator& slot_grid, const pending_rar_t& rar, uint32_t& nof_grants_alloc);
const bwp_params* bwp_cfg = nullptr;
srslog::basic_logger& logger;

@ -83,13 +83,16 @@ class bwp_slot_allocator
public:
explicit bwp_slot_allocator(bwp_res_grid& bwp_grid_);
void new_slot(slot_point pdcch_slot_) { pdcch_slot = pdcch_slot_; }
void new_slot(slot_point pdcch_slot_, slot_ue_map_t& ues_)
{
pdcch_slot = pdcch_slot_;
slot_ues = &ues_;
}
alloc_result alloc_si(uint32_t aggr_idx, uint32_t si_idx, uint32_t si_ntx, const prb_interval& prbs);
alloc_result alloc_rar_and_msg3(uint16_t ra_rnti,
uint32_t aggr_idx,
prb_interval interv,
slot_ue_map_t& ues,
srsran::const_span<dl_sched_rar_info_t> pending_rars);
alloc_result alloc_pdsch(slot_ue& ue, const prb_grant& dl_grant);
alloc_result alloc_pusch(slot_ue& ue, const prb_grant& dl_mask);
@ -106,7 +109,8 @@ private:
srslog::basic_logger& logger;
bwp_res_grid& bwp_grid;
slot_point pdcch_slot;
slot_point pdcch_slot;
slot_ue_map_t* slot_ues;
};
} // namespace sched_nr_impl

@ -77,10 +77,8 @@ void si_sched::run_slot(bwp_slot_allocator& slot_alloc)
ra_sched::ra_sched(const bwp_params& bwp_cfg_) : bwp_cfg(&bwp_cfg_), logger(srslog::fetch_basic_logger("MAC")) {}
alloc_result ra_sched::allocate_pending_rar(bwp_slot_allocator& slot_grid,
const pending_rar_t& rar,
slot_ue_map_t& slot_ues,
uint32_t& nof_grants_alloc)
alloc_result
ra_sched::allocate_pending_rar(bwp_slot_allocator& slot_grid, const pending_rar_t& rar, uint32_t& nof_grants_alloc)
{
const uint32_t rar_aggr_level = 2;
const prb_bitmap& prbs = slot_grid.res_grid()[slot_grid.get_pdcch_tti()].dl_prbs.prbs();
@ -94,8 +92,8 @@ alloc_result ra_sched::allocate_pending_rar(bwp_slot_allocator& slot_grid,
prb_interval interv = find_empty_interval_of_length(prbs, nprb, start_prb_idx);
start_prb_idx = interv.start();
if (interv.length() == nprb) {
ret = slot_grid.alloc_rar_and_msg3(
rar.ra_rnti, rar_aggr_level, interv, slot_ues, msg3_grants.subspan(0, nof_grants_alloc));
ret =
slot_grid.alloc_rar_and_msg3(rar.ra_rnti, rar_aggr_level, interv, msg3_grants.subspan(0, nof_grants_alloc));
} else {
ret = alloc_result::no_sch_space;
}
@ -112,7 +110,7 @@ alloc_result ra_sched::allocate_pending_rar(bwp_slot_allocator& slot_grid,
return ret;
}
void ra_sched::run_slot(bwp_slot_allocator& slot_grid, slot_ue_map_t& slot_ues)
void ra_sched::run_slot(bwp_slot_allocator& slot_grid)
{
slot_point pdcch_slot = slot_grid.get_pdcch_tti();
slot_point msg3_slot = pdcch_slot + bwp_cfg->pusch_ra_list[0].msg3_delay;
@ -145,7 +143,7 @@ void ra_sched::run_slot(bwp_slot_allocator& slot_grid, slot_ue_map_t& slot_ues)
// Try to schedule DCIs + RBGs for RAR Grants
uint32_t nof_rar_allocs = 0;
alloc_result ret = allocate_pending_rar(slot_grid, rar, slot_ues, nof_rar_allocs);
alloc_result ret = allocate_pending_rar(slot_grid, rar, nof_rar_allocs);
if (ret == alloc_result::success) {
// If RAR allocation was successful:

@ -84,7 +84,6 @@ alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx, uint32_t si_idx, ui
alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint16_t ra_rnti,
uint32_t aggr_idx,
prb_interval interv,
slot_ue_map_t& ues,
srsran::const_span<dl_sched_rar_info_t> pending_rars)
{
static const uint32_t msg3_nof_prbs = 3, m = 0;
@ -148,7 +147,7 @@ alloc_result bwp_slot_allocator::alloc_rar_and_msg3(uint16_t
srsran_slot_cfg_t slot_cfg;
slot_cfg.idx = msg3_slot.slot_idx();
for (const dl_sched_rar_info_t& grant : pending_rars) {
slot_ue& ue = ues[grant.temp_crnti];
slot_ue& ue = (*slot_ues)[grant.temp_crnti];
// Allocate Msg3
prb_interval msg3_interv{last_msg3, last_msg3 + msg3_nof_prbs};

@ -91,10 +91,10 @@ void slot_cc_worker::run()
{
srsran_assert(running(), "scheduler worker::run() called for non-active worker");
bwp_alloc.new_slot(slot_rx + TX_ENB_DELAY);
bwp_alloc.new_slot(slot_rx + TX_ENB_DELAY, slot_ues);
// Allocate pending RARs
cell.bwps[0].ra.run_slot(bwp_alloc, slot_ues);
cell.bwps[0].ra.run_slot(bwp_alloc);
// TODO: Prioritize PDCCH scheduling for DL and UL data in a Round-Robin fashion
alloc_dl_ues();

@ -21,6 +21,7 @@ void test_pdcch_consistency(srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdc
if (pdcch.dci.ctx.rnti_type == srsran_rnti_type_ra) {
TESTASSERT_EQ(pdcch.dci.ctx.format, srsran_dci_format_nr_1_0);
TESTASSERT_EQ(pdcch.dci.ctx.ss_type, srsran_search_space_type_common_1);
TESTASSERT(pdcch.dci.ctx.location.L > 0);
}
}
}

@ -52,8 +52,8 @@ void test_single_prach()
mac_logger.set_context(pdcch_slot.to_uint());
slot_ues.clear();
slot_ues.insert(rnti, u.try_reserve(pdcch_slot, 0));
alloc.new_slot(pdcch_slot);
rasched.run_slot(alloc, slot_ues);
alloc.new_slot(pdcch_slot, slot_ues);
rasched.run_slot(alloc);
const bwp_slot_grid* result = &alloc.res_grid()[alloc.get_pdcch_tti()];
test_pdcch_consistency(result->dl_pdcchs);
++pdcch_slot;

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