Add support for NSA FDD on band n3, n5 and n7.

lib/include/srsran/interfaces/gnb_interfaces.h

@@ -161,6 +161,7 @@ public:
     srsran_carrier_nr_t   carrier;
     srsran_pdcch_cfg_nr_t pdcch;
     srsran_prach_cfg_t    prach;
+    srsran_duplex_mode_t  duplex_mode;
   };
 
   virtual int set_common_cfg(const common_cfg_t& common_cfg) = 0;

lib/include/srsran/interfaces/gnb_rrc_nr_interfaces.h

@@ -38,6 +38,8 @@ struct rrc_cell_cfg_nr_t {
   uint32_t             tac;      // Tracking area code
   uint32_t             dl_arfcn; // DL freq already included in phy_cell
   uint32_t             ul_arfcn; // UL freq also in phy_cell
+  uint32_t             band;
+  srsran_duplex_mode_t duplex_mode;
 };
 
 typedef std::vector<rrc_cell_cfg_nr_t> rrc_cell_list_nr_t;

lib/include/srsran/phy/phch/prach.h

@@ -23,6 +23,7 @@
 
 #include "srsran/config.h"
 #include "srsran/phy/common/phy_common.h"
+#include "srsran/phy/common/phy_common_nr.h"
 #include "srsran/phy/dft/dft.h"
 #include <complex.h>
 #include <stdbool.h>
@@ -117,7 +118,7 @@ typedef struct SRSRAN_API {
 } srsran_prach_sf_config_t;
 
 ///@brief Maximum number of subframe number candidates for PRACH NR configuration
-#define PRACH_NR_CFG_MAX_NOF_SF 5
+#define PRACH_NR_CFG_MAX_NOF_SF 10
 
 /**
  * @brief PRACH configuration for NR as described in TS 38.211 Tables 6.3.3.2-2, 6.3.3.2-3 and 6.3.3.2-4
@@ -177,11 +178,17 @@ SRSRAN_API bool srsran_prach_tti_opportunity_config_tdd(uint32_t  config_idx,
                                                         uint32_t  current_tti,
                                                         uint32_t* prach_idx);
 
+SRSRAN_API const prach_nr_config_t* srsran_prach_nr_get_cfg_fr1_paired(uint32_t config_idx);
+
+SRSRAN_API bool srsran_prach_nr_tti_opportunity_fr1_paired(uint32_t config_idx, uint32_t current_tti);
+
+SRSRAN_API uint32_t srsran_prach_nr_start_symbol_fr1_paired(uint32_t config_idx);
+
 SRSRAN_API const prach_nr_config_t* srsran_prach_nr_get_cfg_fr1_unpaired(uint32_t config_idx);
 
 SRSRAN_API bool srsran_prach_nr_tti_opportunity_fr1_unpaired(uint32_t config_idx, uint32_t current_tti);
 
-SRSRAN_API uint32_t srsran_prach_nr_start_symbol_fr1_unpaired(uint32_t config_idx);
+SRSRAN_API uint32_t srsran_prach_nr_start_symbol(uint32_t config_idx, srsran_duplex_mode_t duplex_mode);
 
 SRSRAN_API uint32_t srsran_prach_f_ra_tdd(uint32_t config_idx,
                                           uint32_t tdd_ul_dl_config,

lib/src/asn1/rrc_nr_utils.cc

@@ -274,6 +274,8 @@ bool make_phy_tdd_cfg(const tdd_ul_dl_cfg_common_s& tdd_ul_dl_cfg_common,
                       srsran_duplex_config_nr_t*    in_srsran_duplex_config_nr)
 {
   srsran_duplex_config_nr_t srsran_duplex_config_nr = {};
+  srsran_duplex_config_nr.mode                      = SRSRAN_DUPLEX_MODE_TDD;
+
   switch (tdd_ul_dl_cfg_common.pattern1.dl_ul_tx_periodicity) {
     case tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms1:
       srsran_duplex_config_nr.tdd.pattern1.period_ms = 1;

lib/src/common/phy_cfg_nr_default.cc

@@ -457,6 +457,8 @@ phy_cfg_nr_default_t::phy_cfg_nr_default_t(const reference_cfg_t& reference_cfg)
       make_prach_default_lte(prach);
       break;
   }
+
+  prach.tdd_config.configured = (duplex.mode == SRSRAN_DUPLEX_MODE_TDD);
 }
 
 } // namespace srsran

lib/src/phy/phch/prach.c

@@ -15,6 +15,7 @@
 #include <string.h>
 
 #include "srsran/phy/common/phy_common.h"
+#include "srsran/phy/common/phy_common_nr.h"
 #include "srsran/phy/phch/prach.h"
 #include "srsran/phy/utils/debug.h"
 #include "srsran/phy/utils/vector.h"
@@ -118,17 +119,21 @@ bool srsran_prach_tti_opportunity(srsran_prach_t* p, uint32_t current_tti, int a
     return false;
   }
 
+  uint32_t config_idx = p->config_idx;
+  if (p->tdd_config.configured) {
     if (p->is_nr) {
       return srsran_prach_nr_tti_opportunity_fr1_unpaired(p->config_idx, current_tti);
-  }
-
-  uint32_t config_idx = p->config_idx;
-  if (!p->tdd_config.configured) {
-    return srsran_prach_tti_opportunity_config_fdd(config_idx, current_tti, allowed_subframe);
     } else {
       return srsran_prach_tti_opportunity_config_tdd(
           config_idx, p->tdd_config.sf_config, current_tti, &p->current_prach_idx);
     }
+  } else {
+    if (p->is_nr) {
+      return srsran_prach_nr_tti_opportunity_fr1_paired(p->config_idx, current_tti);
+    } else {
+      return srsran_prach_tti_opportunity_config_fdd(config_idx, current_tti, allowed_subframe);
+    }
+  }
 }
 
 bool srsran_prach_tti_opportunity_config_fdd(uint32_t config_idx, uint32_t current_tti, int allowed_subframe)
@@ -281,6 +286,66 @@ void srsran_prach_sf_config(uint32_t config_idx, srsran_prach_sf_config_t* sf_co
   memcpy(sf_config, &prach_sf_config[config_idx % 16], sizeof(srsran_prach_sf_config_t));
 }
 
+const prach_nr_config_t* srsran_prach_nr_get_cfg_fr1_paired(uint32_t config_idx)
+{
+  if (config_idx < PRACH_NR_CFG_FR1_PAIRED_NOF_CFG) {
+    return &prach_nr_cfg_fr1_paired[config_idx];
+  }
+
+  ERROR("Invalid configuration index %d", config_idx);
+  return NULL;
+}
+
+bool srsran_prach_nr_tti_opportunity_fr1_paired(uint32_t config_idx, uint32_t current_tti)
+{
+  uint32_t sfn    = current_tti / SRSRAN_NOF_SF_X_FRAME;
+  uint32_t sf_idx = current_tti % SRSRAN_NOF_SF_X_FRAME;
+
+  // Get configuration
+  const prach_nr_config_t* cfg = srsran_prach_nr_get_cfg_fr1_paired(config_idx);
+  if (cfg == NULL) {
+    return false;
+  }
+
+  // Protect zero division
+  if (cfg->x == 0) {
+    ERROR("Invalid Zero value");
+    return false;
+  }
+
+  // Check for System Frame Number match
+  if (sfn % cfg->x != cfg->y) {
+    return false;
+  }
+
+  // Protect subframe number vector access
+  if (cfg->nof_subframe_number > PRACH_NR_CFG_MAX_NOF_SF) {
+    ERROR("Invalid number of subframes (%d)", cfg->nof_subframe_number);
+    return false;
+  }
+
+  // Check for subframe number match
+  for (uint32_t i = 0; i < cfg->nof_subframe_number; i++) {
+    if (cfg->subframe_number[i] == sf_idx) {
+      return true;
+    }
+  }
+
+  // If reached here, no opportunity
+  return false;
+}
+
+uint32_t srsran_prach_nr_start_symbol_fr1_paired(uint32_t config_idx)
+{
+  // Get configuration
+  const prach_nr_config_t* cfg = srsran_prach_nr_get_cfg_fr1_paired(config_idx);
+  if (cfg == NULL) {
+    return 0;
+  }
+
+  return cfg->starting_symbol;
+}
+
 const prach_nr_config_t* srsran_prach_nr_get_cfg_fr1_unpaired(uint32_t config_idx)
 {
   if (config_idx < PRACH_NR_CFG_FR1_UNPAIRED_NOF_CFG) {
@@ -330,12 +395,21 @@ bool srsran_prach_nr_tti_opportunity_fr1_unpaired(uint32_t config_idx, uint32_t
   return false;
 }
 
-uint32_t srsran_prach_nr_start_symbol_fr1_unpaired(uint32_t config_idx)
+uint32_t srsran_prach_nr_start_symbol(uint32_t config_idx, srsran_duplex_mode_t duplex_mode)
 {
+  const prach_nr_config_t* cfg;
+  if (duplex_mode == SRSRAN_DUPLEX_MODE_TDD) {
     // Get configuration
-  const prach_nr_config_t* cfg = srsran_prach_nr_get_cfg_fr1_unpaired(config_idx);
+    cfg = srsran_prach_nr_get_cfg_fr1_unpaired(config_idx);
     if (cfg == NULL) {
-    return false;
+      return 0;
+    }
+  } else {
+    // Get configuration
+    cfg = srsran_prach_nr_get_cfg_fr1_paired(config_idx);
+    if (cfg == NULL) {
+      return 0;
+    }
   }
 
   return cfg->starting_symbol;

lib/src/phy/phch/prach_tables.h

@@ -446,10 +446,29 @@ static const prach_nr_config_t prach_nr_cfg_fr1_unpaired[PRACH_NR_CFG_FR1_UNPAIR
     {0, 1, 0, {8}, 1, 0},          {0, 1, 0, {7}, 1, 0},
     {0, 1, 0, {6}, 1, 0},          {0, 1, 0, {5}, 1, 0},
     {0, 1, 0, {4}, 1, 0},          {0, 1, 0, {3}, 1, 0},
-    {0, 1, 0, {2}, 1, 0},          {0, 1, 0, {1, 6}, 1, 0},
-    {0, 1, 0, {1, 6}, 1, 7},       {0, 1, 0, {4, 9}, 1, 0},
-    {0, 1, 0, {3, 8}, 1, 0},       {0, 1, 0, {2, 7}, 1, 0},
-    {0, 1, 0, {8, 9}, 1, 0},       {0, 1, 0, {4, 8, 9}, 1, 0},
-    {0, 1, 0, {3, 4, 9}, 1, 0},    {0, 1, 0, {7, 8, 9}, 1, 0},
-    {0, 1, 0, {3, 4, 8, 9}, 1, 0}, {0, 1, 0, {6, 7, 8, 9}, 1, 0},
-    {0, 1, 0, {1, 4, 6, 9}, 1, 0}, {0, 1, 0, {1, 3, 5, 7, 9}, 1, 0}};
+    {0, 1, 0, {2}, 1, 0},          {0, 1, 0, {1, 6}, 2, 0},
+    {0, 1, 0, {1, 6}, 2, 7},       {0, 1, 0, {4, 9}, 2, 0},
+    {0, 1, 0, {3, 8}, 2, 0},       {0, 1, 0, {2, 7}, 2, 0},
+    {0, 1, 0, {8, 9}, 2, 0},       {0, 1, 0, {4, 8, 9}, 3, 0},
+    {0, 1, 0, {3, 4, 9}, 3, 0},    {0, 1, 0, {7, 8, 9}, 3, 0},
+    {0, 1, 0, {3, 4, 8, 9}, 4, 0}, {0, 1, 0, {6, 7, 8, 9}, 4, 0},
+    {0, 1, 0, {1, 4, 6, 9}, 4, 0}, {0, 1, 0, {1, 3, 5, 7, 9}, 5, 0}};
+
+#define PRACH_NR_CFG_FR1_PAIRED_NOF_CFG 28
+
+// Table 6.3.3.2-2: Random access configurations for FR1 and paired spectrum.
+static const prach_nr_config_t prach_nr_cfg_fr1_paired[PRACH_NR_CFG_FR1_PAIRED_NOF_CFG] = {
+    {0, 16, 1, {1}, 1, 0},            {0, 16, 1, {4}, 1, 0},
+    {0, 16, 1, {7}, 1, 0},            {0, 16, 1, {9}, 1, 0},
+    {0, 8, 1, {1}, 1, 0},             {0, 8, 1, {4}, 1, 0},
+    {0, 8, 1, {7}, 1, 0},             {0, 8, 1, {9}, 1, 0},
+    {0, 4, 1, {1}, 1, 0},             {0, 4, 1, {4}, 1, 0},
+    {0, 4, 1, {7}, 1, 0},             {0, 4, 1, {9}, 1, 0},
+    {0, 2, 1, {1}, 1, 0},             {0, 2, 1, {4}, 1, 0},
+    {0, 2, 1, {7}, 1, 0},             {0, 2, 1, {9}, 1, 0},
+    {0, 1, 0, {1}, 1, 0},             {0, 1, 0, {4}, 1, 0},
+    {0, 1, 0, {7}, 1, 0},             {0, 1, 0, {1, 6}, 2, 0},
+    {0, 1, 0, {2, 7}, 2, 0},          {0, 1, 0, {3, 8}, 2, 0},
+    {0, 1, 0, {1, 4, 7}, 3, 0},       {0, 1, 0, {2, 5, 8}, 3, 0},
+    {0, 1, 0, {3, 6, 9}, 3, 0},       {0, 1, 0, {0, 2, 4, 6, 8}, 5, 0},
+    {0, 1, 0, {1, 3, 5, 7, 9}, 5, 0}, {0, 1, 0, {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, 10, 0}};

lib/test/asn1/srsran_asn1_rrc_nr_test.cc

@@ -1221,43 +1221,142 @@ int test_cell_group_config_fdd()
   cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg_present = true;
   cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.set_setup();
 
-  //TODO?
   // nzp-CSI-RS Resource
   cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list_present = true;
-  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list.resize(1);
+  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list.resize(5);
   auto& nzp_csi_res =
-      cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list[0];
-  nzp_csi_res.nzp_csi_rs_res_id = 0;
-  nzp_csi_res.res_map.freq_domain_alloc.set_row2();
-  nzp_csi_res.res_map.freq_domain_alloc.row2().from_number(0b100000000000);
-  nzp_csi_res.res_map.nrof_ports                       = asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
-  nzp_csi_res.res_map.first_ofdm_symbol_in_time_domain = 4;
-  nzp_csi_res.res_map.cdm_type                         = asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
-  nzp_csi_res.res_map.density.set_one();
-  nzp_csi_res.res_map.freq_band.start_rb = 0;
-  nzp_csi_res.res_map.freq_band.nrof_rbs = 52;
-  nzp_csi_res.pwr_ctrl_offset            = 0;
+      cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup();
+  // item 0
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].nzp_csi_rs_res_id = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.freq_domain_alloc.set_row2();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.freq_domain_alloc.row2().from_number(0b100000000000);
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.nrof_ports =
+      asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.first_ofdm_symbol_in_time_domain = 4;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.cdm_type =
+      asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.density.set_one();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.freq_band.start_rb = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.freq_band.nrof_rbs = 52;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].pwr_ctrl_offset            = 0;
   // Skip pwr_ctrl_offset_ss_present
-  nzp_csi_res.scrambling_id                  = 500;
-  nzp_csi_res.periodicity_and_offset_present = true;
-  nzp_csi_res.periodicity_and_offset.set_slots80();
-  nzp_csi_res.periodicity_and_offset.slots80() = 1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].scrambling_id                  = 500;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].periodicity_and_offset_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].periodicity_and_offset.set_slots80();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].periodicity_and_offset.slots80() = 1;
   // optional
-  nzp_csi_res.qcl_info_periodic_csi_rs_present = true;
-  nzp_csi_res.qcl_info_periodic_csi_rs         = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].qcl_info_periodic_csi_rs_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].qcl_info_periodic_csi_rs         = 0;
+  // item 1
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].nzp_csi_rs_res_id = 1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.freq_domain_alloc.set_row1();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.freq_domain_alloc.row1().from_number(0b0001);
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.nrof_ports =
+      asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.first_ofdm_symbol_in_time_domain = 4;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.cdm_type =
+      asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.density.set_three();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.freq_band.start_rb = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.freq_band.nrof_rbs = 52;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].pwr_ctrl_offset            = 0;
+  // Skip pwr_ctrl_offset_ss_present
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].scrambling_id                  = 500;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].periodicity_and_offset_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].periodicity_and_offset.set_slots40();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].periodicity_and_offset.slots40() = 11;
+  // optional
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].qcl_info_periodic_csi_rs_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].qcl_info_periodic_csi_rs         = 0;
+  // item 2
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].nzp_csi_rs_res_id = 2;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.freq_domain_alloc.set_row1();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.freq_domain_alloc.row1().from_number(0b0001);
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.nrof_ports =
+      asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.first_ofdm_symbol_in_time_domain = 8;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.cdm_type =
+      asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.density.set_three();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.freq_band.start_rb = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.freq_band.nrof_rbs = 52;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].pwr_ctrl_offset            = 0;
+  // Skip pwr_ctrl_offset_ss_present
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].scrambling_id                  = 500;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].periodicity_and_offset_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].periodicity_and_offset.set_slots40();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].periodicity_and_offset.slots40() = 11;
+  // optional
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].qcl_info_periodic_csi_rs_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].qcl_info_periodic_csi_rs         = 0;
+  // item 3
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].nzp_csi_rs_res_id = 3;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.freq_domain_alloc.set_row1();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.freq_domain_alloc.row1().from_number(0b0001);
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.nrof_ports =
+      asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.first_ofdm_symbol_in_time_domain = 4;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.cdm_type =
+      asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.density.set_three();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.freq_band.start_rb = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.freq_band.nrof_rbs = 52;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].pwr_ctrl_offset            = 0;
+  // Skip pwr_ctrl_offset_ss_present
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].scrambling_id                  = 500;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].periodicity_and_offset_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].periodicity_and_offset.set_slots40();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].periodicity_and_offset.slots40() = 12;
+  // optional
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].qcl_info_periodic_csi_rs_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].qcl_info_periodic_csi_rs         = 0;
+  // item 4
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].nzp_csi_rs_res_id = 4;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.freq_domain_alloc.set_row1();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.freq_domain_alloc.row1().from_number(0b0001);
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.nrof_ports =
+      asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.first_ofdm_symbol_in_time_domain = 8;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.cdm_type =
+      asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.density.set_three();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.freq_band.start_rb = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.freq_band.nrof_rbs = 52;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].pwr_ctrl_offset            = 0;
+  // Skip pwr_ctrl_offset_ss_present
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].scrambling_id                  = 500;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].periodicity_and_offset_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].periodicity_and_offset.set_slots40();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].periodicity_and_offset.slots40() = 12;
+  // optional
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].qcl_info_periodic_csi_rs_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].qcl_info_periodic_csi_rs         = 0;
 
-  //TODO?
   // nzp-CSI-RS ResourceSet
   cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list_present =
       true;
-  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list.resize(1);
+  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list.resize(2);
   auto& nzp_csi_res_set =
-      cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list[0];
-  nzp_csi_res_set.nzp_csi_res_set_id = 1;
-  nzp_csi_res_set.nzp_csi_rs_res.resize(1);
-  nzp_csi_res_set.nzp_csi_rs_res[0] = 1;
+      cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup();
+  // item 0
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[0].nzp_csi_res_set_id = 0;
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[0].nzp_csi_rs_res.resize(1);
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[0].nzp_csi_rs_res[0] = 0;
+  // item 1
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[1].nzp_csi_res_set_id = 1;
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[1].nzp_csi_rs_res.resize(4);
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[1].nzp_csi_rs_res[0] = 1;
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[1].nzp_csi_rs_res[1] = 2;
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[1].nzp_csi_rs_res[2] = 3;
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[1].nzp_csi_rs_res[3] = 4;
   // Skip TRS info
 
+  // CSI IM config
+  // TODO: add csi im config
+
+  // CSI resource config
+  // TODO: add csi resource config
+
   // CSI report config
   cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().csi_report_cfg_to_add_mod_list_present = true;
   cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().csi_report_cfg_to_add_mod_list.resize(1);
@@ -1387,6 +1486,10 @@ int test_cell_group_config_fdd()
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common_present = true;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.dummy = time_align_timer_opts::ms500;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.freq_info_ul_present = true;
+  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.freq_info_ul.freq_band_list
+      .push_back(5);
+  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.freq_info_ul.absolute_freq_point_a =
+      166364;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.freq_info_ul
       .scs_specific_carrier_list.resize(1);
   auto& ul_carrier = cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.freq_info_ul

srsenb/src/enb_cfg_parser.cc

@@ -908,6 +908,7 @@ static int parse_nr_cell_list(all_args_t* args, rrc_nr_cfg_t* rrc_cfg_nr, rrc_cf
 
     cell_cfg.phy_cell.carrier.pci = cell_cfg.phy_cell.carrier.pci % SRSRAN_NOF_NID_NR;
     HANDLEPARSERCODE(parse_required_field(cell_cfg.dl_arfcn, cellroot, "dl_arfcn"));
+    parse_opt_field(cell_cfg.ul_arfcn, cellroot, "ul_arfcn");
     // frequencies get derived from ARFCN
 
     // TODO: Add further cell-specific parameters
@@ -1370,6 +1371,12 @@ int set_derived_args_nr(all_args_t* args_, rrc_nr_cfg_t* rrc_cfg_, phy_cfg_t* ph
       cfg.phy_cell.ul_freq_hz = band_helper.nr_arfcn_to_freq(cfg.ul_arfcn);
     }
 
+    // band
+    cfg.band = band_helper.get_band_from_dl_arfcn(cfg.dl_arfcn);
+
+    // duplex mode
+    cfg.duplex_mode = band_helper.get_duplex_mode(cfg.band);
+
     phy_cfg_->phy_cell_cfg_nr.push_back(cfg.phy_cell);
   }
 

srsenb/src/phy/nr/worker_pool.cc

@@ -132,6 +132,7 @@ int worker_pool::set_common_cfg(const phy_interface_rrc_nr::common_cfg_t& common
   }
   prach_cfg.freq_offset -= lte_nr_prach_offset;
   prach_cfg.is_nr = true;
+  prach_cfg.tdd_config.configured = (common_cfg.duplex_mode == SRSRAN_DUPLEX_MODE_TDD);
 
   // Set the PRACH configuration
   prach.init(0, cell, prach_cfg, &prach_stack_adaptor, logger, 0, nof_prach_workers);

srsenb/src/stack/rrc/rrc_nr.cc

@@ -14,6 +14,7 @@
 #include "srsenb/hdr/common/common_enb.h"
 #include "srsenb/test/mac/nr/sched_nr_cfg_generators.h"
 #include "srsran/asn1/rrc_nr_utils.h"
+#include "srsran/common/band_helper.h"
 #include "srsran/common/common_nr.h"
 #include "srsran/common/phy_cfg_nr_default.h"
 #include "srsran/common/standard_streams.h"
@@ -540,6 +541,8 @@ int rrc_nr::ue::pack_secondary_cell_group_config_common(asn1::rrc_nr::cell_group
 {
   auto& pscell_cfg = parent->cfg.cell_list.at(UE_PSCELL_CC_IDX);
 
+  srsran::srsran_band_helper band_helper;
+
   // RLC for DRB1 (with fixed LCID)
   cell_group_cfg_pack.rlc_bearer_to_add_mod_list_present = true;
   cell_group_cfg_pack.rlc_bearer_to_add_mod_list.resize(1);
@@ -698,8 +701,8 @@ int rrc_nr::ue::pack_secondary_cell_group_config_common(asn1::rrc_nr::cell_group
   sr_res1.sched_request_res_id           = 1;
   sr_res1.sched_request_id               = 0;
   sr_res1.periodicity_and_offset_present = true;
-  sr_res1.periodicity_and_offset.set_sl40() = 8;
   sr_res1.res_present                    = true;
+  sr_res1.res                            = 2; // PUCCH resource for SR
 
   // DL data
   ul_config.init_ul_bwp.pucch_cfg.setup().dl_data_to_ul_ack_present = true;
@@ -812,37 +815,6 @@ int rrc_nr::ue::pack_secondary_cell_group_config_common(asn1::rrc_nr::cell_group
   cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg_present = true;
   cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.set_setup();
 
-  // nzp-CSI-RS Resource
-  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list_present = true;
-  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list.resize(1);
-  auto& nzp_csi_res =
-      cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list[0];
-  nzp_csi_res.nzp_csi_rs_res_id = 0;
-  nzp_csi_res.res_map.freq_domain_alloc.set_row2();
-  nzp_csi_res.res_map.freq_domain_alloc.row2().from_number(0b100000000000);
-  nzp_csi_res.res_map.nrof_ports                       = asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
-  nzp_csi_res.res_map.first_ofdm_symbol_in_time_domain = 4;
-  nzp_csi_res.res_map.cdm_type                         = asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
-  nzp_csi_res.res_map.density.set_one();
-  nzp_csi_res.res_map.freq_band.start_rb = 0;
-  nzp_csi_res.res_map.freq_band.nrof_rbs = 52;
-  nzp_csi_res.pwr_ctrl_offset            = 0;
-  // Skip pwr_ctrl_offset_ss_present
-  nzp_csi_res.periodicity_and_offset_present = true;
-  nzp_csi_res.periodicity_and_offset.set_slots80();
-  // optional
-  nzp_csi_res.qcl_info_periodic_csi_rs_present = true;
-  nzp_csi_res.qcl_info_periodic_csi_rs         = 0;
-
-  // nzp-CSI-RS ResourceSet
-  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list_present =
-      true;
-  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list.resize(1);
-  auto& nzp_csi_res_set =
-      cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list[0];
-  nzp_csi_res_set.nzp_csi_rs_res.resize(1);
-  // Skip TRS info
-
   // CSI report config
   cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().csi_report_cfg_to_add_mod_list_present = true;
   cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().csi_report_cfg_to_add_mod_list.resize(1);
@@ -878,6 +850,7 @@ int rrc_nr::ue::pack_secondary_cell_group_config_common(asn1::rrc_nr::cell_group
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.t304      = recfg_with_sync_s::t304_opts::ms1000;
 
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common_present           = true;
+  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ss_pbch_block_pwr = 0;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.n_timing_advance_offset =
       asn1::rrc_nr::serving_cell_cfg_common_s::n_timing_advance_offset_opts::n0;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dmrs_type_a_position =
@@ -885,12 +858,15 @@ int rrc_nr::ue::pack_secondary_cell_group_config_common(asn1::rrc_nr::cell_group
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.pci_present = true;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.pci         = pscell_cfg.phy_cell.carrier.pci;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ssb_subcarrier_spacing_present = true;
-  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ssb_subcarrier_spacing =
-      subcarrier_spacing_opts::khz30;
 
   // DL config
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common_present              = true;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.freq_info_dl_present = true;
+  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.freq_info_dl.freq_band_list
+      .push_back(parent->cfg.cell_list[0].band);
+  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.freq_info_dl.absolute_freq_point_a =
+      band_helper.get_abs_freq_point_a_arfcn(parent->cfg.cell_list[0].phy_cell.carrier.nof_prb,
+                                             parent->cfg.cell_list[0].dl_arfcn);
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.freq_info_dl
       .absolute_freq_ssb_present = true;
 
@@ -972,6 +948,12 @@ int rrc_nr::ue::pack_secondary_cell_group_config_common(asn1::rrc_nr::cell_group
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common_present = true;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.dummy = time_align_timer_opts::ms500;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.freq_info_ul_present = true;
+  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.freq_info_ul.freq_band_list
+      .push_back(parent->cfg.cell_list[0].band);
+  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.freq_info_ul.absolute_freq_point_a =
+      band_helper.get_abs_freq_point_a_arfcn(parent->cfg.cell_list[0].phy_cell.carrier.nof_prb,
+                                             parent->cfg.cell_list[0].ul_arfcn);
+  ;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.freq_info_ul
       .scs_specific_carrier_list.resize(1);
   auto& ul_carrier = cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.freq_info_ul
@@ -1056,6 +1038,19 @@ int rrc_nr::ue::pack_secondary_cell_group_config_fdd(asn1::dyn_octstring& packed
   auto& cell_group_cfg_pack = cell_group_cfg;
   pack_secondary_cell_group_config_common(cell_group_cfg);
 
+  uint32_t absolute_freq_ssb;
+
+  if (parent->cfg.cell_list[0].band == 3) { // band n3
+    absolute_freq_ssb = 367930;
+  } else if (parent->cfg.cell_list[0].band == 5) { // band n5
+    absolute_freq_ssb = 176210;
+  } else if (parent->cfg.cell_list[0].band == 7) { // band n7
+    absolute_freq_ssb = 529470;
+  } else {
+    parent->logger.error("Unsupported dl_arfcn.");
+    return SRSRAN_ERROR;
+  }
+
   cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.first_active_dl_bwp_id = 0;
   cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.ul_cfg_present         = true;
 
@@ -1063,28 +1058,146 @@ int rrc_nr::ue::pack_secondary_cell_group_config_fdd(asn1::dyn_octstring& packed
   auto& ul_config = cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.ul_cfg;
   // SR resources
   auto& sr_res1 = ul_config.init_ul_bwp.pucch_cfg.setup().sched_request_res_to_add_mod_list[0];
-  sr_res1.periodicity_and_offset.sl40() = 4;
-  sr_res1.res_present                   = true;
-  sr_res1.res                           = 16; // PUCCH resource for SR
+  sr_res1.periodicity_and_offset.set_sl40() = 8;
+  sr_res1.res                               = 2; // PUCCH resource for SR
 
   // DL data
-  ul_config.init_ul_bwp.pucch_cfg.setup().dl_data_to_ul_ack_present = true;
   ul_config.init_ul_bwp.pucch_cfg.setup().dl_data_to_ul_ack.resize(1);
   ul_config.init_ul_bwp.pucch_cfg.setup().dl_data_to_ul_ack[0] = 4;
 
   // nzp-CSI-RS Resource
-  auto& nzp_csi_res =
-      cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list[0];
-  nzp_csi_res.scrambling_id                  = 500;
-  nzp_csi_res.periodicity_and_offset_present = true;
-  nzp_csi_res.periodicity_and_offset.set_slots80();
-  nzp_csi_res.periodicity_and_offset.slots80() = 1;
+  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list_present = true;
+  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list.resize(5);
+  auto& nzp_csi_res = cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup();
+  // item 0
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].nzp_csi_rs_res_id = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.freq_domain_alloc.set_row2();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.freq_domain_alloc.row2().from_number(0b100000000000);
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.nrof_ports =
+      asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.first_ofdm_symbol_in_time_domain = 4;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.cdm_type =
+      asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.density.set_one();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.freq_band.start_rb = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].res_map.freq_band.nrof_rbs = 52;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].pwr_ctrl_offset            = 0;
+  // Skip pwr_ctrl_offset_ss_present
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].scrambling_id = parent->cfg.cell_list[0].phy_cell.cell_id;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].periodicity_and_offset_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].periodicity_and_offset.set_slots80();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].periodicity_and_offset.slots80() = 1;
+  // optional
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].qcl_info_periodic_csi_rs_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[0].qcl_info_periodic_csi_rs         = 0;
+  // item 1
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].nzp_csi_rs_res_id = 1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.freq_domain_alloc.set_row1();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.freq_domain_alloc.row1().from_number(0b0001);
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.nrof_ports =
+      asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.first_ofdm_symbol_in_time_domain = 4;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.cdm_type =
+      asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.density.set_three();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.freq_band.start_rb = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].res_map.freq_band.nrof_rbs = 52;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].pwr_ctrl_offset            = 0;
+  // Skip pwr_ctrl_offset_ss_present
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].scrambling_id = parent->cfg.cell_list[0].phy_cell.cell_id;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].periodicity_and_offset_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].periodicity_and_offset.set_slots40();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].periodicity_and_offset.slots40() = 11;
+  // optional
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].qcl_info_periodic_csi_rs_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[1].qcl_info_periodic_csi_rs         = 0;
+  // item 2
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].nzp_csi_rs_res_id = 2;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.freq_domain_alloc.set_row1();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.freq_domain_alloc.row1().from_number(0b0001);
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.nrof_ports =
+      asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.first_ofdm_symbol_in_time_domain = 8;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.cdm_type =
+      asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.density.set_three();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.freq_band.start_rb = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].res_map.freq_band.nrof_rbs = 52;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].pwr_ctrl_offset            = 0;
+  // Skip pwr_ctrl_offset_ss_present
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].scrambling_id = parent->cfg.cell_list[0].phy_cell.cell_id;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].periodicity_and_offset_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].periodicity_and_offset.set_slots40();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].periodicity_and_offset.slots40() = 11;
+  // optional
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].qcl_info_periodic_csi_rs_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[2].qcl_info_periodic_csi_rs         = 0;
+  // item 3
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].nzp_csi_rs_res_id = 3;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.freq_domain_alloc.set_row1();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.freq_domain_alloc.row1().from_number(0b0001);
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.nrof_ports =
+      asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.first_ofdm_symbol_in_time_domain = 4;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.cdm_type =
+      asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.density.set_three();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.freq_band.start_rb = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].res_map.freq_band.nrof_rbs = 52;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].pwr_ctrl_offset            = 0;
+  // Skip pwr_ctrl_offset_ss_present
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].scrambling_id = parent->cfg.cell_list[0].phy_cell.cell_id;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].periodicity_and_offset_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].periodicity_and_offset.set_slots40();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].periodicity_and_offset.slots40() = 12;
+  // optional
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].qcl_info_periodic_csi_rs_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[3].qcl_info_periodic_csi_rs         = 0;
+  // item 4
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].nzp_csi_rs_res_id = 4;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.freq_domain_alloc.set_row1();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.freq_domain_alloc.row1().from_number(0b0001);
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.nrof_ports =
+      asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.first_ofdm_symbol_in_time_domain = 8;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.cdm_type =
+      asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.density.set_three();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.freq_band.start_rb = 0;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].res_map.freq_band.nrof_rbs = 52;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].pwr_ctrl_offset            = 0;
+  // Skip pwr_ctrl_offset_ss_present
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].scrambling_id = parent->cfg.cell_list[0].phy_cell.cell_id;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].periodicity_and_offset_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].periodicity_and_offset.set_slots40();
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].periodicity_and_offset.slots40() = 12;
+  // optional
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].qcl_info_periodic_csi_rs_present = true;
+  nzp_csi_res.nzp_csi_rs_res_to_add_mod_list[4].qcl_info_periodic_csi_rs         = 0;
 
   // nzp-CSI-RS ResourceSet
-  auto& nzp_csi_res_set =
-      cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list[0];
-  nzp_csi_res_set.nzp_csi_res_set_id = 1;
-  nzp_csi_res_set.nzp_csi_rs_res[0]  = 1;
+  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list_present =
+      true;
+  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list.resize(2);
+  auto& nzp_csi_res_set = cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup();
+  // item 0
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[0].nzp_csi_res_set_id = 0;
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[0].nzp_csi_rs_res.resize(1);
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[0].nzp_csi_rs_res[0] = 0;
+  // item 1
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[1].nzp_csi_res_set_id = 1;
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[1].nzp_csi_rs_res.resize(4);
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[1].nzp_csi_rs_res[0] = 1;
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[1].nzp_csi_rs_res[1] = 2;
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[1].nzp_csi_rs_res[2] = 3;
+  nzp_csi_res_set.nzp_csi_rs_res_set_to_add_mod_list[1].nzp_csi_rs_res[3] = 4;
+  // Skip TRS info
+
+  // CSI IM config
+  // TODO: add csi im config
+
+  // CSI resource config
+  // TODO: add csi resource config
 
   // CSI report config
   auto& csi_report =
@@ -1092,18 +1205,13 @@ int rrc_nr::ue::pack_secondary_cell_group_config_fdd(asn1::dyn_octstring& packed
   csi_report.report_cfg_type.periodic().report_slot_cfg.slots80() = 5;
 
   // Reconfig with Sync
-  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common_present           = true;
-  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ss_pbch_block_pwr = -36;
+  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ssb_subcarrier_spacing =
+      subcarrier_spacing_opts::khz15;
 
   // DL config
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common_present = true;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.freq_info_dl.absolute_freq_ssb =
-      176210; // TODO: calculate from actual DL ARFCN
-
-  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.freq_info_dl.freq_band_list
-      .push_back(5);
-  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.freq_info_dl.absolute_freq_point_a =
-      175364; // TODO: calculate from actual DL ARFCN
+      absolute_freq_ssb; // TODO: calculate from actual DL ARFCN
 
   // RACH config
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ul_cfg_common.init_ul_bwp.rach_cfg_common_present =
@@ -1145,12 +1253,10 @@ int rrc_nr::ue::pack_secondary_cell_group_config_tdd(asn1::dyn_octstring& packed
   // SR resources
   auto& sr_res1 = ul_config.init_ul_bwp.pucch_cfg.setup().sched_request_res_to_add_mod_list[0];
   // SR resources
-  sr_res1.periodicity_and_offset.sl40() = 8;
-  sr_res1.res_present                   = true;
+  sr_res1.periodicity_and_offset.set_sl40() = 8;
   sr_res1.res                               = 2; // PUCCH resource for SR
 
   // DL data
-  ul_config.init_ul_bwp.pucch_cfg.setup().dl_data_to_ul_ack_present = true;
   ul_config.init_ul_bwp.pucch_cfg.setup().dl_data_to_ul_ack.resize(6);
   ul_config.init_ul_bwp.pucch_cfg.setup().dl_data_to_ul_ack[0] = 6;
   ul_config.init_ul_bwp.pucch_cfg.setup().dl_data_to_ul_ack[1] = 5;
@@ -1160,17 +1266,36 @@ int rrc_nr::ue::pack_secondary_cell_group_config_tdd(asn1::dyn_octstring& packed
   ul_config.init_ul_bwp.pucch_cfg.setup().dl_data_to_ul_ack[5] = 4;
 
   // nzp-CSI-RS Resource
+  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list_present = true;
+  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list.resize(1);
   auto& nzp_csi_res =
       cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_to_add_mod_list[0];
+  nzp_csi_res.nzp_csi_rs_res_id = 0;
+  nzp_csi_res.res_map.freq_domain_alloc.set_row2();
+  nzp_csi_res.res_map.freq_domain_alloc.row2().from_number(0b100000000000);
+  nzp_csi_res.res_map.nrof_ports                       = asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
+  nzp_csi_res.res_map.first_ofdm_symbol_in_time_domain = 4;
+  nzp_csi_res.res_map.cdm_type                         = asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
+  nzp_csi_res.res_map.density.set_one();
+  nzp_csi_res.res_map.freq_band.start_rb = 0;
+  nzp_csi_res.res_map.freq_band.nrof_rbs = 52;
+  nzp_csi_res.pwr_ctrl_offset            = 0;
+  // Skip pwr_ctrl_offset_ss_present
   nzp_csi_res.scrambling_id                        = 0;
   nzp_csi_res.periodicity_and_offset_present       = true;
-  nzp_csi_res.periodicity_and_offset.set_slots80();
-  nzp_csi_res.periodicity_and_offset.slots80() = 0;
+  nzp_csi_res.periodicity_and_offset.set_slots80() = 0;
+  // optional
+  nzp_csi_res.qcl_info_periodic_csi_rs_present = true;
+  nzp_csi_res.qcl_info_periodic_csi_rs         = 0;
 
   // nzp-CSI-RS ResourceSet
+  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list_present =
+      true;
+  cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list.resize(1);
   auto& nzp_csi_res_set =
       cell_group_cfg_pack.sp_cell_cfg.sp_cell_cfg_ded.csi_meas_cfg.setup().nzp_csi_rs_res_set_to_add_mod_list[0];
   nzp_csi_res_set.nzp_csi_res_set_id = 0;
+  nzp_csi_res_set.nzp_csi_rs_res.resize(1);
   nzp_csi_res_set.nzp_csi_rs_res[0] = 0;
   // Skip TRS info
 
@@ -1181,20 +1306,14 @@ int rrc_nr::ue::pack_secondary_cell_group_config_tdd(asn1::dyn_octstring& packed
 
   // Reconfig with Sync
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.smtc.release();
-
-  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common_present           = true;
-  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ss_pbch_block_pwr = 0;
+  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.ssb_subcarrier_spacing =
+      subcarrier_spacing_opts::khz30;
 
   // DL config
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common_present = true;
   cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.freq_info_dl.absolute_freq_ssb =
       634176; // TODO: calculate from actual DL ARFCN
 
-  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.freq_info_dl.freq_band_list
-      .push_back(78);
-  cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.freq_info_dl.absolute_freq_point_a =
-      633928; // TODO: calculate from actual DL ARFCN
-
   auto& pdcch_cfg_common =
       cell_group_cfg_pack.sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.init_dl_bwp.pdcch_cfg_common;
   pdcch_cfg_common.set_setup();
@@ -1245,10 +1364,18 @@ int rrc_nr::ue::pack_rrc_reconfiguraiton(asn1::dyn_octstring& packed_rrc_reconfi
 
   // add secondary cell group config
   recfg_ies.secondary_cell_group_present = true;
+
+  if (parent->cfg.cell_list[0].duplex_mode == SRSRAN_DUPLEX_MODE_FDD) {
+    if (pack_secondary_cell_group_config_fdd(recfg_ies.secondary_cell_group) == SRSRAN_ERROR) {
+      parent->logger.error("Failed to pack TDD RRC Reconfiguration");
+      return SRSRAN_ERROR;
+    }
+  } else {
     if (pack_secondary_cell_group_config_tdd(recfg_ies.secondary_cell_group) == SRSRAN_ERROR) {
       parent->logger.error("Failed to pack TDD RRC Reconfiguration");
       return SRSRAN_ERROR;
     }
+  }
 
   // now pack ..
   packed_rrc_reconfig.resize(512);

srsue/hdr/stack/rrc/rrc.h

@@ -45,6 +45,7 @@ typedef struct {
   uint32_t                                release;
   uint32_t                                feature_group;
   std::array<uint8_t, SRSRAN_RRC_N_BANDS> supported_bands;
+  std::vector<uint32_t>                   supported_bands_nr;
   uint32_t                                nof_supported_bands;
   bool                                    support_ca;
   int                                     mbms_service_id;

srsue/hdr/stack/rrc/rrc_nr.h

@@ -13,6 +13,7 @@
 #ifndef SRSUE_RRC_NR_H
 #define SRSUE_RRC_NR_H
 
+#include "srsran/adt/circular_map.h"
 #include "srsran/asn1/rrc_nr.h"
 #include "srsran/asn1/rrc_nr_utils.h"
 #include "srsran/common/block_queue.h"
@@ -185,8 +186,7 @@ private:
   std::map<uint32_t, uint32_t> drb_eps_bearer_id; // Map of drb id to eps_bearer_id
 
   // temporary maps for building the pucch nr resources
-  std::map<uint32_t, srsran_pucch_nr_resource_t>   res_list;
-  std::map<uint32_t, bool>                         res_list_present;
+  srsran::static_circular_map<uint32_t, srsran_pucch_nr_resource_t, 128> pucch_res_list;
   std::map<uint32_t, srsran_csi_rs_zp_resource_t>                        csi_rs_zp_res;
   std::map<uint32_t, srsran_csi_rs_nzp_resource_t>                       csi_rs_nzp_res;
 

srsue/src/phy/nr/sf_worker.cc

@@ -90,7 +90,7 @@ void sf_worker::work_imp()
 
     // Notify MAC about PRACH transmission
     phy_state.stack->prach_sent(TTI_TX(tti_rx),
-                                srsran_prach_nr_start_symbol_fr1_unpaired(phy_state.cfg.prach.config_idx),
+                                srsran_prach_nr_start_symbol(phy_state.cfg.prach.config_idx, phy_state.cfg.duplex.mode),
                                 SRSRAN_SLOT_NR_MOD(phy_state.cfg.carrier.scs, TTI_TX(tti_rx)),
                                 0,
                                 0);

srsue/src/phy/nr/worker_pool.cc

@@ -172,6 +172,7 @@ bool worker_pool::set_config(const srsran::phy_cfg_nr_t& cfg)
     return false;
   }
   prach_cfg.freq_offset -= lte_nr_prach_offset;
+  prach_cfg.tdd_config.configured = (cfg.duplex.mode == SRSRAN_DUPLEX_MODE_TDD);
 
   // Set the PRACH configuration
   if (not prach_buffer->set_cell(cell, prach_cfg)) {

srsue/src/phy/phy.cc

@@ -664,9 +664,9 @@ bool phy::set_config(const srsran::phy_cfg_nr_t& cfg)
 
   // tune radio
   for (uint32_t i = 0; i < common.args->nof_nr_carriers; i++) {
-    logger_phy.info("Tuning Rx channel %d to %.2f GHz", i + common.args->nof_lte_carriers, dl_freq_hz / 1e6);
+    logger_phy.info("Tuning Rx channel %d to %.2f MHz", i + common.args->nof_lte_carriers, dl_freq_hz / 1e6);
     radio->set_rx_freq(i + common.args->nof_lte_carriers, dl_freq_hz);
-    logger_phy.info("Tuning Tx channel %d to %.2f GHz", i + common.args->nof_lte_carriers, ul_freq_hz / 1e6);
+    logger_phy.info("Tuning Tx channel %d to %.2f MHz", i + common.args->nof_lte_carriers, ul_freq_hz / 1e6);
     radio->set_tx_freq(i + common.args->nof_lte_carriers, ul_freq_hz);
   }
 

srsue/src/stack/rrc/rrc.cc

@@ -2110,10 +2110,12 @@ void rrc::handle_ue_capability_enquiry(const ue_cap_enquiry_s& enquiry)
         irat_params_nr_r15.en_dc_r15_present                     = true;
         irat_params_nr_r15.supported_band_list_en_dc_r15_present = true;
 
-        supported_band_nr_r15_s supported_band_nr_r15;
-        supported_band_nr_r15.band_nr_r15 = 78;
+        uint32_t nof_supported_nr_bands = args.supported_bands_nr.size();
+        irat_params_nr_r15.supported_band_list_en_dc_r15.resize(nof_supported_nr_bands);
+        for (uint32_t k = 0; k < nof_supported_nr_bands; k++) {
+          irat_params_nr_r15.supported_band_list_en_dc_r15[k].band_nr_r15 = args.supported_bands_nr[k];
+        }
 
-        irat_params_nr_r15.supported_band_list_en_dc_r15.push_back(supported_band_nr_r15);
         ue_eutra_cap_v1450_ies->non_crit_ext.non_crit_ext.irat_params_nr_r15_present = true;
         ue_eutra_cap_v1450_ies->non_crit_ext.non_crit_ext.irat_params_nr_r15         = irat_params_nr_r15;
         ue_eutra_cap_v1450_ies->non_crit_ext.non_crit_ext.non_crit_ext_present       = true;

srsue/src/stack/rrc/rrc_nr.cc

@@ -703,8 +703,8 @@ bool rrc_nr::apply_res_csi_report_cfg(const asn1::rrc_nr::csi_report_cfg_s& csi_
       uint32_t res_id = csi_report_cfg.report_cfg_type.periodic()
                             .pucch_csi_res_list[0]
                             .pucch_res; // TODO: support and check more items
-      if (res_list_present[res_id] == true) {
-        phy_cfg.csi.reports[report_cfg_id].periodic.resource = res_list[res_id];
+      if (pucch_res_list.contains(res_id)) {
+        phy_cfg.csi.reports[report_cfg_id].periodic.resource = pucch_res_list[res_id];
       } else {
         logger.error("Resources set not present for assigning pucch sets (res_id %d)", res_id);
         return false;
@@ -753,7 +753,7 @@ bool rrc_nr::apply_csi_meas_cfg(const asn1::rrc_nr::csi_meas_cfg_s& csi_meas_cfg
         uint8_t res = csi_meas_cfg.nzp_csi_rs_res_set_to_add_mod_list[i].nzp_csi_rs_res[j];
         // use temporally stored values to assign
         if (csi_rs_nzp_res.find(res) == csi_rs_nzp_res.end()) {
-          logger.warning("Can not find p_zp_csi_rs_res in temporally stored csi_rs_zp_res");
+          logger.warning("Can not find nzp_csi_rs_res in temporally stored csi_rs_nzp_res");
           return false;
         }
         phy_cfg.pdsch.nzp_csi_rs_sets[set_id].data[j] = csi_rs_nzp_res[res];
@@ -1002,9 +1002,8 @@ bool rrc_nr::apply_sp_cell_ded_ul_pucch(const asn1::rrc_nr::pucch_cfg_s& pucch_c
   if (pucch_cfg.res_to_add_mod_list_present) {
     for (uint32_t i = 0; i < pucch_cfg.res_to_add_mod_list.size(); i++) {
       uint32_t res_id = pucch_cfg.res_to_add_mod_list[i].pucch_res_id;
-      if (make_phy_res_config(pucch_cfg.res_to_add_mod_list[i], format_2_max_code_rate, &res_list[res_id]) == true) {
-        res_list_present[res_id] = true;
-      } else {
+      pucch_res_list.insert(res_id, {});
+      if (!make_phy_res_config(pucch_cfg.res_to_add_mod_list[i], format_2_max_code_rate, &pucch_res_list[res_id])) {
         logger.warning("Warning while building pucch_nr_resource structure");
         return false;
       }
@@ -1022,8 +1021,8 @@ bool rrc_nr::apply_sp_cell_ded_ul_pucch(const asn1::rrc_nr::pucch_cfg_s& pucch_c
       phy_cfg.pucch.sets[set_id].nof_resources = pucch_cfg.res_set_to_add_mod_list[i].res_list.size();
       for (uint32_t j = 0; j < pucch_cfg.res_set_to_add_mod_list[i].res_list.size(); j++) {
         uint32_t res_id = pucch_cfg.res_set_to_add_mod_list[i].res_list[j];
-        if (res_list_present[res_id] == true) {
-          phy_cfg.pucch.sets[set_id].resources[j] = res_list[res_id];
+        if (pucch_res_list.contains(res_id)) {
+          phy_cfg.pucch.sets[set_id].resources[j] = pucch_res_list[res_id];
         } else {
           logger.error(
               "Resources set not present for assign pucch sets (res_id %d, setid %d, j %d)", res_id, set_id, j);
@@ -1034,24 +1033,26 @@ bool rrc_nr::apply_sp_cell_ded_ul_pucch(const asn1::rrc_nr::pucch_cfg_s& pucch_c
 
   if (pucch_cfg.sched_request_res_to_add_mod_list_present) {
     for (uint32_t i = 0; i < pucch_cfg.sched_request_res_to_add_mod_list.size(); i++) {
-      uint32_t                      res_id = pucch_cfg.sched_request_res_to_add_mod_list[i].sched_request_res_id;
+      uint32_t                      sr_res_id = pucch_cfg.sched_request_res_to_add_mod_list[i].sched_request_res_id;
       srsran_pucch_nr_sr_resource_t srsran_pucch_nr_sr_resource;
       if (make_phy_sr_resource(pucch_cfg.sched_request_res_to_add_mod_list[i], &srsran_pucch_nr_sr_resource) ==
           true) { // TODO: fix that if indexing is solved
-        phy_cfg.pucch.sr_resources[res_id] = srsran_pucch_nr_sr_resource;
+        phy_cfg.pucch.sr_resources[sr_res_id] = srsran_pucch_nr_sr_resource;
 
         // Set PUCCH resource
         if (pucch_cfg.sched_request_res_to_add_mod_list[i].res_present) {
           uint32_t pucch_res_id = pucch_cfg.sched_request_res_to_add_mod_list[i].res;
-          if (res_list_present[res_id]) {
-            phy_cfg.pucch.sr_resources[res_id].resource = res_list[pucch_res_id];
+          if (pucch_res_list.contains(pucch_res_id)) {
+            phy_cfg.pucch.sr_resources[sr_res_id].resource = pucch_res_list[pucch_res_id];
           } else {
-            logger.warning("Warning SR's PUCCH resource is invalid (%d)", pucch_res_id);
-            phy_cfg.pucch.sr_resources[res_id].configured = false;
+            logger.warning("Warning SR (%d) PUCCH resource is invalid (%d)", sr_res_id, pucch_res_id);
+            phy_cfg.pucch.sr_resources[sr_res_id].configured = false;
+            return false;
           }
         } else {
           logger.warning("Warning SR resource is present but no PUCCH resource is assigned to it");
-          phy_cfg.pucch.sr_resources[res_id].configured = false;
+          phy_cfg.pucch.sr_resources[sr_res_id].configured = false;
+          return false;
         }
 
       } else {
@@ -1193,6 +1194,7 @@ bool rrc_nr::apply_sp_cell_cfg(const sp_cell_cfg_s& sp_cell_cfg)
       }
 
       if (recfg_with_sync.sp_cell_cfg_common.tdd_ul_dl_cfg_common_present) {
+        logger.info("TDD UL DL config present, using TDD");
         srsran_duplex_config_nr_t duplex;
         if (make_phy_tdd_cfg(recfg_with_sync.sp_cell_cfg_common.tdd_ul_dl_cfg_common, &duplex) == true) {
           phy_cfg.duplex = duplex;
@@ -1201,8 +1203,7 @@ bool rrc_nr::apply_sp_cell_cfg(const sp_cell_cfg_s& sp_cell_cfg)
           return false;
         }
       } else {
-        logger.warning("TDD UL DL config not present");
-        return false;
+        logger.info("TDD UL DL config not present, using FDD");
       }
     }
   } else {

srsue/src/ue.cc

@@ -219,6 +219,7 @@ int ue::parse_args(const all_args_t& args_)
     if (not args.stack.rrc_nr.supported_bands_nr_str.empty()) {
       // Populates supported bands
       srsran::string_parse_list(args.stack.rrc_nr.supported_bands_nr_str, ',', args.stack.rrc_nr.supported_bands_nr);
+      args.stack.rrc.supported_bands_nr = args.stack.rrc_nr.supported_bands_nr;
     } else {
       logger.error("Error: rat.nr.bands list is empty");
       srsran::console("Error: rat.nr.bands list is empty\n");

test/phy/CMakeLists.txt

@@ -94,8 +94,19 @@ if (RF_FOUND AND ENABLE_SRSUE AND ENABLE_SRSENB)
                 )
 
         # Test PRACH transmission and detection
-        add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_prach nr_phy_test
-                --reference=carrier=${NR_PHY_TEST_BW}
+        add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_prach_fdd nr_phy_test
+                --reference=carrier=${NR_PHY_TEST_BW},duplex=FDD
+                --duration=1000 # 1000 slots
+                --gnb.stack.pdsch.slots=none # No PDSCH
+                --gnb.stack.pusch.slots=none # No PUSCH
+                --gnb.phy.nof_threads=${NR_PHY_TEST_GNB_NOF_THREADS}
+                --ue.stack.prach.period=30 # Transmit PRACH every 30 radio frames
+                --ue.stack.prach.preamble=10 # Use preamble 10
+                --ue.phy.nof_threads=${NR_PHY_TEST_UE_NOF_THREADS}
+                )
+
+        add_nr_test(nr_phy_test_${NR_PHY_TEST_BW}_prach_tdd nr_phy_test
+                --reference=carrier=${NR_PHY_TEST_BW},duplex=6D+4U
                 --duration=1000 # 1000 slots
                 --gnb.stack.pdsch.slots=none # No PDSCH
                 --gnb.stack.pusch.slots=none # No PUSCH

test/phy/test_bench.h

@@ -82,6 +82,7 @@ public:
     common_cfg.carrier                                    = args.phy_cfg.carrier;
     common_cfg.pdcch                                      = args.phy_cfg.pdcch;
     common_cfg.prach                                      = args.phy_cfg.prach;
+    common_cfg.duplex_mode                                = args.phy_cfg.duplex.mode;
 
     if (gnb_phy.set_common_cfg(common_cfg) < SRSRAN_SUCCESS) {
       return;