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Make NR DCI test more exhaustive and fix issues

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master
Xavier Arteaga 4 years ago committed by Xavier Arteaga
parent ab6a5ef17a
commit 873f375ecc
4 changed files with 462 additions and 145 deletions
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75
lib/include/srsran/phy/phch/dci_nr.h
Unescape Escape View File

@ -45,7 +45,7 @@ typedef struct SRSRAN_API {
/// Common Formats 0_1 and 1_1
uint32_t carrier_indicator_size; ///< Defined in TS 38.213 clause 10.1
srsran_harq_ack_codebook_t harq_ack_codebok; ///< PDSCH HARQ-ACK codebook mode
uint32_t nof_rb_groups; ///< Defined in TS 38.214 clause 6.1.2.2.1
uint32_t nof_rb_groups; ///< For allocation type 0, defined in TS 38.214 clause 6.1.2.2.1
/// Format 0_1 specific configuration (for PUSCH only)
uint32_t nof_ul_bwp; ///< Number of UL BWPs excluding the initial UL BWP, mentioned in the TS as N_BWP_RRC
@ -56,7 +56,7 @@ typedef struct SRSRAN_API {
uint32_t report_trigger_size; ///< determined by reportTriggerSize
bool enable_transform_precoding; ///< Set to true if PUSCH transform precoding is enabled
bool dynamic_dual_harq_ack_codebook; ///< Set to true if HARQ-ACK codebook is set to dynamic with 2 sub-codebooks
bool pusch_tx_config_codebook; ///< Set to true if PUSCH txConfig is set to codebook
bool pusch_tx_config_non_codebook; ///< Set to true if PUSCH txConfig is set to non-codebook
bool pusch_dmrs_type2; ///< Set to true if PUSCH DMRS are type 2
bool pusch_dmrs_double; ///< Set to true if PUSCH DMRS are 2 symbol long
bool pusch_ptrs; ///< Set to true if PT-RS are enabled for PUSCH transmission
@ -64,22 +64,22 @@ typedef struct SRSRAN_API {
srsran_resource_alloc_t pusch_alloc_type; ///< PUSCH resource allocation type
/// Format 1_1 specific configuration (for PDSCH only)
uint32_t nof_dl_bwp; ///< Number of DL BWPs excluding the initial UL BWP, mentioned in the TS as N_BWP_RRC
srsran_resource_alloc_t pdsch_alloc_type; ///< PDSCH resource allocation type, set to 0 for default
uint32_t nof_dl_time_res; ///< Number of dedicated PDSCH time domain resource assigment
uint32_t nof_aperiodic_zp; ///< Number of aperiodic ZP CSI-RS resource sets configured
bool pdsch_inter_prb_to_prb; ///< Set to true if interleaved VRB to PRB mapping is enabled
bool pdsch_rm_pattern1; ///< Set to true if rateMatchPatternGroup1 is configured
bool pdsch_rm_pattern2; ///< Set to true if rateMatchPatternGroup2 is configured
bool pdsch_2cw; ///< Set to true if maxNrofCodeWordsScheduledByDCI is set to 2 in any BWP
uint32_t pdsch_nof_cbg; ///< determined by maxCodeBlockGroupsPerTransportBlock for PDSCH
bool multiple_scell; ///< Set to true if configured with multiple serving cell
bool nof_dl_to_ul_ack; ///< Number of entries in the dl-DataToUL-ACK
bool pdsch_dmrs_type2; ///< Set to true if PDSCH DMRS are type 2
bool pdsch_dmrs_double; ///< Set to true if PDSCH DMRS are 2 symbol long
bool pdsch_tci; ///< Set to true if tci-PresentInDCI is enabled
bool pdsch_cbg_flush; ///< Set to true if codeBlockGroupFlushIndicator is true
bool pdsch_dynamic_bundling; ///< Set to true if prb-BundlingType is set to dynamicBundling
uint32_t nof_dl_bwp; ///< Number of DL BWPs excluding the initial UL BWP, mentioned in the TS as N_BWP_RRC
uint32_t nof_dl_time_res; ///< Number of dedicated PDSCH time domain resource assigment
uint32_t nof_aperiodic_zp; ///< Number of aperiodic ZP CSI-RS resource sets configured
uint32_t pdsch_nof_cbg; ///< determined by maxCodeBlockGroupsPerTransportBlock for PDSCH
uint32_t nof_dl_to_ul_ack; ///< Number of entries in the dl-DataToUL-ACK
bool pdsch_inter_prb_to_prb; ///< Set to true if interleaved VRB to PRB mapping is enabled
bool pdsch_rm_pattern1; ///< Set to true if rateMatchPatternGroup1 is configured
bool pdsch_rm_pattern2; ///< Set to true if rateMatchPatternGroup2 is configured
bool pdsch_2cw; ///< Set to true if maxNrofCodeWordsScheduledByDCI is set to 2 in any BWP
bool multiple_scell; ///< Set to true if configured with multiple serving cell
bool pdsch_dmrs_type2; ///< Set to true if PDSCH DMRS are type 2
bool pdsch_dmrs_double; ///< Set to true if PDSCH DMRS are 2 symbol long
bool pdsch_tci; ///< Set to true if tci-PresentInDCI is enabled
bool pdsch_cbg_flush; ///< Set to true if codeBlockGroupFlushIndicator is true
bool pdsch_dynamic_bundling; ///< Set to true if prb-BundlingType is set to dynamicBundling
srsran_resource_alloc_t pdsch_alloc_type; ///< PDSCH resource allocation type, set to 0 for default
} srsran_dci_cfg_nr_t;
@ -112,20 +112,12 @@ typedef struct SRSRAN_API {
* @brief Describes the NR DCI search context
*/
typedef struct SRSRAN_API {
srsran_dci_location_t location; ///< DCI location
srsran_search_space_type_t ss_type; ///< Search space type
uint32_t coreset_id; ///< CORESET identifier
srsran_rnti_type_t rnti_type; ///< RNTI type
srsran_dci_format_nr_t format; ///< DCI format
uint16_t rnti; ///< UE temporal RNTI
uint32_t coreset0_bw; ///< CORESET0 DL bandwidth, set to 0 if not present
uint32_t bwp_dl_initial_bw; ///< Initial DL/UL BWP bandwidth
uint32_t bwp_dl_active_bw; ///< Active DL/UL BWP bandwidth in PRB
uint32_t bwp_ul_initial_bw; ///< Initial UL BWP bandwidth
uint32_t bwp_ul_active_bw; ///< Active UL BWP bandwidth in PRB
bool monitor_common_0_0; ///< Set to true if Format 0_0 is monitored in common SS
bool enable_sul; ///< Set to true if supplementary uplink is configured
bool enable_hopping; ///< Set to true if frequency hopping is enabled
srsran_dci_location_t location; ///< DCI location
srsran_search_space_type_t ss_type; ///< Search space type
uint32_t coreset_id; ///< CORESET identifier
srsran_rnti_type_t rnti_type; ///< RNTI type
srsran_dci_format_nr_t format; ///< DCI format
uint16_t rnti; ///< UE temporal RNTI
} srsran_dci_ctx_t;
/**
@ -204,11 +196,9 @@ typedef struct SRSRAN_API {
uint32_t reserved; ///< Reserved bits
// C-RNTI or CS-RNTI or MCS-C-RNTI
uint32_t ndi; ///< New data indicator
uint32_t pid; ///< HARQ process number
uint32_t tpc; ///< TPC command for scheduled PUCCH
uint32_t pucch_resource; ///< PUCCH resource indicator
uint32_t harq_feedback; ///< PDSCH-to-HARQ_feedback timing indicator
uint32_t ndi; ///< New data indicator
uint32_t pid; ///< HARQ process number
uint32_t tpc; ///< TPC command for scheduled PUCCH
// Frequency hopping
uint32_t frequency_offset; ///< frequency offset
@ -299,7 +289,16 @@ SRSRAN_API int srsran_dci_nr_ul_pack(const srsran_dci_nr_t* q, const srsran_dci_
SRSRAN_API int srsran_dci_nr_ul_unpack(const srsran_dci_nr_t* q, srsran_dci_msg_nr_t* msg, srsran_dci_ul_nr_t* dci);
/**
* @brief Stringifies an DL NR DCI structure
* @brief Stringifies an NR DCI conxtext
* @param ctx Provides NR DCI context
* @param[out] str Destination string
* @param str_len Destination string length
* @return The number of written characters
*/
SRSRAN_API int srsran_dci_ctx_to_str(const srsran_dci_ctx_t* ctx, char* str, uint32_t str_len);
/**
* @brief Stringifies a DL NR DCI structure
* @param q NR DCI object with precomputed DCI parameters
* @param dci DL NR SCI structure to stringify
* @param[out] str Destination string

194
lib/src/phy/phch/dci_nr.c
Unescape Escape View File

@ -64,7 +64,7 @@ static uint32_t dci_nr_time_res_size(uint32_t nof_time_res)
{
if (nof_time_res == 0) {
// 4 bits are necessary for PUSCH default time resource assigment (TS 38.214 Table 6.1.2.1.1-2)
return 4;
nof_time_res = SRSRAN_MAX_NOF_TIME_RA;
}
return (uint32_t)CEIL_LOG2(nof_time_res);
}
@ -84,6 +84,19 @@ static uint32_t dci_nr_ptrs_size(const srsran_dci_cfg_nr_t* cfg)
return 2;
}
static uint32_t dci_nr_srs_id_size(const srsran_dci_cfg_nr_t* cfg)
{
uint32_t N_srs = SRSRAN_MIN(1, cfg->nof_srs);
if (cfg->pusch_tx_config_non_codebook) {
uint32_t N = 0;
for (uint32_t k = 1; k < SRSRAN_MIN(cfg->nof_ul_layers, cfg->nof_srs); k++) {
N += cfg->nof_srs / k;
}
return (uint32_t)CEIL_LOG2(N);
}
return (uint32_t)CEIL_LOG2(N_srs);
}
// Determines DCI format 0_0 according to TS 38.212 clause 7.3.1.1.1
static uint32_t dci_nr_format_0_0_sizeof(uint32_t N_UL_BWP_RB, const srsran_dci_cfg_nr_t* cfg)
{
@ -281,10 +294,6 @@ static int dci_nr_format_0_0_to_str(const srsran_dci_ul_nr_t* dci, char* str, ui
{
uint32_t len = 0;
// Print format
len = srsran_print_check(
str, str_len, len, "rnti=%04x L=%d cce=%d dci=0_0 ", dci->ctx.rnti, dci->ctx.location.L, dci->ctx.location.ncce);
// Frequency domain resource assignment
len = srsran_print_check(str, str_len, len, "f_alloc=0x%x ", dci->freq_domain_assigment);
@ -304,7 +313,7 @@ static int dci_nr_format_0_0_to_str(const srsran_dci_ul_nr_t* dci, char* str, ui
len = srsran_print_check(str, str_len, len, "rv=%d ", dci->rv);
// HARQ process number – 4 bits
len = srsran_print_check(str, str_len, len, "harq_id=%d ", dci->harq_feedback);
len = srsran_print_check(str, str_len, len, "harq_id=%d ", dci->pid);
// TPC command for scheduled PUSCH – 2 bits
len = srsran_print_check(str, str_len, len, "tpc=%d ", dci->tpc);
@ -360,7 +369,7 @@ static uint32_t dci_nr_format_0_1_sizeof(const srsran_dci_cfg_nr_t* cfg, srsran_
count += 4;
// 1st DAI - 1 or 2 bits
if (cfg->pusch_tx_config_codebook == srsran_pdsch_harq_ack_codebook_semi_static) {
if (cfg->harq_ack_codebok == srsran_pdsch_harq_ack_codebook_semi_static) {
count += 1;
} else {
count += 2;
@ -369,31 +378,19 @@ static uint32_t dci_nr_format_0_1_sizeof(const srsran_dci_cfg_nr_t* cfg, srsran_
// 2st DAI - 0 or 2 bits
if (cfg->dynamic_dual_harq_ack_codebook) {
count += 2;
} else {
count += 0;
}
// TPC command for scheduled PUSCH – 2 bits
count += 2;
// SRS resource indicator
uint32_t N_srs = SRSRAN_MIN(1, cfg->nof_srs);
if (cfg->pusch_tx_config_codebook) {
uint32_t N = 0;
for (uint32_t k = 1; k < SRSRAN_MIN(cfg->nof_ul_layers, cfg->nof_srs); k++) {
N += cfg->nof_srs / k;
}
count += (uint32_t)CEIL_LOG2(N);
} else {
count += (uint32_t)CEIL_LOG2(N_srs);
}
count += dci_nr_srs_id_size(cfg);
// Precoding information and number of layers
if (cfg->pusch_tx_config_codebook) {
if (!cfg->pusch_tx_config_non_codebook && cfg->nof_ul_layers > 1) {
ERROR("Not implemented");
return 0;
}
count += 0;
// Antenna ports
if (!cfg->enable_transform_precoding && !cfg->pusch_dmrs_double) {
@ -403,8 +400,8 @@ static uint32_t dci_nr_format_0_1_sizeof(const srsran_dci_cfg_nr_t* cfg, srsran_
return 0;
}
// SRS request - 2 bits
count += 2;
// SRS request - 2 or 3 bits
count += cfg->enable_sul ? 3 : 2;
// CSI request - 0, 1, 2, 3, 4, 5, or 6 bits
count += SRSRAN_MIN(6, cfg->report_trigger_size);
@ -444,10 +441,10 @@ static int dci_nr_format_0_1_pack(const srsran_dci_nr_t* q, const srsran_dci_ul_
uint8_t* y = msg->payload;
// Identifier for DCI formats – 1 bit
*(y++) = 0;
*(y++) = 0; // The value of this bit field is always set to 0, indicating an UL DCI format
// Carrier indicator – 0 or 3 bits
srsran_bit_unpack(dci->cc_id, &y, SRSRAN_MIN(cfg->carrier_indicator_size, 3));
srsran_bit_unpack(dci->cc_id, &y, cfg->carrier_indicator_size);
// UL/SUL indicator – 0 bit for UEs not configured with supplementaryUplink ... otherwise, 1 bit
srsran_bit_unpack(dci->sul, &y, cfg->enable_sul ? 1 : 0);
@ -481,7 +478,7 @@ static int dci_nr_format_0_1_pack(const srsran_dci_nr_t* q, const srsran_dci_ul_
srsran_bit_unpack(dci->pid, &y, 4);
// 1st DAI - 1 or 2 bits
if (cfg->pusch_tx_config_codebook == srsran_pdsch_harq_ack_codebook_semi_static) {
if (cfg->harq_ack_codebok == srsran_pdsch_harq_ack_codebook_semi_static) {
srsran_bit_unpack(dci->dai1, &y, 1);
} else {
srsran_bit_unpack(dci->dai1, &y, 2);
@ -489,26 +486,17 @@ static int dci_nr_format_0_1_pack(const srsran_dci_nr_t* q, const srsran_dci_ul_
// 2st DAI - 0 or 2 bits
if (cfg->dynamic_dual_harq_ack_codebook) {
srsran_bit_unpack(dci->dai2, &y, 1);
srsran_bit_unpack(dci->dai2, &y, 2);
}
// TPC command for scheduled PUSCH – 2 bits
srsran_bit_unpack(dci->tpc, &y, 2);
// SRS resource indicator
uint32_t N_srs = SRSRAN_MIN(1, cfg->nof_srs);
if (cfg->pusch_tx_config_codebook) {
uint32_t N = 0;
for (uint32_t k = 1; k < SRSRAN_MIN(cfg->nof_ul_layers, cfg->nof_srs); k++) {
N += cfg->nof_srs / k;
}
srsran_bit_unpack(dci->srs_id, &y, N);
} else {
srsran_bit_unpack(dci->srs_id, &y, N_srs);
}
srsran_bit_unpack(dci->srs_id, &y, dci_nr_srs_id_size(cfg));
// Precoding information and number of layers
if (cfg->pusch_tx_config_codebook) {
if (cfg->pusch_tx_config_non_codebook) {
ERROR("Not implemented");
return 0;
}
@ -521,8 +509,8 @@ static int dci_nr_format_0_1_pack(const srsran_dci_nr_t* q, const srsran_dci_ul_
return 0;
}
// SRS request - 2 bits
srsran_bit_unpack(dci->srs_request, &y, 2);
// SRS request - 2 or 3 bits
srsran_bit_unpack(dci->srs_request, &y, cfg->enable_sul ? 3 : 2);
// CSI request - 0, 1, 2, 3, 4, 5, or 6 bits
srsran_bit_unpack(dci->csi_request, &y, SRSRAN_MIN(6, cfg->report_trigger_size));
@ -548,7 +536,7 @@ static int dci_nr_format_0_1_pack(const srsran_dci_nr_t* q, const srsran_dci_ul_
msg->nof_bits = srsran_dci_nr_size(q, msg->ctx.ss_type, srsran_dci_format_nr_0_1);
if (msg->nof_bits != y - msg->payload) {
ERROR("Packed bits read (%d) do NOT match payload size (%d)", msg->nof_bits, (int)(y - msg->payload));
ERROR("Unpacked bits read (%d) do NOT match payload size (%d)", msg->nof_bits, (int)(y - msg->payload));
return SRSRAN_ERROR;
}
@ -607,7 +595,7 @@ static int dci_nr_format_0_1_unpack(const srsran_dci_nr_t* q, srsran_dci_msg_nr_
dci->pid = srsran_bit_pack(&y, 4);
// 1st DAI - 1 or 2 bits
if (cfg->pusch_tx_config_codebook == srsran_pdsch_harq_ack_codebook_semi_static) {
if (cfg->harq_ack_codebok == srsran_pdsch_harq_ack_codebook_semi_static) {
dci->dai1 = srsran_bit_pack(&y, 1);
} else {
dci->dai1 = srsran_bit_pack(&y, 2);
@ -622,19 +610,10 @@ static int dci_nr_format_0_1_unpack(const srsran_dci_nr_t* q, srsran_dci_msg_nr_
dci->tpc = srsran_bit_pack(&y, 2);
// SRS resource indicator
uint32_t N_srs = SRSRAN_MIN(1, cfg->nof_srs);
if (cfg->pusch_tx_config_codebook) {
uint32_t N = 0;
for (uint32_t k = 1; k < SRSRAN_MIN(cfg->nof_ul_layers, cfg->nof_srs); k++) {
N += cfg->nof_srs / k;
}
dci->srs_id = srsran_bit_pack(&y, N);
} else {
dci->srs_id = srsran_bit_pack(&y, N_srs);
}
dci->srs_id = srsran_bit_pack(&y, dci_nr_srs_id_size(cfg));
// Precoding information and number of layers
if (cfg->pusch_tx_config_codebook) {
if (cfg->pusch_tx_config_non_codebook) {
ERROR("Not implemented");
return 0;
}
@ -647,8 +626,8 @@ static int dci_nr_format_0_1_unpack(const srsran_dci_nr_t* q, srsran_dci_msg_nr_
return 0;
}
// SRS request - 2 bits
dci->srs_request = srsran_bit_pack(&y, 2);
// SRS request - 2 or 3 bits
dci->srs_request = srsran_bit_pack(&y, cfg->enable_sul ? 3 : 2);
// CSI request - 0, 1, 2, 3, 4, 5, or 6 bits
dci->csi_request = srsran_bit_pack(&y, SRSRAN_MIN(6, cfg->report_trigger_size));
@ -687,8 +666,14 @@ dci_nr_format_0_1_to_str(const srsran_dci_nr_t* q, const srsran_dci_ul_nr_t* dci
const srsran_dci_cfg_nr_t* cfg = &q->cfg;
// Print format
len = srsran_print_check(
str, str_len, len, "rnti=%04x L=%d cce=%d dci=0_0 ", dci->ctx.rnti, dci->ctx.location.L, dci->ctx.location.ncce);
len = srsran_print_check(str,
str_len,
len,
"rnti=%04x L=%d cce=%d dci=%s ",
dci->ctx.rnti,
dci->ctx.location.L,
dci->ctx.location.ncce,
srsran_dci_format_nr_string(dci->ctx.format));
// Carrier indicator – 0 or 3 bits
if (cfg->carrier_indicator_size) {
@ -717,7 +702,7 @@ dci_nr_format_0_1_to_str(const srsran_dci_nr_t* q, const srsran_dci_ul_nr_t* dci
}
// Modulation and coding scheme – 5 bits
len = srsran_print_check(str, str_len, len, "mcs=%D ", dci->mcs);
len = srsran_print_check(str, str_len, len, "mcs=%d ", dci->mcs);
// New data indicator – 1 bit
len = srsran_print_check(str, str_len, len, "ndi=%d ", dci->ndi);
@ -740,10 +725,12 @@ dci_nr_format_0_1_to_str(const srsran_dci_nr_t* q, const srsran_dci_ul_nr_t* dci
len = srsran_print_check(str, str_len, len, "tpc=%d ", dci->tpc);
// SRS resource indicator
len = srsran_print_check(str, str_len, len, "srs_id=%d ", dci->srs_id);
if (dci_nr_srs_id_size(cfg) > 0) {
len = srsran_print_check(str, str_len, len, "srs_id=%d ", dci->srs_id);
}
// Precoding information and number of layers
if (cfg->pusch_tx_config_codebook) {
if (cfg->pusch_tx_config_non_codebook) {
ERROR("Not implemented");
return 0;
}
@ -1193,10 +1180,10 @@ static uint32_t dci_nr_format_1_1_sizeof(const srsran_dci_cfg_nr_t* cfg, srsran_
count += 1;
// Carrier indicator – 0 or 3 bits
count += (int)SRSRAN_MIN(cfg->carrier_indicator_size, 3);
count += (int)cfg->carrier_indicator_size;
// Bandwidth part indicator – 0, 1 or 2 bits
count += (int)SRSRAN_MIN(dci_nr_bwp_id_size(cfg->nof_ul_bwp), 2);
count += (int)dci_nr_bwp_id_size(cfg->nof_dl_bwp);
// Frequency domain resource assignment
count += dci_nr_freq_resource_size(cfg->pdsch_alloc_type, cfg->nof_rb_groups, cfg->bwp_dl_active_bw);
@ -1260,6 +1247,9 @@ static uint32_t dci_nr_format_1_1_sizeof(const srsran_dci_cfg_nr_t* cfg, srsran_
// TPC command for scheduled PUCCH – 2 bits
count += 2;
// PUCCH resource indicator – 3 bits
count += 3;
// PDSCH-to-HARQ_feedback timing indicator – 0, 1, 2, or 3 bits
count += (int)CEIL_LOG2(cfg->nof_dl_to_ul_ack);
@ -1278,7 +1268,7 @@ static uint32_t dci_nr_format_1_1_sizeof(const srsran_dci_cfg_nr_t* cfg, srsran_
}
// SRS request – 2 or 3 bits
count += cfg->enable_sul ? 2 : 3;
count += cfg->enable_sul ? 3 : 2;
// CBG transmission information (CBGTI) – 0, 2, 4, 6, or 8 bits
count += cfg->pdsch_nof_cbg;
@ -1312,7 +1302,7 @@ static int dci_nr_format_1_1_pack(const srsran_dci_nr_t* q, const srsran_dci_dl_
srsran_bit_unpack(dci->cc_id, &y, cfg->carrier_indicator_size);
// Bandwidth part indicator – 0, 1 or 2 bits
srsran_bit_unpack(dci->bwp_id, &y, dci_nr_bwp_id_size(cfg->nof_ul_bwp));
srsran_bit_unpack(dci->bwp_id, &y, dci_nr_bwp_id_size(cfg->nof_dl_bwp));
// Frequency domain resource assignment
srsran_bit_unpack(dci->freq_domain_assigment,
@ -1379,8 +1369,11 @@ static int dci_nr_format_1_1_pack(const srsran_dci_nr_t* q, const srsran_dci_dl_
// TPC command for scheduled PUCCH – 2 bits
srsran_bit_unpack(dci->tpc, &y, 2);
// PUCCH resource indicator – 3 bits
srsran_bit_unpack(dci->pucch_resource, &y, 3);
// PDSCH-to-HARQ_feedback timing indicator – 0, 1, 2, or 3 bits
srsran_bit_unpack(dci->harq_feedback, &y, cfg->nof_dl_to_ul_ack);
srsran_bit_unpack(dci->harq_feedback, &y, (int)CEIL_LOG2(cfg->nof_dl_to_ul_ack));
// Antenna port(s) – 4, 5, or 6 bits
srsran_bit_unpack(dci->ports, &y, 4);
@ -1397,7 +1390,7 @@ static int dci_nr_format_1_1_pack(const srsran_dci_nr_t* q, const srsran_dci_dl_
}
// SRS request – 2 or 3 bits
srsran_bit_unpack(dci->srs_request, &y, cfg->enable_sul ? 2 : 3);
srsran_bit_unpack(dci->srs_request, &y, cfg->enable_sul ? 3 : 2);
// CBG transmission information (CBGTI) – 0, 2, 4, 6, or 8 bits
srsran_bit_unpack(dci->cbg_info, &y, cfg->pdsch_nof_cbg);
@ -1410,13 +1403,11 @@ static int dci_nr_format_1_1_pack(const srsran_dci_nr_t* q, const srsran_dci_dl_
// DMRS sequence initialization – 1 bit
srsran_bit_unpack(dci->dmrs_id, &y, 1);
msg->nof_bits = srsran_dci_nr_size(q, msg->ctx.ss_type, srsran_dci_format_nr_1_1);
uint32_t nof_bits = (uint32_t)(y - msg->payload);
if (msg->nof_bits != nof_bits) {
ERROR("Unpacked bits read (%d) do NOT match payload size (%d)", msg->nof_bits, nof_bits);
msg->nof_bits = srsran_dci_nr_size(q, msg->ctx.ss_type, srsran_dci_format_nr_1_1);
if (msg->nof_bits != y - msg->payload) {
ERROR("Unpacked bits read (%d) do NOT match payload size (%d)", msg->nof_bits, (int)(y - msg->payload));
return SRSRAN_ERROR;
}
return SRSRAN_SUCCESS;
}
@ -1431,7 +1422,7 @@ static int dci_nr_format_1_1_unpack(const srsran_dci_nr_t* q, srsran_dci_msg_nr_
return SRSRAN_ERROR;
}
uint32_t nof_bits = srsran_dci_nr_size(q, msg->ctx.ss_type, srsran_dci_format_nr_1_0);
uint32_t nof_bits = srsran_dci_nr_size(q, msg->ctx.ss_type, srsran_dci_format_nr_1_1);
if (msg->nof_bits != nof_bits) {
ERROR("Invalid number of bits %d, expected %d", msg->nof_bits, nof_bits);
return SRSRAN_ERROR;
@ -1448,7 +1439,7 @@ static int dci_nr_format_1_1_unpack(const srsran_dci_nr_t* q, srsran_dci_msg_nr_
dci->cc_id = srsran_bit_pack(&y, cfg->carrier_indicator_size);
// Bandwidth part indicator – 0, 1 or 2 bits
dci->bwp_id = srsran_bit_pack(&y, dci_nr_bwp_id_size(cfg->nof_ul_bwp));
dci->bwp_id = srsran_bit_pack(&y, dci_nr_bwp_id_size(cfg->nof_dl_bwp));
// Frequency domain resource assignment
dci->freq_domain_assigment =
@ -1514,8 +1505,11 @@ static int dci_nr_format_1_1_unpack(const srsran_dci_nr_t* q, srsran_dci_msg_nr_
// TPC command for scheduled PUCCH – 2 bits
dci->tpc = srsran_bit_pack(&y, 2);
// PUCCH resource indicator – 3 bits
dci->pucch_resource = srsran_bit_pack(&y, 3);
// PDSCH-to-HARQ_feedback timing indicator – 0, 1, 2, or 3 bits
dci->harq_feedback = srsran_bit_pack(&y, cfg->nof_dl_to_ul_ack);
dci->harq_feedback = srsran_bit_pack(&y, (int)CEIL_LOG2(cfg->nof_dl_to_ul_ack));
// Antenna port(s) – 4, 5, or 6 bits
dci->ports = srsran_bit_pack(&y, 4);
@ -1532,7 +1526,7 @@ static int dci_nr_format_1_1_unpack(const srsran_dci_nr_t* q, srsran_dci_msg_nr_
}
// SRS request – 2 or 3 bits
dci->srs_request = srsran_bit_pack(&y, cfg->enable_sul ? 2 : 3);
dci->srs_request = srsran_bit_pack(&y, cfg->enable_sul ? 3 : 2);
// CBG transmission information (CBGTI) – 0, 2, 4, 6, or 8 bits
dci->cbg_info = srsran_bit_pack(&y, cfg->pdsch_nof_cbg);
@ -1547,7 +1541,7 @@ static int dci_nr_format_1_1_unpack(const srsran_dci_nr_t* q, srsran_dci_msg_nr_
uint32_t nof_unpacked_bits = (uint32_t)(y - msg->payload);
if (nof_unpacked_bits != nof_bits) {
ERROR("Unpacked bits read (%d) do NOT match payload size (%d)", msg->nof_bits, nof_bits);
ERROR("Unpacked bits read (%d) do NOT match payload size (%d)", nof_unpacked_bits, nof_bits);
return SRSRAN_ERROR;
}
@ -1980,32 +1974,62 @@ int srsran_dci_nr_ul_unpack(const srsran_dci_nr_t* q, srsran_dci_msg_nr_t* msg,
return SRSRAN_ERROR;
}
int srsran_dci_ctx_to_str(const srsran_dci_ctx_t* ctx, char* str, uint32_t str_len)
{
// Print format
return srsran_print_check(str,
str_len,
0,
"rnti=%04x L=%d cce=%d dci=%s ",
ctx->rnti,
ctx->location.L,
ctx->location.ncce,
srsran_dci_format_nr_string(ctx->format));
}
int srsran_dci_ul_nr_to_str(const srsran_dci_nr_t* q, const srsran_dci_ul_nr_t* dci, char* str, uint32_t str_len)
{
uint32_t len = 0;
len += srsran_dci_ctx_to_str(&dci->ctx, &str[len], str_len - len);
// Pack DCI
switch (dci->ctx.format) {
case srsran_dci_format_nr_0_0:
return dci_nr_format_0_0_to_str(dci, str, str_len);
len += dci_nr_format_0_0_to_str(dci, &str[len], str_len - len);
break;
case srsran_dci_format_nr_0_1:
return dci_nr_format_0_1_to_str(q, dci, str, str_len);
len += dci_nr_format_0_1_to_str(q, dci, &str[len], str_len - len);
break;
case srsran_dci_format_nr_rar:
return dci_nr_rar_to_str(dci, str, str_len);
default:; // Do nothing
len += dci_nr_rar_to_str(dci, &str[len], str_len - len);
break;
default:
len = srsran_print_check(str, str_len, len, "<invalid ul dci> ");
break;
}
return srsran_print_check(str, str_len, 0, "unknown");
return len;
}
int srsran_dci_dl_nr_to_str(const srsran_dci_nr_t* q, const srsran_dci_dl_nr_t* dci, char* str, uint32_t str_len)
{
uint32_t len = 0;
len += srsran_dci_ctx_to_str(&dci->ctx, &str[len], str_len - len);
// Pack DCI
switch (dci->ctx.format) {
case srsran_dci_format_nr_1_0:
return dci_nr_format_1_0_to_str(dci, str, str_len);
len += dci_nr_format_1_0_to_str(dci, &str[len], str_len - len);
break;
case srsran_dci_format_nr_1_1:
return dci_nr_format_1_1_to_str(q, dci, str, str_len);
default:; // Do nothing
len += dci_nr_format_1_1_to_str(q, dci, &str[len], str_len - len);
break;
default:
len = srsran_print_check(str, str_len, len, "<invalid dl dci> ");
break;
}
return srsran_print_check(str, str_len, 0, "unknown");
return len;
}

35
lib/src/phy/phch/ra_ul_nr.c
Unescape Escape View File

@ -25,22 +25,23 @@ typedef struct {
uint32_t L;
} ue_ra_time_resource_t;
static const ue_ra_time_resource_t ue_ul_default_A_lut[16] = {{srsran_sch_mapping_type_A, 0, 0, 14},
{srsran_sch_mapping_type_A, 0, 0, 12},
{srsran_sch_mapping_type_A, 0, 0, 10},
{srsran_sch_mapping_type_B, 0, 2, 10},
{srsran_sch_mapping_type_B, 0, 4, 10},
{srsran_sch_mapping_type_B, 0, 4, 8},
{srsran_sch_mapping_type_B, 0, 4, 6},
{srsran_sch_mapping_type_A, 1, 0, 14},
{srsran_sch_mapping_type_A, 1, 0, 12},
{srsran_sch_mapping_type_A, 1, 0, 10},
{srsran_sch_mapping_type_A, 2, 0, 14},
{srsran_sch_mapping_type_A, 2, 0, 12},
{srsran_sch_mapping_type_A, 2, 0, 10},
{srsran_sch_mapping_type_B, 0, 8, 6},
{srsran_sch_mapping_type_A, 3, 0, 14},
{srsran_sch_mapping_type_A, 3, 0, 10}};
static const ue_ra_time_resource_t ue_ul_default_A_lut[SRSRAN_MAX_NOF_TIME_RA] = {
{srsran_sch_mapping_type_A, 0, 0, 14},
{srsran_sch_mapping_type_A, 0, 0, 12},
{srsran_sch_mapping_type_A, 0, 0, 10},
{srsran_sch_mapping_type_B, 0, 2, 10},
{srsran_sch_mapping_type_B, 0, 4, 10},
{srsran_sch_mapping_type_B, 0, 4, 8},
{srsran_sch_mapping_type_B, 0, 4, 6},
{srsran_sch_mapping_type_A, 1, 0, 14},
{srsran_sch_mapping_type_A, 1, 0, 12},
{srsran_sch_mapping_type_A, 1, 0, 10},
{srsran_sch_mapping_type_A, 2, 0, 14},
{srsran_sch_mapping_type_A, 2, 0, 12},
{srsran_sch_mapping_type_A, 2, 0, 10},
{srsran_sch_mapping_type_B, 0, 8, 6},
{srsran_sch_mapping_type_A, 3, 0, 14},
{srsran_sch_mapping_type_A, 3, 0, 10}};
int srsran_ra_ul_nr_pusch_time_resource_default_A(uint32_t scs_cfg, uint32_t m, srsran_sch_grant_nr_t* grant)
{
@ -55,7 +56,7 @@ int srsran_ra_ul_nr_pusch_time_resource_default_A(uint32_t scs_cfg, uint32_t m,
return SRSRAN_ERROR;
}
if (m >= 16) {
if (m >= SRSRAN_MAX_NOF_TIME_RA) {
ERROR("m (%d) is out-of-range", m);
return SRSRAN_ERROR_INVALID_INPUTS;
}

303
lib/src/phy/phch/test/dci_nr_test.c
Unescape Escape View File

@ -12,8 +12,14 @@
#include "srsran/common/test_common.h"
#include "srsran/phy/phch/dci_nr.h"
#include "srsran/phy/utils/debug.h"
#include "srsran/phy/utils/random.h"
#include <getopt.h>
static int test_52prb()
static uint32_t nof_repetitions = 1024;
static srsran_random_t random_gen = NULL;
static int test_52prb_base()
{
// Default configuration with all options disabled
srsran_dci_cfg_nr_t cfg = {};
@ -30,6 +36,49 @@ static int test_52prb()
cfg.monitor_0_0_and_1_0 = true;
cfg.monitor_0_1_and_1_1 = true;
// Common parameters
cfg.enable_hopping = false;
cfg.enable_sul = false;
// Common DCI 0_1 and 1_1 parameters
cfg.carrier_indicator_size = 0;
cfg.harq_ack_codebok = srsran_pdsch_harq_ack_codebook_dynamic;
cfg.nof_rb_groups = 0; // Only for allocation type 0
// DCI 0_1 parameters
cfg.nof_ul_bwp = 0;
cfg.nof_ul_time_res = 2;
cfg.nof_srs = 1;
cfg.nof_ul_layers = 1;
cfg.pusch_nof_cbg = 0;
cfg.report_trigger_size = 0;
cfg.enable_transform_precoding = false;
cfg.dynamic_dual_harq_ack_codebook = false;
cfg.pusch_tx_config_non_codebook = false;
cfg.pusch_dmrs_type2 = false;
cfg.pusch_dmrs_double = false;
cfg.pusch_ptrs = false;
cfg.pusch_dynamic_betas = false;
cfg.pusch_alloc_type = srsran_resource_alloc_type1;
// DCI 1_1 parameters
cfg.nof_dl_bwp = 0;
cfg.nof_dl_time_res = 1;
cfg.nof_aperiodic_zp = 0;
cfg.pdsch_nof_cbg = 0;
cfg.nof_dl_to_ul_ack = 5;
cfg.pdsch_inter_prb_to_prb = false;
cfg.pdsch_rm_pattern1 = false;
cfg.pdsch_rm_pattern2 = false;
cfg.pdsch_2cw = false;
cfg.multiple_scell = false;
cfg.pdsch_dmrs_type2 = false;
cfg.pdsch_dmrs_double = false;
cfg.pdsch_tci = false;
cfg.pdsch_cbg_flush = false;
cfg.pdsch_dynamic_bundling = false;
cfg.pdsch_alloc_type = srsran_resource_alloc_type1;
// Configure DCI
srsran_dci_nr_t dci = {};
TESTASSERT(srsran_dci_nr_set_cfg(&dci, &cfg) == SRSRAN_SUCCESS);
@ -39,15 +88,259 @@ static int test_52prb()
TESTASSERT(srsran_dci_nr_size(&dci, srsran_search_space_type_common_3, srsran_dci_format_nr_1_0) == 39);
TESTASSERT(srsran_dci_nr_size(&dci, srsran_search_space_type_ue, srsran_dci_format_nr_0_0) == 39);
TESTASSERT(srsran_dci_nr_size(&dci, srsran_search_space_type_ue, srsran_dci_format_nr_1_0) == 39);
TESTASSERT(srsran_dci_nr_size(&dci, srsran_search_space_type_ue, srsran_dci_format_nr_0_1) == 28);
TESTASSERT(srsran_dci_nr_size(&dci, srsran_search_space_type_ue, srsran_dci_format_nr_1_1) == 26);
TESTASSERT(srsran_dci_nr_size(&dci, srsran_search_space_type_ue, srsran_dci_format_nr_0_1) == 36);
TESTASSERT(srsran_dci_nr_size(&dci, srsran_search_space_type_ue, srsran_dci_format_nr_1_1) == 41);
srsran_dci_ctx_t ctx = {};
ctx.rnti = 0x1234;
ctx.ss_type = srsran_search_space_type_common_3;
ctx.rnti_type = srsran_rnti_type_c;
// Test UL DCI 0_0 Packing/Unpacking and info
ctx.format = srsran_dci_format_nr_0_0;
for (uint32_t i = 0; i < nof_repetitions; i++) {
srsran_dci_ul_nr_t dci_tx = {};
dci_tx.ctx = ctx;
dci_tx.freq_domain_assigment = srsran_random_uniform_int_dist(random_gen, 0, (int)(1U << 11U) - 1);
dci_tx.time_domain_assigment = srsran_random_uniform_int_dist(random_gen, 0, (int)cfg.nof_ul_time_res - 1);
dci_tx.freq_hopping_flag = 0; // unavailable
dci_tx.mcs = srsran_random_uniform_int_dist(random_gen, 0, 31);
dci_tx.rv = srsran_random_uniform_int_dist(random_gen, 0, 3);
dci_tx.ndi = srsran_random_uniform_int_dist(random_gen, 0, 1);
dci_tx.pid = srsran_random_uniform_int_dist(random_gen, 0, 15);
dci_tx.tpc = srsran_random_uniform_int_dist(random_gen, 0, 3);
dci_tx.frequency_offset = 0; // unavailable
dci_tx.csi_request = 0; // unavailable
dci_tx.sul = 0; // unavailable
dci_tx.cc_id = 0; // unavailable
dci_tx.bwp_id = 0; // unavailable
dci_tx.dai1 = 0; // unavailable
dci_tx.dai2 = 0; // unavailable
dci_tx.srs_id = 0; // unavailable
dci_tx.ports = 0; // unavailable
dci_tx.srs_request = 0; // unavailable
dci_tx.cbg_info = 0; // unavailable
dci_tx.ptrs_id = 0; // unavailable
dci_tx.beta_id = 0; // unavailable
dci_tx.dmrs_id = 0; // unavailable
dci_tx.ulsch = 0; // unavailable
// Pack
srsran_dci_msg_nr_t dci_msg = {};
TESTASSERT(srsran_dci_nr_ul_pack(&dci, &dci_tx, &dci_msg) == SRSRAN_SUCCESS);
// Unpack
srsran_dci_ul_nr_t dci_rx = {};
TESTASSERT(srsran_dci_nr_ul_unpack(&dci, &dci_msg, &dci_rx) == SRSRAN_SUCCESS);
// To string
char str[512];
TESTASSERT(srsran_dci_ul_nr_to_str(&dci, &dci_tx, str, (uint32_t)sizeof(str)) != 0);
INFO("Tx: %s", str);
TESTASSERT(srsran_dci_ul_nr_to_str(&dci, &dci_rx, str, (uint32_t)sizeof(str)) != 0);
INFO("Rx: %s", str);
// Assert
TESTASSERT(memcmp(&dci_tx, &dci_rx, sizeof(srsran_dci_ul_nr_t)) == 0);
}
// Test UL DCI 0_1 Packing/Unpacking and info
ctx.ss_type = srsran_search_space_type_ue;
ctx.format = srsran_dci_format_nr_0_1;
for (uint32_t i = 0; i < nof_repetitions; i++) {
srsran_dci_ul_nr_t dci_tx = {};
dci_tx.ctx = ctx;
dci_tx.freq_domain_assigment = srsran_random_uniform_int_dist(random_gen, 0, (int)(1U << 11U) - 1);
dci_tx.time_domain_assigment = srsran_random_uniform_int_dist(random_gen, 0, (int)cfg.nof_ul_time_res - 1);
dci_tx.freq_hopping_flag = 0; // unavailable
dci_tx.mcs = srsran_random_uniform_int_dist(random_gen, 0, 31);
dci_tx.rv = srsran_random_uniform_int_dist(random_gen, 0, 3);
dci_tx.ndi = srsran_random_uniform_int_dist(random_gen, 0, 1);
dci_tx.pid = srsran_random_uniform_int_dist(random_gen, 0, 15);
dci_tx.tpc = srsran_random_uniform_int_dist(random_gen, 0, 3);
dci_tx.frequency_offset = 0; // unavailable
dci_tx.csi_request = 0; // unavailable
dci_tx.sul = 0; // unavailable
dci_tx.cc_id = 0; // unavailable
dci_tx.bwp_id = 0; // unavailable
dci_tx.dai1 = srsran_random_uniform_int_dist(random_gen, 0, 3);
dci_tx.dai2 = 0; // unavailable
dci_tx.srs_id = 0; // unavailable
dci_tx.ports = srsran_random_uniform_int_dist(random_gen, 0, 7);
dci_tx.srs_request = srsran_random_uniform_int_dist(random_gen, 0, 3);
dci_tx.cbg_info = 0; // unavailable
dci_tx.ptrs_id = 0; // unavailable
dci_tx.beta_id = 0; // unavailable
dci_tx.dmrs_id = srsran_random_uniform_int_dist(random_gen, 0, 1);
dci_tx.ulsch = srsran_random_uniform_int_dist(random_gen, 0, 1);
// Pack
srsran_dci_msg_nr_t dci_msg = {};
TESTASSERT(srsran_dci_nr_ul_pack(&dci, &dci_tx, &dci_msg) == SRSRAN_SUCCESS);
// Unpack
srsran_dci_ul_nr_t dci_rx = {};
TESTASSERT(srsran_dci_nr_ul_unpack(&dci, &dci_msg, &dci_rx) == SRSRAN_SUCCESS);
// To string
char str[512];
TESTASSERT(srsran_dci_ul_nr_to_str(&dci, &dci_tx, str, (uint32_t)sizeof(str)) != 0);
INFO("Tx: %s", str);
TESTASSERT(srsran_dci_ul_nr_to_str(&dci, &dci_rx, str, (uint32_t)sizeof(str)) != 0);
INFO("Rx: %s", str);
// Assert
TESTASSERT(memcmp(&dci_tx, &dci_rx, sizeof(srsran_dci_ul_nr_t)) == 0);
}
// Test UL DCI 1_0 Packing/Unpacking and info
ctx.format = srsran_dci_format_nr_1_0;
for (uint32_t i = 0; i < nof_repetitions; i++) {
srsran_dci_dl_nr_t dci_tx = {};
dci_tx.ctx = ctx;
dci_tx.freq_domain_assigment = srsran_random_uniform_int_dist(random_gen, 0, (int)(1U << 11U) - 1);
dci_tx.time_domain_assigment = srsran_random_uniform_int_dist(random_gen, 0, (int)cfg.nof_ul_time_res - 1);
dci_tx.vrb_to_prb_mapping = 0; // unavailable
dci_tx.mcs = srsran_random_uniform_int_dist(random_gen, 0, 31);
dci_tx.rv = srsran_random_uniform_int_dist(random_gen, 0, 3);
dci_tx.ndi = srsran_random_uniform_int_dist(random_gen, 0, 1);
dci_tx.pid = srsran_random_uniform_int_dist(random_gen, 0, 15);
dci_tx.tpc = srsran_random_uniform_int_dist(random_gen, 0, 3);
dci_tx.pucch_resource = srsran_random_uniform_int_dist(random_gen, 0, 7);
dci_tx.harq_feedback = srsran_random_uniform_int_dist(random_gen, 0, 7);
dci_tx.smi = 0; // unavailable
dci_tx.sm = 0; // unavailable
dci_tx.tb_scaling = 0; // unavailable
dci_tx.sii = 0; // unavailable
dci_tx.mcs2 = 0; // unavailable
dci_tx.ndi2 = 0; // unavailable
dci_tx.rv2 = 0; // unavailable
dci_tx.cc_id = 0; // unavailable
dci_tx.bwp_id = 0; // unavailable
dci_tx.rm_pattern1 = 0; // unavailable
dci_tx.rm_pattern2 = 0; // unavailable
dci_tx.zp_csi_rs_id = 0; // unavailable
dci_tx.ports = 0; // unavailable
dci_tx.tci = 0; // unavailable
dci_tx.srs_request = 0; // unavailable
dci_tx.cbg_info = 0; // unavailable
dci_tx.cbg_flush = 0; // unavailable
dci_tx.dmrs_id = 0; // unavailable
// Pack
srsran_dci_msg_nr_t dci_msg = {};
TESTASSERT(srsran_dci_nr_dl_pack(&dci, &dci_tx, &dci_msg) == SRSRAN_SUCCESS);
// Unpack
srsran_dci_dl_nr_t dci_rx = {};
TESTASSERT(srsran_dci_nr_dl_unpack(&dci, &dci_msg, &dci_rx) == SRSRAN_SUCCESS);
// To string
char str[512];
TESTASSERT(srsran_dci_dl_nr_to_str(&dci, &dci_tx, str, (uint32_t)sizeof(str)) != 0);
INFO("Tx: %s", str);
TESTASSERT(srsran_dci_dl_nr_to_str(&dci, &dci_rx, str, (uint32_t)sizeof(str)) != 0);
INFO("Rx: %s", str);
// Assert
TESTASSERT(memcmp(&dci_tx, &dci_rx, sizeof(srsran_dci_dl_nr_t)) == 0);
}
// Test UL DCI 1_0 Packing/Unpacking and info
ctx.format = srsran_dci_format_nr_1_1;
for (uint32_t i = 0; i < nof_repetitions; i++) {
srsran_dci_dl_nr_t dci_tx = {};
dci_tx.ctx = ctx;
dci_tx.freq_domain_assigment = srsran_random_uniform_int_dist(random_gen, 0, (int)(1U << 11U) - 1);
dci_tx.time_domain_assigment = srsran_random_uniform_int_dist(random_gen, 0, (int)cfg.nof_dl_time_res - 1);
dci_tx.vrb_to_prb_mapping = 0; // unavailable
dci_tx.mcs = srsran_random_uniform_int_dist(random_gen, 0, 31);
dci_tx.rv = srsran_random_uniform_int_dist(random_gen, 0, 3);
dci_tx.ndi = srsran_random_uniform_int_dist(random_gen, 0, 1);
dci_tx.pid = srsran_random_uniform_int_dist(random_gen, 0, 15);
dci_tx.tpc = srsran_random_uniform_int_dist(random_gen, 0, 3);
dci_tx.pucch_resource = srsran_random_uniform_int_dist(random_gen, 0, 7);
dci_tx.harq_feedback = srsran_random_uniform_int_dist(random_gen, 0, 7);
dci_tx.smi = 0; // unavailable
dci_tx.sm = 0; // unavailable
dci_tx.tb_scaling = 0; // unavailable
dci_tx.sii = 0; // unavailable
dci_tx.mcs2 = 0; // unavailable
dci_tx.ndi2 = 0; // unavailable
dci_tx.rv2 = 0; // unavailable
dci_tx.cc_id = 0; // unavailable
dci_tx.bwp_id = 0; // unavailable
dci_tx.rm_pattern1 = 0; // unavailable
dci_tx.rm_pattern2 = 0; // unavailable
dci_tx.zp_csi_rs_id = 0; // unavailable
dci_tx.ports = srsran_random_uniform_int_dist(random_gen, 0, 7);
dci_tx.tci = 0; // unavailable
dci_tx.srs_request = 0; // unavailable
dci_tx.cbg_info = 0; // unavailable
dci_tx.cbg_flush = 0; // unavailable
dci_tx.dmrs_id = 0; // unavailable
// Pack
srsran_dci_msg_nr_t dci_msg = {};
TESTASSERT(srsran_dci_nr_dl_pack(&dci, &dci_tx, &dci_msg) == SRSRAN_SUCCESS);
// Unpack
srsran_dci_dl_nr_t dci_rx = {};
TESTASSERT(srsran_dci_nr_dl_unpack(&dci, &dci_msg, &dci_rx) == SRSRAN_SUCCESS);
// To string
char str[512];
TESTASSERT(srsran_dci_dl_nr_to_str(&dci, &dci_tx, str, (uint32_t)sizeof(str)) != 0);
INFO("Tx: %s", str);
TESTASSERT(srsran_dci_dl_nr_to_str(&dci, &dci_rx, str, (uint32_t)sizeof(str)) != 0);
INFO("Rx: %s", str);
// Assert
TESTASSERT(memcmp(&dci_tx, &dci_rx, sizeof(srsran_dci_dl_nr_t)) == 0);
}
return SRSRAN_SUCCESS;
}
static void usage(char* prog)
{
printf("Usage: %s [cpndv]\n", prog);
printf("\t-v Increase verbose [default none]\n");
printf("\t-R Set number of Packing/Unpacking [default %d]\n", nof_repetitions);
}
static void parse_args(int argc, char** argv)
{
int opt;
while ((opt = getopt(argc, argv, "vR")) != -1) {
switch (opt) {
case 'v':
srsran_verbose++;
break;
case 'R':
nof_repetitions = (uint32_t)strtol(argv[optind], NULL, 10);
break;
default:
usage(argv[0]);
exit(-1);
}
}
}
int main(int argc, char** argv)
{
TESTASSERT(test_52prb() == SRSRAN_SUCCESS);
parse_args(argc, argv);
return SRSRAN_SUCCESS;
int ret = SRSRAN_ERROR;
random_gen = srsran_random_init(1234);
if (test_52prb_base() < SRSRAN_SUCCESS) {
goto clean_exit;
}
ret = SRSRAN_SUCCESS;
clean_exit:
srsran_random_free(random_gen);
return ret;
}

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