5g-team
/
srsRAN_4G
mirror of https://github.com/pvnis/srsRAN_4G.git
2
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sched rand test refactor: removal of redundant tests

Browse Source
master
Francisco 4 years ago committed by Andre Puschmann
parent cba0cc457f
commit 783131a4e1
7 changed files with 79 additions and 184 deletions
Show Stats Download Patch File Download Diff File

2
srsenb/test/mac/sched_ca_test.cc
Unescape Escape View File

@ -119,7 +119,7 @@ int test_scell_activation(test_scell_activation_params params)
// Event PRACH: PRACH takes place for "rnti1", and carrier "pcell_idx" // Event PRACH: PRACH takes place for "rnti1", and carrier "pcell_idx"
generator.step_until(prach_tti); generator.step_until(prach_tti);
tti_ev::user_cfg_ev* user = generator.add_new_default_user(duration, sim_args.default_ue_sim_cfg.ue_cfg); tti_ev::user_cfg_ev* user = generator.add_new_default_user(duration, sim_args.default_ue_sim_cfg);
user->rnti = rnti1; user->rnti = rnti1;
tester.test_next_ttis(generator.tti_events); tester.test_next_ttis(generator.tti_events);
TESTASSERT(tester.sched_sim->user_exists(rnti1)); TESTASSERT(tester.sched_sim->user_exists(rnti1));

54
srsenb/test/mac/sched_sim_ue.cc
Unescape Escape View File

@ -38,11 +38,9 @@ bool sim_ue_ctxt_t::is_last_dl_retx(uint32_t ue_cc_idx, uint32_t pid) const
} }
ue_sim::ue_sim(uint16_t rnti_, ue_sim::ue_sim(uint16_t rnti_,
const std::vector<sched_interface::cell_cfg_t>& cell_params_,
const sched_interface::ue_cfg_t& ue_cfg_, const sched_interface::ue_cfg_t& ue_cfg_,
srslte::tti_point prach_tti_rx_, srslte::tti_point prach_tti_rx_,
uint32_t preamble_idx) : uint32_t preamble_idx)
cell_params(&cell_params_)
{ {
ctxt.rnti = rnti_; ctxt.rnti = rnti_;
ctxt.prach_tti_rx = prach_tti_rx_; ctxt.prach_tti_rx = prach_tti_rx_;
@ -210,12 +208,6 @@ void ue_sim::update_conn_state(const sf_output_res_t& sf_out)
} }
} }
} }
if (ctxt.msg4_tti_rx.is_valid()) {
if (to_tx_dl(ctxt.msg4_tti_rx) >= sf_out.tti_rx) {
ctxt.conres_rx = true;
}
}
} }
int sched_sim_base::add_user(uint16_t rnti, const sched_interface::ue_cfg_t& ue_cfg_, uint32_t preamble_idx) int sched_sim_base::add_user(uint16_t rnti, const sched_interface::ue_cfg_t& ue_cfg_, uint32_t preamble_idx)
@ -227,11 +219,9 @@ int sched_sim_base::add_user(uint16_t rnti, const sched_interface::ue_cfg_t& ue_
final_ue_cfg[rnti] = ue_cfg_; final_ue_cfg[rnti] = ue_cfg_;
auto rach_cfg = generate_rach_ue_cfg(ue_cfg_); auto rach_cfg = generate_rach_ue_cfg(ue_cfg_);
ue_db.insert(std::make_pair(rnti, ue_sim(rnti, *cell_params, rach_cfg, current_tti_rx, preamble_idx))); ue_db.insert(std::make_pair(rnti, ue_sim(rnti, rach_cfg, current_tti_rx, preamble_idx)));
CONDERROR(sched_ptr->ue_cfg(rnti, generate_rach_ue_cfg(ue_cfg_)) != SRSLTE_SUCCESS, CONDERROR(sched_ptr->ue_cfg(rnti, rach_cfg) != SRSLTE_SUCCESS, "Configuring new user rnti=0x%x to sched\n", rnti);
"Configuring new user rnti=0x%x to sched\n",
rnti);
sched_interface::dl_sched_rar_info_t rar_info = {}; sched_interface::dl_sched_rar_info_t rar_info = {};
rar_info.prach_tti = current_tti_rx.to_uint(); rar_info.prach_tti = current_tti_rx.to_uint();
@ -246,9 +236,8 @@ int sched_sim_base::add_user(uint16_t rnti, const sched_interface::ue_cfg_t& ue_
int sched_sim_base::ue_recfg(uint16_t rnti, const sched_interface::ue_cfg_t& ue_cfg_) int sched_sim_base::ue_recfg(uint16_t rnti, const sched_interface::ue_cfg_t& ue_cfg_)
{ {
ue_db.at(rnti).set_cfg(ue_cfg_);
CONDERROR(ue_db.count(rnti) == 0, "User must already exist to be configured\n"); CONDERROR(ue_db.count(rnti) == 0, "User must already exist to be configured\n");
ue_db.at(rnti).set_cfg(ue_cfg_);
CONDERROR(sched_ptr->ue_cfg(rnti, ue_cfg_) != SRSLTE_SUCCESS, "Configuring new user rnti=0x%x to sched\n", rnti); CONDERROR(sched_ptr->ue_cfg(rnti, ue_cfg_) != SRSLTE_SUCCESS, "Configuring new user rnti=0x%x to sched\n", rnti);
return SRSLTE_SUCCESS; return SRSLTE_SUCCESS;
@ -285,7 +274,7 @@ sim_enb_ctxt_t sched_sim_base::get_enb_ctxt() const
return ctxt; return ctxt;
} }
void sched_sim_base::set_default_tti_events(const sim_ue_ctxt_t& ue_ctxt, ue_tti_events& pending_events) int sched_sim_base::set_default_tti_events(const sim_ue_ctxt_t& ue_ctxt, ue_tti_events& pending_events)
{ {
pending_events.cc_list.clear(); pending_events.cc_list.clear();
pending_events.cc_list.resize(cell_params->size()); pending_events.cc_list.resize(cell_params->size());
@ -325,9 +314,11 @@ void sched_sim_base::set_default_tti_events(const sim_ue_ctxt_t& ue_ctxt, ue_tti
// TODO: UL CQI // TODO: UL CQI
} }
} }
return SRSLTE_SUCCESS;
} }
void sched_sim_base::apply_tti_events(sim_ue_ctxt_t& ue_ctxt, const ue_tti_events& events) int sched_sim_base::apply_tti_events(sim_ue_ctxt_t& ue_ctxt, const ue_tti_events& events)
{ {
for (uint32_t enb_cc_idx = 0; enb_cc_idx < events.cc_list.size(); ++enb_cc_idx) { for (uint32_t enb_cc_idx = 0; enb_cc_idx < events.cc_list.size(); ++enb_cc_idx) {
const auto& cc_feedback = events.cc_list[enb_cc_idx]; const auto& cc_feedback = events.cc_list[enb_cc_idx];
@ -365,7 +356,7 @@ void sched_sim_base::apply_tti_events(sim_ue_ctxt_t& ue_ctxt, const ue_tti_event
log_h->info("UL ACK rnti=0x%x tti_ul_tx=%u pid=%d\n", log_h->info("UL ACK rnti=0x%x tti_ul_tx=%u pid=%d\n",
ue_ctxt.rnti, ue_ctxt.rnti,
to_tx_ul(h.last_tti_rx).to_uint(), to_tx_ul(h.last_tti_rx).to_uint(),
cc_feedback.dl_pid); cc_feedback.ul_pid);
} }
// update scheduler // update scheduler
@ -383,6 +374,31 @@ void sched_sim_base::apply_tti_events(sim_ue_ctxt_t& ue_ctxt, const ue_tti_event
sched_ptr->ul_snr_info(events.tti_rx.to_uint(), ue_ctxt.rnti, enb_cc_idx, cc_feedback.ul_cqi, 0); sched_ptr->ul_snr_info(events.tti_rx.to_uint(), ue_ctxt.rnti, enb_cc_idx, cc_feedback.ul_cqi, 0);
} }
} }
if (not ue_ctxt.conres_rx and ue_ctxt.msg3_tti_rx.is_valid() and to_tx_ul(ue_ctxt.msg3_tti_rx) <= events.tti_rx) {
uint32_t enb_cc_idx = ue_ctxt.ue_cfg.supported_cc_list[0].enb_cc_idx;
auto& cc_feedback = events.cc_list[enb_cc_idx];
// Schedule Msg4 when Msg3 is received
if (cc_feedback.ul_pid >= 0 and cc_feedback.ul_ack) {
sched_interface::ue_cfg_t ue_cfg = generate_setup_ue_cfg(final_ue_cfg[ue_ctxt.rnti]);
TESTASSERT(ue_recfg(ue_ctxt.rnti, ue_cfg) == SRSLTE_SUCCESS);
uint32_t lcid = RB_ID_SRB0; // Use SRB0 to schedule Msg4
TESTASSERT(sched_ptr->dl_rlc_buffer_state(ue_ctxt.rnti, lcid, 50, 0) == SRSLTE_SUCCESS);
TESTASSERT(sched_ptr->dl_mac_buffer_state(ue_ctxt.rnti, (uint32_t)srslte::dl_sch_lcid::CON_RES_ID, 1) ==
SRSLTE_SUCCESS);
}
// Perform DRB config when Msg4 is received
if (cc_feedback.dl_pid >= 0 and cc_feedback.dl_ack) {
ue_ctxt.conres_rx = true;
TESTASSERT(ue_recfg(ue_ctxt.rnti, final_ue_cfg[ue_ctxt.rnti]) == SRSLTE_SUCCESS);
}
}
return SRSLTE_SUCCESS;
} }
void sched_sim_base::new_tti(srslte::tti_point tti_rx) void sched_sim_base::new_tti(srslte::tti_point tti_rx)
@ -391,7 +407,7 @@ void sched_sim_base::new_tti(srslte::tti_point tti_rx)
for (auto& ue : ue_db) { for (auto& ue : ue_db) {
ue_tti_events events; ue_tti_events events;
set_default_tti_events(ue.second.get_ctxt(), events); set_default_tti_events(ue.second.get_ctxt(), events);
before_sched(ue.second.get_ctxt(), events); set_external_tti_events(ue.second.get_ctxt(), events);
apply_tti_events(ue.second.get_ctxt(), events); apply_tti_events(ue.second.get_ctxt(), events);
} }
} }

8
srsenb/test/mac/sched_sim_ue.h
Unescape Escape View File

@ -73,7 +73,6 @@ class ue_sim
{ {
public: public:
ue_sim(uint16_t rnti_, ue_sim(uint16_t rnti_,
const std::vector<sched_interface::cell_cfg_t>& cell_params_,
const sched_interface::ue_cfg_t& ue_cfg_, const sched_interface::ue_cfg_t& ue_cfg_,
srslte::tti_point prach_tti_rx, srslte::tti_point prach_tti_rx,
uint32_t preamble_idx); uint32_t preamble_idx);
@ -92,7 +91,6 @@ private:
void update_ul_harqs(const sf_output_res_t& sf_out); void update_ul_harqs(const sf_output_res_t& sf_out);
srslte::log_ref log_h{"MAC"}; srslte::log_ref log_h{"MAC"};
const std::vector<sched_interface::cell_cfg_t>* cell_params;
sim_ue_ctxt_t ctxt; sim_ue_ctxt_t ctxt;
}; };
@ -138,11 +136,11 @@ public:
std::map<uint16_t, ue_sim>::iterator end() { return ue_db.end(); } std::map<uint16_t, ue_sim>::iterator end() { return ue_db.end(); }
// configurable by simulator concrete implementation // configurable by simulator concrete implementation
virtual void before_sched(const sim_ue_ctxt_t& ue_ctxt, ue_tti_events& pending_events) = 0; virtual void set_external_tti_events(const sim_ue_ctxt_t& ue_ctxt, ue_tti_events& pending_events) = 0;
private: private:
void set_default_tti_events(const sim_ue_ctxt_t& ue_ctxt, ue_tti_events& pending_events); int set_default_tti_events(const sim_ue_ctxt_t& ue_ctxt, ue_tti_events& pending_events);
void apply_tti_events(sim_ue_ctxt_t& ue_ctxt, const ue_tti_events& events); int apply_tti_events(sim_ue_ctxt_t& ue_ctxt, const ue_tti_events& events);
srslte::log_ref log_h{"MAC"}; srslte::log_ref log_h{"MAC"};
sched_interface* sched_ptr; sched_interface* sched_ptr;

51
srsenb/test/mac/sched_test_common.cc
Unescape Escape View File

@ -13,7 +13,6 @@
#include "sched_test_common.h" #include "sched_test_common.h"
#include "srsenb/hdr/stack/mac/sched.h" #include "srsenb/hdr/stack/mac/sched.h"
#include "srsenb/hdr/stack/upper/common_enb.h" #include "srsenb/hdr/stack/upper/common_enb.h"
#include "srslte/mac/pdu.h"
#include "sched_common_test_suite.h" #include "sched_common_test_suite.h"
#include "sched_ue_ded_test_suite.h" #include "sched_ue_ded_test_suite.h"
@ -47,7 +46,7 @@ std::default_random_engine& ::srsenb::get_rand_gen()
* User State Tester * User State Tester
***********************/ ***********************/
void sched_sim_random::before_sched(const sim_ue_ctxt_t& ue_ctxt, ue_tti_events& pending_events) void sched_sim_random::set_external_tti_events(const sim_ue_ctxt_t& ue_ctxt, ue_tti_events& pending_events)
{ {
const auto& sim_cfg = ue_sim_cfg_map.at(ue_ctxt.rnti); const auto& sim_cfg = ue_sim_cfg_map.at(ue_ctxt.rnti);
@ -81,16 +80,6 @@ void sched_sim_random::before_sched(const sim_ue_ctxt_t& ue_ctxt, ue_tti_events&
} }
} }
bool is_drb_cfg(const sched_interface::ue_cfg_t& ue_cfg)
{
for (uint32_t i = 2; i < ue_cfg.ue_bearers.size(); ++i) {
if (ue_cfg.ue_bearers[i].direction != sched_interface::ue_bearer_cfg_t::IDLE) {
return true;
}
}
return false;
}
/*********************** /***********************
* Sim Stats Storage * Sim Stats Storage
**********************/ **********************/
@ -233,54 +222,20 @@ int common_sched_tester::process_tti_events(const tti_ev& tti_ev)
const ue_sim* user = sched_sim->find_rnti(ue_ev.rnti); const ue_sim* user = sched_sim->find_rnti(ue_ev.rnti);
if (user != nullptr) {
const auto& ue_sim_ctxt = user->get_ctxt();
if (not ue_sim_ctxt.msg4_tti_rx.is_valid() and ue_sim_ctxt.msg3_tti_rx.is_valid() and
to_tx_ul(ue_sim_ctxt.msg3_tti_rx) <= tti_rx) {
// Msg3 has been received but Msg4 has not been yet transmitted
// Setup default UE config
TESTASSERT(reconf_user(ue_sim_ctxt.rnti, generate_setup_ue_cfg(sim_args0.default_ue_sim_cfg.ue_cfg)) ==
SRSLTE_SUCCESS);
// Schedule RRC Setup and ConRes CE
uint32_t pending_dl_new_data = ue_db[ue_ev.rnti].get_pending_dl_rlc_data();
if (pending_dl_new_data == 0) {
uint32_t lcid = RB_ID_SRB0; // Use SRB0 to schedule Msg4
dl_rlc_buffer_state(ue_ev.rnti, lcid, 50, 0);
dl_mac_buffer_state(ue_ev.rnti, (uint32_t)srslte::dl_sch_lcid::CON_RES_ID);
} else {
// Let SRB0 Msg4 get fully transmitted
}
}
}
// push UL SRs and DL packets // push UL SRs and DL packets
if (ue_ev.buffer_ev != nullptr) { if (ue_ev.buffer_ev != nullptr) {
CONDERROR(user == nullptr, "TESTER ERROR: Trying to schedule data for user that does not exist\n"); CONDERROR(user == nullptr, "TESTER ERROR: Trying to schedule data for user that does not exist\n");
const auto& ue_sim_ctxt = user->get_ctxt(); const auto& ue_sim_ctxt = user->get_ctxt();
if (ue_ev.buffer_ev->dl_data > 0 and ue_sim_ctxt.msg4_tti_rx.is_valid()) { if (ue_ev.buffer_ev->dl_data > 0 and ue_sim_ctxt.conres_rx) {
// If Msg4 has already been tx and there DL data to transmit // If Msg4 has already been tx and there DL data to transmit
uint32_t lcid = RB_ID_DRB1; uint32_t lcid = RB_ID_DRB1;
uint32_t pending_dl_new_data = ue_db[ue_ev.rnti].get_pending_dl_rlc_data(); uint32_t pending_dl_new_data = ue_db[ue_ev.rnti].get_pending_dl_rlc_data();
if (is_drb_cfg(sched_sim->find_rnti(ue_ev.rnti)->get_ctxt().ue_cfg) or pending_dl_new_data == 0) {
// If RRCSetup finished
if (not is_drb_cfg(sched_sim->find_rnti(ue_ev.rnti)->get_ctxt().ue_cfg)) {
reconf_user(ue_sim_ctxt.rnti, sim_args0.default_ue_sim_cfg.ue_cfg);
// setup lcid==drb1 bearer
sched::ue_bearer_cfg_t cfg = {};
cfg.direction = ue_bearer_cfg_t::BOTH;
cfg.group = 1;
TESTASSERT(sched_sim->bearer_cfg(ue_ev.rnti, lcid, cfg) == SRSLTE_SUCCESS);
}
// DRB is set. Update DL buffer // DRB is set. Update DL buffer
uint32_t tot_dl_data = pending_dl_new_data + ue_ev.buffer_ev->dl_data; // TODO: derive pending based on rx uint32_t tot_dl_data = pending_dl_new_data + ue_ev.buffer_ev->dl_data; // TODO: derive pending based on rx
dl_rlc_buffer_state(ue_ev.rnti, lcid, tot_dl_data, 0); // TODO: Check retx_queue dl_rlc_buffer_state(ue_ev.rnti, lcid, tot_dl_data, 0); // TODO: Check retx_queue
} else {
// Let SRB0 get emptied
}
} }
if (ue_ev.buffer_ev->sr_data > 0 and is_drb_cfg(sched_sim->find_rnti(ue_ev.rnti)->get_ctxt().ue_cfg)) { if (ue_ev.buffer_ev->sr_data > 0 and ue_sim_ctxt.conres_rx) {
uint32_t tot_ul_data = uint32_t tot_ul_data =
ue_db[ue_ev.rnti].get_pending_ul_new_data(to_tx_ul(tti_rx), -1) + ue_ev.buffer_ev->sr_data; ue_db[ue_ev.rnti].get_pending_ul_new_data(to_tx_ul(tti_rx), -1) + ue_ev.buffer_ev->sr_data;
uint32_t lcg = 1; uint32_t lcg = 1;

2
srsenb/test/mac/sched_test_common.h
Unescape Escape View File

@ -39,7 +39,7 @@ class sched_sim_random : public sched_sim_base
{ {
public: public:
using sched_sim_base::sched_sim_base; using sched_sim_base::sched_sim_base;
void before_sched(const sim_ue_ctxt_t& ue_ctxt, ue_tti_events& pending_events) override; void set_external_tti_events(const sim_ue_ctxt_t& ue_ctxt, ue_tti_events& pending_events) override;
std::map<uint16_t, ue_ctxt_test_cfg> ue_sim_cfg_map; std::map<uint16_t, ue_ctxt_test_cfg> ue_sim_cfg_map;
}; };

93
srsenb/test/mac/sched_test_rand.cc
Unescape Escape View File

@ -20,42 +20,18 @@
#include <srslte/srslte.h> #include <srslte/srslte.h>
#include <unistd.h> #include <unistd.h>
#include "srsenb/hdr/phy/phy.h"
#include "srsenb/hdr/stack/mac/mac.h"
#include "srslte/common/log_filter.h" #include "srslte/common/log_filter.h"
#include "srslte/interfaces/enb_interfaces.h" #include "srslte/interfaces/enb_interfaces.h"
#include "srslte/interfaces/sched_interface.h" #include "srslte/interfaces/sched_interface.h"
#include "srslte/phy/utils/debug.h" #include "srslte/phy/utils/debug.h"
#include "sched_common_test_suite.h" #include "sched_common_test_suite.h"
#include "sched_sim_ue.h"
#include "sched_test_common.h" #include "sched_test_common.h"
#include "sched_test_utils.h" #include "sched_test_utils.h"
#include "srslte/common/test_common.h" #include "srslte/common/test_common.h"
using srslte::tti_point; using srslte::tti_point;
/********************************************************
* Random Tester for Scheduler.
* Current Checks:
* - Check correct timing of PRACH, RAR, and Msg3
* - Check whether Msg4 contains ConRes
* - Check allocs of users that no longer exist
* - Check collisions in PDCCH, PUSCH, and PDSCH
* - Unexpected Msg3, RAR allocs or with wrong values
* - Users without data to Tx cannot be allocated in UL
* - Retxs always take precedence
* - Invalid BC SIB index or TBS
* - Harqs:
* - invalid pids scheduled
* - empty harqs scheduled
* - invalid harq TTI
* - consistent NCCE loc
* - invalid retx number
* - DL adaptive retx/new tx <=> PDCCH alloc
*******************************************************/
uint32_t const seed = std::chrono::system_clock::now().time_since_epoch().count(); uint32_t const seed = std::chrono::system_clock::now().time_since_epoch().count();
struct ue_stats_t { struct ue_stats_t {
@ -110,14 +86,6 @@ constexpr uint32_t CARRIER_IDX = 0;
// Designed for testing purposes // Designed for testing purposes
struct sched_tester : public srsenb::common_sched_tester { struct sched_tester : public srsenb::common_sched_tester {
struct tester_user_results { struct tester_user_results {
uint32_t dl_pending_data = 0;
uint32_t ul_pending_data = 0; ///< data pending for UL
bool has_dl_tx = false;
bool has_ul_tx = false; ///< has either tx or retx
bool has_ul_retx = false;
bool has_ul_newtx = false; ///< *no* retx, but has tx
bool ul_retx_got_delayed = false;
srsenb::dl_harq_proc dl_harqs[srsenb::cc_sched_ue::SCHED_MAX_HARQ_PROC];
srsenb::ul_harq_proc ul_harq; srsenb::ul_harq_proc ul_harq;
}; };
struct sched_tti_data { struct sched_tti_data {
@ -129,7 +97,6 @@ struct sched_tester : public srsenb::common_sched_tester {
sched_tti_data tti_data; sched_tti_data tti_data;
int rem_user(uint16_t rnti) override; int rem_user(uint16_t rnti) override;
int assert_no_empty_allocs();
int test_harqs(); int test_harqs();
private: private:
@ -160,33 +127,11 @@ void sched_tester::before_sched()
uint16_t rnti = it.first; uint16_t rnti = it.first;
srsenb::sched_ue* user = &it.second; srsenb::sched_ue* user = &it.second;
tester_user_results d; tester_user_results d;
srsenb::ul_harq_proc* hul = user->get_ul_harq(srsenb::to_tx_ul(tti_rx), CARRIER_IDX);
d.ul_pending_data = get_ul_buffer(rnti);
// user->get_pending_ul_new_data(tti_info.tti_params.tti_tx_ul) or hul->has_pending_retx(); //
// get_ul_buffer(rnti);
d.dl_pending_data = get_dl_buffer(rnti);
d.has_ul_retx = hul->has_pending_retx();
d.has_ul_tx = d.has_ul_retx or d.ul_pending_data > 0;
srsenb::dl_harq_proc* hdl = user->get_pending_dl_harq(srsenb::to_tx_dl(tti_rx), CARRIER_IDX);
d.has_dl_tx = (hdl != nullptr) or (it.second.get_empty_dl_harq(srsenb::to_tx_dl(tti_rx), CARRIER_IDX) != nullptr and
d.dl_pending_data > 0);
d.has_ul_newtx = not d.has_ul_retx and d.ul_pending_data > 0;
tti_data.ue_data.insert(std::make_pair(rnti, d)); tti_data.ue_data.insert(std::make_pair(rnti, d));
tti_data.total_ues.dl_pending_data += d.dl_pending_data;
tti_data.total_ues.ul_pending_data += d.ul_pending_data;
tti_data.total_ues.has_ul_tx |= d.has_ul_tx;
tti_data.total_ues.has_dl_tx |= d.has_dl_tx;
tti_data.total_ues.has_ul_newtx |= d.has_ul_newtx;
for (uint32_t i = 0; i < srsenb::cc_sched_ue::SCHED_MAX_HARQ_PROC; ++i) {
const srsenb::dl_harq_proc& h = user->get_dl_harq(i, CARRIER_IDX);
tti_data.ue_data[rnti].dl_harqs[i] = h;
}
// NOTE: ACK might have just cleared the harq for tti_info.tti_params.tti_tx_ul // NOTE: ACK might have just cleared the harq for tti_info.tti_params.tti_tx_ul
tti_data.ue_data[rnti].ul_harq = *user->get_ul_harq(srsenb::to_tx_ul(tti_rx), CARRIER_IDX); tti_data.ue_data[rnti].ul_harq = *user->get_ul_harq(srsenb::to_tx_ul(tti_rx), CARRIER_IDX);
} }
// TODO: Check whether pending pending_rar.rar_tti correspond to a prach_tti
} }
int sched_tester::process_results() int sched_tester::process_results()
@ -204,39 +149,12 @@ int sched_tester::process_results()
// UE dedicated tests // UE dedicated tests
TESTASSERT(run_ue_ded_tests_and_update_ctxt(sf_out) == SRSLTE_SUCCESS); TESTASSERT(run_ue_ded_tests_and_update_ctxt(sf_out) == SRSLTE_SUCCESS);
assert_no_empty_allocs();
test_harqs(); test_harqs();
update_ue_stats(); update_ue_stats();
return SRSLTE_SUCCESS; return SRSLTE_SUCCESS;
} }
int sched_tester::assert_no_empty_allocs()
{
// Test if allocations only take place for users with pending data or in RAR
for (auto& iter : tti_data.ue_data) {
uint16_t rnti = iter.first;
// srsenb::sched_ue* user = &ue_db[rnti];
if (not iter.second.has_ul_tx) {
for (uint32_t i = 0; i < tti_info.ul_sched_result[CARRIER_IDX].nof_dci_elems; ++i) {
auto& pusch = tti_info.ul_sched_result[CARRIER_IDX].pusch[i];
if (pusch.dci.rnti == rnti and pusch.needs_pdcch) {
// TODO: This test does not work for adaptive re-tx
TESTERROR("There was a user without data that got allocated in UL\n");
}
}
}
// srsenb::ul_harq_proc* hul = user->get_ul_harq(tti_info.tti_params.tti_tx_ul);
iter.second.ul_retx_got_delayed = iter.second.has_ul_retx and iter.second.ul_harq.is_empty(0);
tti_data.total_ues.ul_retx_got_delayed |= iter.second.ul_retx_got_delayed;
// Retxs cannot give space to newtx allocations
CONDERROR(tti_data.total_ues.ul_retx_got_delayed, "There was a retx that was erased for user rnti=0x%x\n", rnti);
}
return SRSLTE_SUCCESS;
}
int sched_tester::test_harqs() int sched_tester::test_harqs()
{ {
/* check consistency of DL harq procedures and allocations */ /* check consistency of DL harq procedures and allocations */
@ -356,6 +274,12 @@ sched_sim_events rand_sim_params(uint32_t nof_ttis)
sim_gen.sim_args.default_ue_sim_cfg.ue_cfg = generate_default_ue_cfg(); sim_gen.sim_args.default_ue_sim_cfg.ue_cfg = generate_default_ue_cfg();
sim_gen.sim_args.default_ue_sim_cfg.periodic_cqi = true; sim_gen.sim_args.default_ue_sim_cfg.periodic_cqi = true;
sim_gen.sim_args.default_ue_sim_cfg.ue_cfg.maxharq_tx = std::uniform_int_distribution<>{1, 5}(srsenb::get_rand_gen()); sim_gen.sim_args.default_ue_sim_cfg.ue_cfg.maxharq_tx = std::uniform_int_distribution<>{1, 5}(srsenb::get_rand_gen());
sim_gen.sim_args.default_ue_sim_cfg.prob_dl_ack_mask.resize(sim_gen.sim_args.default_ue_sim_cfg.ue_cfg.maxharq_tx,
0.5);
sim_gen.sim_args.default_ue_sim_cfg.prob_dl_ack_mask.back() = 1;
sim_gen.sim_args.default_ue_sim_cfg.prob_ul_ack_mask.resize(sim_gen.sim_args.default_ue_sim_cfg.ue_cfg.maxharq_tx,
0.5);
sim_gen.sim_args.default_ue_sim_cfg.prob_ul_ack_mask.back() = 1;
sim_gen.sim_args.default_ue_sim_cfg.ue_cfg.measgap_period = pick_random_uniform({0, 40, 80}); sim_gen.sim_args.default_ue_sim_cfg.ue_cfg.measgap_period = pick_random_uniform({0, 40, 80});
sim_gen.sim_args.default_ue_sim_cfg.ue_cfg.measgap_offset = std::uniform_int_distribution<uint32_t>{ sim_gen.sim_args.default_ue_sim_cfg.ue_cfg.measgap_offset = std::uniform_int_distribution<uint32_t>{
0, sim_gen.sim_args.default_ue_sim_cfg.ue_cfg.measgap_period}(srsenb::get_rand_gen()); 0, sim_gen.sim_args.default_ue_sim_cfg.ue_cfg.measgap_period}(srsenb::get_rand_gen());
@ -385,8 +309,7 @@ sched_sim_events rand_sim_params(uint32_t nof_ttis)
bool is_prach_tti = bool is_prach_tti =
srslte_prach_tti_opportunity_config_fdd(sim_gen.sim_args.cell_cfg[CARRIER_IDX].prach_config, tti, -1); srslte_prach_tti_opportunity_config_fdd(sim_gen.sim_args.cell_cfg[CARRIER_IDX].prach_config, tti, -1);
if (is_prach_tti and generator.current_users.size() < max_nof_users and srsenb::randf() < P_prach) { if (is_prach_tti and generator.current_users.size() < max_nof_users and srsenb::randf() < P_prach) {
generator.add_new_default_user(connection_dur_dist(srsenb::get_rand_gen()), generator.add_new_default_user(connection_dur_dist(srsenb::get_rand_gen()), sim_gen.sim_args.default_ue_sim_cfg);
sim_gen.sim_args.default_ue_sim_cfg.ue_cfg);
} }
generator.step_tti(); generator.step_tti();
} }

11
srsenb/test/mac/sched_test_utils.h
Unescape Escape View File

@ -63,7 +63,11 @@ inline srsenb::sched_interface::ue_cfg_t generate_default_ue_cfg()
ue_cfg.supported_cc_list[0].enb_cc_idx = 0; ue_cfg.supported_cc_list[0].enb_cc_idx = 0;
ue_cfg.supported_cc_list[0].active = true; ue_cfg.supported_cc_list[0].active = true;
ue_cfg.supported_cc_list[0].dl_cfg.tm = SRSLTE_TM1; ue_cfg.supported_cc_list[0].dl_cfg.tm = SRSLTE_TM1;
ue_cfg.ue_bearers[0].direction = srsenb::sched_interface::ue_bearer_cfg_t::BOTH; ue_cfg.ue_bearers[srsenb::RB_ID_SRB0].direction = srsenb::sched_interface::ue_bearer_cfg_t::BOTH;
ue_cfg.ue_bearers[srsenb::RB_ID_SRB1].direction = srsenb::sched_interface::ue_bearer_cfg_t::BOTH;
ue_cfg.ue_bearers[srsenb::RB_ID_SRB2].direction = srsenb::sched_interface::ue_bearer_cfg_t::BOTH;
ue_cfg.ue_bearers[srsenb::RB_ID_DRB1].direction = srsenb::sched_interface::ue_bearer_cfg_t::BOTH;
ue_cfg.ue_bearers[srsenb::RB_ID_DRB1].group = 1;
return ue_cfg; return ue_cfg;
} }
@ -201,19 +205,18 @@ struct sched_sim_event_generator {
return jump; return jump;
} }
tti_ev::user_cfg_ev* add_new_default_user(uint32_t duration, const srsenb::sched_interface::ue_cfg_t& ue_cfg) tti_ev::user_cfg_ev* add_new_default_user(uint32_t duration, const ue_ctxt_test_cfg& ue_sim_cfg)
{ {
std::vector<tti_ev::user_cfg_ev>& user_updates = tti_events[tti_counter].user_updates; std::vector<tti_ev::user_cfg_ev>& user_updates = tti_events[tti_counter].user_updates;
user_updates.emplace_back(); user_updates.emplace_back();
auto& user = user_updates.back(); auto& user = user_updates.back();
user.rnti = next_rnti++; user.rnti = next_rnti++;
// creates a user with one supported CC (PRACH stage) // creates a user with one supported CC (PRACH stage)
user.ue_sim_cfg.reset(new ue_ctxt_test_cfg{}); user.ue_sim_cfg.reset(new ue_ctxt_test_cfg{ue_sim_cfg});
auto& u = current_users[user.rnti]; auto& u = current_users[user.rnti];
u.rnti = user.rnti; u.rnti = user.rnti;
u.tti_start = tti_counter; u.tti_start = tti_counter;
u.tti_duration = duration; u.tti_duration = duration;
user.ue_sim_cfg->ue_cfg = ue_cfg;
return &user; return &user;
} }

Write Preview
Loading…
Cancel
Save