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@ -48,7 +48,6 @@ int mac_nr::init(const mac_nr_args_t& args_,
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{
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{
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args = args_;
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args = args_;
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sched.reset(new sched_nr{args.sched_cfg});
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phy = phy_;
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phy = phy_;
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stack = stack_;
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stack = stack_;
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rlc = rlc_;
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rlc = rlc_;
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@ -82,7 +81,7 @@ void mac_nr::get_metrics(srsenb::mac_metrics_t& metrics)
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srsran::rwlock_read_guard lock(rwlock);
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srsran::rwlock_read_guard lock(rwlock);
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metrics.ues.reserve(ue_db.size());
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metrics.ues.reserve(ue_db.size());
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for (auto& u : ue_db) {
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for (auto& u : ue_db) {
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if (not sched->ue_exists(u.first)) {
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if (not sched.ue_exists(u.first)) {
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continue;
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continue;
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}
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}
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metrics.ues.emplace_back();
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metrics.ues.emplace_back();
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@ -98,7 +97,7 @@ void mac_nr::get_metrics(srsenb::mac_metrics_t& metrics)
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int mac_nr::cell_cfg(const std::vector<srsenb::sched_nr_interface::cell_cfg_t>& nr_cells)
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int mac_nr::cell_cfg(const std::vector<srsenb::sched_nr_interface::cell_cfg_t>& nr_cells)
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{
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{
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cell_config = nr_cells;
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cell_config = nr_cells;
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sched->cell_cfg(nr_cells);
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sched.config(args.sched_cfg, nr_cells);
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detected_rachs.resize(nr_cells.size());
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detected_rachs.resize(nr_cells.size());
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// read SIBs from RRC (SIB1 for now only)
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// read SIBs from RRC (SIB1 for now only)
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@ -127,7 +126,7 @@ int mac_nr::cell_cfg(const std::vector<srsenb::sched_nr_interface::cell_cfg_t>&
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int mac_nr::ue_cfg(uint16_t rnti, const sched_nr_interface::ue_cfg_t& ue_cfg)
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int mac_nr::ue_cfg(uint16_t rnti, const sched_nr_interface::ue_cfg_t& ue_cfg)
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{
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{
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sched->ue_cfg(rnti, ue_cfg);
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sched.ue_cfg(rnti, ue_cfg);
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return SRSRAN_SUCCESS;
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return SRSRAN_SUCCESS;
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}
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}
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@ -148,7 +147,7 @@ uint16_t mac_nr::reserve_rnti(uint32_t enb_cc_idx)
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srsenb::sched_nr_interface::ue_cfg_t ue_cfg = srsenb::get_default_ue_cfg(1);
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srsenb::sched_nr_interface::ue_cfg_t ue_cfg = srsenb::get_default_ue_cfg(1);
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ue_cfg.fixed_dl_mcs = args.fixed_dl_mcs;
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ue_cfg.fixed_dl_mcs = args.fixed_dl_mcs;
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ue_cfg.fixed_ul_mcs = args.fixed_ul_mcs;
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ue_cfg.fixed_ul_mcs = args.fixed_ul_mcs;
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sched->ue_cfg(rnti, ue_cfg);
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sched.ue_cfg(rnti, ue_cfg);
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return rnti;
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return rnti;
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}
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}
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@ -174,7 +173,7 @@ void mac_nr::rach_detected(const rach_info_t& rach_info)
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rar_info.ta_cmd = rach_info.time_adv;
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rar_info.ta_cmd = rach_info.time_adv;
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rar_info.prach_slot = slot_point{NUMEROLOGY_IDX, rach_info.slot_index};
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rar_info.prach_slot = slot_point{NUMEROLOGY_IDX, rach_info.slot_index};
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// TODO: fill remaining fields as required
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// TODO: fill remaining fields as required
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sched->dl_rach_info(enb_cc_idx, rar_info);
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sched.dl_rach_info(enb_cc_idx, rar_info);
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rrc->add_user(rnti);
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rrc->add_user(rnti);
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logger.info("RACH: slot=%d, cc=%d, preamble=%d, offset=%d, temp_crnti=0x%x",
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logger.info("RACH: slot=%d, cc=%d, preamble=%d, offset=%d, temp_crnti=0x%x",
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@ -210,8 +209,7 @@ uint16_t mac_nr::alloc_ue(uint32_t enb_cc_idx)
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}
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}
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// Allocate and initialize UE object
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// Allocate and initialize UE object
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std::unique_ptr<ue_nr> ue_ptr =
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std::unique_ptr<ue_nr> ue_ptr = std::unique_ptr<ue_nr>(new ue_nr(rnti, enb_cc_idx, &sched, rrc, rlc, phy, logger));
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std::unique_ptr<ue_nr>(new ue_nr(rnti, enb_cc_idx, sched.get(), rrc, rlc, phy, logger));
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// Add UE to rnti map
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// Add UE to rnti map
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srsran::rwlock_write_guard rw_lock(rwlock);
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srsran::rwlock_write_guard rw_lock(rwlock);
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@ -285,7 +283,7 @@ int mac_nr::get_dl_sched(const srsran_slot_cfg_t& slot_cfg, dl_sched_t& dl_sched
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}
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}
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sched_nr_interface::dl_sched_res_t dl_res;
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sched_nr_interface::dl_sched_res_t dl_res;
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int ret = sched->get_dl_sched(pdsch_slot, 0, dl_res);
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int ret = sched.get_dl_sched(pdsch_slot, 0, dl_res);
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if (ret != SRSRAN_SUCCESS) {
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if (ret != SRSRAN_SUCCESS) {
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return ret;
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return ret;
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}
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}
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@ -327,7 +325,7 @@ int mac_nr::get_ul_sched(const srsran_slot_cfg_t& slot_cfg, ul_sched_t& ul_sched
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pusch_slot++;
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pusch_slot++;
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}
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}
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return sched->get_ul_sched(pusch_slot, 0, ul_sched);
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return sched.get_ul_sched(pusch_slot, 0, ul_sched);
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}
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}
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int mac_nr::pucch_info(const srsran_slot_cfg_t& slot_cfg, const mac_interface_phy_nr::pucch_info_t& pucch_info)
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int mac_nr::pucch_info(const srsran_slot_cfg_t& slot_cfg, const mac_interface_phy_nr::pucch_info_t& pucch_info)
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@ -345,7 +343,7 @@ bool mac_nr::handle_uci_data(const uint16_t rnti, const srsran_uci_cfg_nr_t& cfg
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for (uint32_t i = 0; i < cfg_.ack.count; i++) {
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for (uint32_t i = 0; i < cfg_.ack.count; i++) {
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const srsran_harq_ack_bit_t* ack_bit = &cfg_.ack.bits[i];
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const srsran_harq_ack_bit_t* ack_bit = &cfg_.ack.bits[i];
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bool is_ok = (value.ack[i] == 1) and value.valid;
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bool is_ok = (value.ack[i] == 1) and value.valid;
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sched->dl_ack_info(rnti, 0, ack_bit->pid, 0, is_ok);
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sched.dl_ack_info(rnti, 0, ack_bit->pid, 0, is_ok);
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}
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}
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// Process SR
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// Process SR
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@ -365,7 +363,7 @@ int mac_nr::pusch_info(const srsran_slot_cfg_t& slot_cfg, mac_interface_phy_nr::
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return SRSRAN_ERROR;
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return SRSRAN_ERROR;
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}
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}
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sched->ul_crc_info(rnti, 0, pusch_info.pid, pusch_info.pusch_data.tb[0].crc);
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sched.ul_crc_info(rnti, 0, pusch_info.pid, pusch_info.pusch_data.tb[0].crc);
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// process only PDUs with CRC=OK
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// process only PDUs with CRC=OK
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if (pusch_info.pusch_data.tb[0].crc) {
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if (pusch_info.pusch_data.tb[0].crc) {
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