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@ -132,14 +132,12 @@ bool slot_worker::work_ul()
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}
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}
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// Decode PUCCH
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// Decode PUCCH
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for (uint32_t i = 0; i < ul_sched.uci_count; i++) {
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for (stack_interface_phy_nr::pucch_t& pucch : ul_sched.pucch) {
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const stack_interface_phy_nr::uci_t& uci = ul_sched.uci[i];
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// ...
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// ...
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}
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}
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// Decode PUSCH
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// Decode PUSCH
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for (uint32_t i = 0; i < ul_sched.pusch_count; i++) {
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for (stack_interface_phy_nr::pusch_t& pusch : ul_sched.pusch) {
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const stack_interface_phy_nr::pusch_t& pusch = ul_sched.pusch[i];
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// ...
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// ...
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}
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}
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@ -148,17 +146,20 @@ bool slot_worker::work_ul()
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bool slot_worker::work_dl()
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bool slot_worker::work_dl()
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{
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{
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// Retrieve Scheduling for the current processing DL slot
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stack_interface_phy_nr::dl_sched_t dl_sched = {};
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stack_interface_phy_nr::dl_sched_t dl_sched = {};
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if (stack.get_dl_sched(ul_slot_cfg, dl_sched) < SRSRAN_SUCCESS) {
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if (stack.get_dl_sched(ul_slot_cfg, dl_sched) < SRSRAN_SUCCESS) {
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logger.error("Error retrieving DL scheduling");
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logger.error("Error retrieving DL scheduling");
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return false;
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return false;
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}
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}
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// Encode PDCCH for DL transmissions
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if (srsran_enb_dl_nr_base_zero(&gnb_dl) < SRSRAN_SUCCESS) {
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for (uint32_t i = 0; i < dl_sched.pdcch_dl_count; i++) {
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logger.error("Error zeroeing RE grid");
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// Select PDCCH from scheduler result
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return false;
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const stack_interface_phy_nr::pdcch_dl_t& pdcch = dl_sched.pdcch_dl[i];
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}
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// Encode PDCCH for DL transmissions
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for (const stack_interface_phy_nr::pdcch_dl_t& pdcch : dl_sched.pdcch_dl) {
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// Set PDCCH configuration, including DCI dedicated
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// Set PDCCH configuration, including DCI dedicated
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if (srsran_enb_dl_nr_set_pdcch_config(&gnb_dl, &pdcch_cfg, &pdcch.dci_cfg) < SRSRAN_SUCCESS) {
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if (srsran_enb_dl_nr_set_pdcch_config(&gnb_dl, &pdcch_cfg, &pdcch.dci_cfg) < SRSRAN_SUCCESS) {
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logger.error("PDCCH: Error setting DL configuration");
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logger.error("PDCCH: Error setting DL configuration");
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@ -180,10 +181,7 @@ bool slot_worker::work_dl()
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}
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}
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// Encode PDCCH for UL transmissions
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// Encode PDCCH for UL transmissions
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for (uint32_t i = 0; i < dl_sched.pdcch_ul_count; i++) {
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for (const stack_interface_phy_nr::pdcch_ul_t& pdcch : dl_sched.pdcch_ul) {
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// Select PDCCH from scheduler result
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const stack_interface_phy_nr::pdcch_ul_t& pdcch = dl_sched.pdcch_ul[i];
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// Set PDCCH configuration, including DCI dedicated
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// Set PDCCH configuration, including DCI dedicated
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if (srsran_enb_dl_nr_set_pdcch_config(&gnb_dl, &pdcch_cfg, &pdcch.dci_cfg) < SRSRAN_SUCCESS) {
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if (srsran_enb_dl_nr_set_pdcch_config(&gnb_dl, &pdcch_cfg, &pdcch.dci_cfg) < SRSRAN_SUCCESS) {
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logger.error("PDCCH: Error setting DL configuration");
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logger.error("PDCCH: Error setting DL configuration");
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@ -205,10 +203,7 @@ bool slot_worker::work_dl()
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}
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}
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// Encode PDSCH
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// Encode PDSCH
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for (uint32_t i = 0; i < dl_sched.pdsch_count; i++) {
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for (stack_interface_phy_nr::pdsch_t& pdsch : dl_sched.pdsch) {
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// Select PDSCH from scheduler result
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stack_interface_phy_nr::pdsch_t& pdsch = dl_sched.pdsch[i];
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// Put PDSCH message
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// Put PDSCH message
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if (srsran_enb_dl_nr_pdsch_put(&gnb_dl, &dl_slot_cfg, &pdsch.sch, pdsch.data.data()) < SRSRAN_SUCCESS) {
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if (srsran_enb_dl_nr_pdsch_put(&gnb_dl, &dl_slot_cfg, &pdsch.sch, pdsch.data.data()) < SRSRAN_SUCCESS) {
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logger.error("PDSCH: Error putting DL message");
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logger.error("PDSCH: Error putting DL message");
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@ -223,16 +218,26 @@ bool slot_worker::work_dl()
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}
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}
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}
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}
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// Put NZP-CSI-RS
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for (srsran_csi_rs_nzp_resource_t& pdsch : dl_sched.nzp_csi_rs) {
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// ...
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}
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// Generate baseband signal
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// Generate baseband signal
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srsran_enb_dl_nr_gen_signal(&gnb_dl);
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srsran_enb_dl_nr_gen_signal(&gnb_dl);
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// Add SSB to the baseband signal
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for (const stack_interface_phy_nr::ssb_t& ssb : dl_sched.ssb) {
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// ...
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}
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return true;
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return true;
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}
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}
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void slot_worker::work_imp()
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void slot_worker::work_imp()
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{
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{
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// Inform Scheduler about new slot
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// Inform Scheduler about new slot
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stack.sf_indication(dl_slot_cfg.idx);
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stack.slot_indication(dl_slot_cfg);
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// Get Transmission buffers
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// Get Transmission buffers
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srsran::rf_buffer_t tx_rf_buffer = {};
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srsran::rf_buffer_t tx_rf_buffer = {};
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