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@ -22,7 +22,7 @@ namespace sched_nr_impl {
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////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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template <typename DciDlOrUl>
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void fill_dci_common(const slot_ue& ue, const bwp_params_t& bwp_cfg, DciDlOrUl& dci)
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void fill_dci_common(const slot_ue& ue, const bwp_params_t& bwp_cfg, const srsran_dci_ctx_t& dci_ctx, DciDlOrUl& dci)
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{
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const static uint32_t rv_idx[4] = {0, 2, 3, 1};
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@ -40,9 +40,16 @@ void fill_dci_common(const slot_ue& ue, const bwp_params_t& bwp_cfg, DciDlOrUl&
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const prb_grant& grant = h->prbs();
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if (grant.is_alloc_type0()) {
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dci.freq_domain_assigment = grant.rbgs().to_uint64();
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if (SRSRAN_SEARCH_SPACE_IS_COMMON(dci_ctx.ss_type) and dci_ctx.coreset_start_rb > 0) {
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dci.freq_domain_assigment =
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(dci.freq_domain_assigment << dci_ctx.coreset_start_rb) & ((1U << grant.rbgs().size()) - 1);
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}
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} else {
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dci.freq_domain_assigment =
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srsran_ra_nr_type1_riv(bwp_cfg.cfg.rb_width, grant.prbs().start(), grant.prbs().length());
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uint32_t rb_start = grant.prbs().start();
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if (SRSRAN_SEARCH_SPACE_IS_COMMON(dci_ctx.ss_type)) {
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rb_start -= dci_ctx.coreset_start_rb;
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}
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dci.freq_domain_assigment = srsran_ra_nr_type1_riv(bwp_cfg.cfg.rb_width, rb_start, grant.prbs().length());
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}
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dci.time_domain_assigment = 0;
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}
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@ -51,13 +58,14 @@ bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp
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{
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uint32_t cs_id = bwp_cfg.cfg.pdcch.ra_search_space.coreset_id;
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dci.mcs = 5;
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dci.ctx.format = srsran_dci_format_nr_1_0;
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dci.ctx.ss_type = srsran_search_space_type_common_1;
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dci.ctx.rnti_type = srsran_rnti_type_ra;
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dci.ctx.rnti = ra_rnti;
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dci.ctx.coreset_id = cs_id;
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dci.ctx.coreset_start_rb = bwp_cfg.cfg.pdcch.coreset[cs_id].offset_rb;
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dci.ctx.coreset_start_rb = srsran_coreset_start_rb(&bwp_cfg.cfg.pdcch.coreset[cs_id]);
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dci.mcs = 5;
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if (bwp_cfg.cfg.pdcch.coreset_present[0] and cs_id == 0) {
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dci.coreset0_bw = srsran_coreset_get_bw(&bwp_cfg.cfg.pdcch.coreset[cs_id]);
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}
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@ -73,7 +81,6 @@ bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp
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bool fill_dci_msg3(const slot_ue& ue, const bwp_params_t& bwp_cfg, srsran_dci_ul_nr_t& msg3_dci)
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{
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fill_dci_common(ue, bwp_cfg, msg3_dci);
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msg3_dci.ctx.coreset_id = ue->phy().pdcch.ra_search_space.coreset_id;
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msg3_dci.ctx.rnti_type = srsran_rnti_type_tc;
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msg3_dci.ctx.rnti = ue->rnti;
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@ -83,6 +90,7 @@ bool fill_dci_msg3(const slot_ue& ue, const bwp_params_t& bwp_cfg, srsran_dci_ul
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} else {
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msg3_dci.ctx.format = srsran_dci_format_nr_0_0;
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}
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fill_dci_common(ue, bwp_cfg, msg3_dci.ctx, msg3_dci);
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return true;
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}
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@ -98,7 +106,7 @@ void fill_dl_dci_ue_fields(const slot_ue& ue,
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bool ret = ue->phy().get_dci_ctx_pdsch_rnti_c(ss_id, dci_pos, ue->rnti, dci.ctx);
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srsran_assert(ret, "Invalid DL DCI format");
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fill_dci_common(ue, bwp_cfg, dci);
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fill_dci_common(ue, bwp_cfg, dci.ctx, dci);
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if (dci.ctx.format == srsran_dci_format_nr_1_0) {
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dci.harq_feedback = (ue.uci_slot - ue.pdsch_slot) - 1;
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} else {
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@ -115,7 +123,7 @@ void fill_ul_dci_ue_fields(const slot_ue& ue,
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bool ret = ue->phy().get_dci_ctx_pusch_rnti_c(ss_id, dci_pos, ue->rnti, dci.ctx);
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srsran_assert(ret, "Invalid DL DCI format");
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fill_dci_common(ue, bwp_cfg, dci);
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fill_dci_common(ue, bwp_cfg, dci.ctx, dci);
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}
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void log_sched_slot_ues(srslog::basic_logger& logger, slot_point pdcch_slot, uint32_t cc, const slot_ue_map_t& slot_ues)
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