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Added 256QAM modulation tables to scheduler

Browse Source
master
Xavier Arteaga 5 years ago committed by Xavier Arteaga
parent a4225b189b
commit 5b7493cab5
12 changed files with 120 additions and 111 deletions
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17
lib/include/srslte/asn1/rrc_asn1_utils.h
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@ -125,22 +125,7 @@ void set_phy_cfg_t_enable_64qam(phy_cfg_t* cfg, const bool enabled);
/***************************
* EUTRA UE Capabilities
**************************/
typedef struct {
uint8_t release = 8;
uint8_t category = 4;
uint8_t category_dl = 0;
uint8_t category_ul = 0;
bool support_dl_256qam = false;
bool support_ul_64qam = false;
} rrc_ue_eutra_cap_t;
/**
* Flattens the UE EUTRA capabilities from the ASN.1 message decoder
*
* @param ue_cap Flat UE EUTRA capabilities
* @param eutra_cap_s ASN.1 structure
*/
void set_rrc_ue_eutra_cap_t(rrc_ue_eutra_cap_t& ue_cap, const asn1::rrc::ue_eutra_cap_s eutra_cap_s);
void set_rrc_ue_capabilities_t(rrc_ue_capabilities_t& ue_cap, const asn1::rrc::ue_eutra_cap_s eutra_cap_s);
// mbms
mbms_notif_cfg_t make_mbms_notif_cfg(const asn1::rrc::mbms_notif_cfg_r9_s& asn1_type);

12
lib/include/srslte/interfaces/rrc_interface_types.h
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@ -339,6 +339,18 @@ inline std::string to_string(const barring_t& b)
return enum_to_text(options, 5u, (uint32_t)b);
}
/**
* Flat UE capabilities
*/
typedef struct {
uint8_t release = 8;
uint8_t category = 4;
uint8_t category_dl = 0;
uint8_t category_ul = 0;
bool support_dl_256qam = false;
bool support_ul_64qam = false;
} rrc_ue_capabilities_t;
} // namespace srslte
#endif // SRSLTE_RRC_INTERFACE_TYPES_H

1
lib/include/srslte/interfaces/sched_interface.h
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@ -143,6 +143,7 @@ public:
std::array<ue_bearer_cfg_t, MAX_LC> ue_bearers = {};
std::vector<cc_cfg_t> supported_cc_list; ///< list of UE supported CCs. First index for PCell
ant_info_ded_t dl_ant_info;
bool use_tbs_index_alt = false;
};
typedef struct {

8
lib/include/srslte/phy/phch/ra.h
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@ -92,15 +92,13 @@ SRSLTE_API uint32_t srslte_ra_type2_to_riv(uint32_t L_crb, uint32_t RB_start, ui
SRSLTE_API void
srslte_ra_type2_from_riv(uint32_t riv, uint32_t* L_crb, uint32_t* RB_start, uint32_t nof_prb, uint32_t nof_vrb);
SRSLTE_API int srslte_ra_tbs_idx_from_mcs(uint32_t mcs, bool is_ul);
SRSLTE_API int srslte_ra_tbs_idx_from_mcs(uint32_t mcs, bool use_tbs_index_alt, bool is_ul);
SRSLTE_API srslte_mod_t srslte_ra_dl_mod_from_mcs(uint32_t mcs);
SRSLTE_API srslte_mod_t srslte_ra_dl_mod_from_mcs2(uint32_t mcs);
SRSLTE_API srslte_mod_t srslte_ra_dl_mod_from_mcs(uint32_t mcs, bool use_tbs_index_alt);
SRSLTE_API srslte_mod_t srslte_ra_ul_mod_from_mcs(uint32_t mcs);
SRSLTE_API int srslte_ra_mcs_from_tbs_idx(uint32_t tbs_idx, bool is_ul);
SRSLTE_API int srslte_ra_mcs_from_tbs_idx(uint32_t tbs_idx, bool use_tbs_index_alt, bool is_ul);
SRSLTE_API int srslte_ra_tbs_from_idx(uint32_t tbs_idx, uint32_t n_prb);

12
lib/src/asn1/rrc_asn1_utils.cc
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@ -799,14 +799,14 @@ void set_phy_cfg_t_scell_config(phy_cfg_t* cfg, const asn1::rrc::scell_to_add_mo
*/
template <class T>
static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_eutra_cap_t& ue_cap, const T& ue_eutra_cap)
static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_capabilities_t& ue_cap, const T& ue_eutra_cap)
{
if (ue_eutra_cap.non_crit_ext_present) {
set_rrc_ue_eutra_cap_t_gen(ue_cap, ue_eutra_cap.non_crit_ext);
}
}
static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_eutra_cap_t& ue_cap, const asn1::rrc::ue_eutra_cap_s& ue_eutra_cap)
static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_capabilities_t& ue_cap, const asn1::rrc::ue_eutra_cap_s& ue_eutra_cap)
{
ue_cap.release = ue_eutra_cap.access_stratum_release.to_number();
ue_cap.category = ue_eutra_cap.ue_category;
@ -816,7 +816,7 @@ static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_eutra_cap_t& ue_cap, const asn1::r
}
}
static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_eutra_cap_t& ue_cap,
static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_capabilities_t& ue_cap,
const asn1::rrc::ue_eutra_cap_v1020_ies_s& ue_eutra_cap)
{
if (ue_eutra_cap.ue_category_v1020_present) {
@ -828,7 +828,7 @@ static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_eutra_cap_t&
}
}
static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_eutra_cap_t& ue_cap,
static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_capabilities_t& ue_cap,
const asn1::rrc::ue_eutra_cap_v1250_ies_s& ue_eutra_cap)
{
if (ue_eutra_cap.ue_category_dl_r12_present) {
@ -856,13 +856,13 @@ static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_eutra_cap_t&
}
}
static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_eutra_cap_t& ue_cap,
static void set_rrc_ue_eutra_cap_t_gen(rrc_ue_capabilities_t& ue_cap,
const asn1::rrc::ue_eutra_cap_v1530_ies_s& ue_eutra_cap)
{
; // Do nothing
}
void set_rrc_ue_eutra_cap_t(rrc_ue_eutra_cap_t& ue_cap, const asn1::rrc::ue_eutra_cap_s eutra_cap_s)
void set_rrc_ue_capabilities_t(rrc_ue_capabilities_t& ue_cap, const asn1::rrc::ue_eutra_cap_s eutra_cap_s)
{
set_rrc_ue_eutra_cap_t_gen(ue_cap, eutra_cap_s);
}

38
lib/src/phy/phch/ra.c
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@ -123,9 +123,11 @@ uint32_t srslte_ra_type2_n_vrb_dl(uint32_t nof_prb, bool ngap_is_1)
}
/* Modulation and TBS index table for PDSCH from 3GPP TS 36.213 v10.3.0 table 7.1.7.1-1 */
static int srslte_ra_dl_tbs_idx_from_mcs(uint32_t mcs)
static int srslte_ra_dl_tbs_idx_from_mcs(uint32_t mcs, bool use_tbs_index_alt)
{
if (mcs < 29) {
if (use_tbs_index_alt && mcs < 28) {
return dl_mcs_tbs_idx_table2[mcs];
} else if (!use_tbs_index_alt && mcs < 29) {
return dl_mcs_tbs_idx_table[mcs];
} else {
return SRSLTE_ERROR;
@ -141,13 +143,24 @@ static int srslte_ra_ul_tbs_idx_from_mcs(uint32_t mcs)
}
}
int srslte_ra_tbs_idx_from_mcs(uint32_t mcs, bool is_ul)
int srslte_ra_tbs_idx_from_mcs(uint32_t mcs, bool use_tbs_index_alt, bool is_ul)
{
return (is_ul) ? srslte_ra_ul_tbs_idx_from_mcs(mcs) : srslte_ra_dl_tbs_idx_from_mcs(mcs);
return (is_ul) ? srslte_ra_ul_tbs_idx_from_mcs(mcs) : srslte_ra_dl_tbs_idx_from_mcs(mcs, use_tbs_index_alt);
}
srslte_mod_t srslte_ra_dl_mod_from_mcs(uint32_t mcs)
srslte_mod_t srslte_ra_dl_mod_from_mcs(uint32_t mcs, bool use_tbs_index_alt)
{
if (use_tbs_index_alt) {
if (mcs < 5 || mcs == 28) {
return SRSLTE_MOD_QPSK;
} else if (mcs < 11 || mcs == 29) {
return SRSLTE_MOD_16QAM;
} else if (mcs < 20 || mcs == 30) {
return SRSLTE_MOD_64QAM;
} else {
return SRSLTE_MOD_256QAM;
}
} else {
if (mcs <= 10 || mcs == 29) {
return SRSLTE_MOD_QPSK;
} else if (mcs <= 17 || mcs == 30) {
@ -155,6 +168,7 @@ srslte_mod_t srslte_ra_dl_mod_from_mcs(uint32_t mcs)
} else {
return SRSLTE_MOD_64QAM;
}
}
}
srslte_mod_t srslte_ra_ul_mod_from_mcs(uint32_t mcs)
@ -171,13 +185,21 @@ srslte_mod_t srslte_ra_ul_mod_from_mcs(uint32_t mcs)
}
}
static int srslte_ra_dl_mcs_from_tbs_idx(uint32_t tbs_idx)
static int srslte_ra_dl_mcs_from_tbs_idx(uint32_t tbs_idx, bool use_tbs_index_alt)
{
if (use_tbs_index_alt) {
for (int i = 0; i < 28; i++) {
if (tbs_idx == dl_mcs_tbs_idx_table2[i]) {
return i;
}
}
} else {
for (int i = 0; i < 29; i++) {
if (tbs_idx == dl_mcs_tbs_idx_table[i]) {
return i;
}
}
}
return SRSLTE_ERROR;
}
@ -191,9 +213,9 @@ static int srslte_ra_ul_mcs_from_tbs_idx(uint32_t tbs_idx)
return SRSLTE_ERROR;
}
int srslte_ra_mcs_from_tbs_idx(uint32_t tbs_idx, bool is_ul)
int srslte_ra_mcs_from_tbs_idx(uint32_t tbs_idx, bool use_tbs_index_alt, bool is_ul)
{
return is_ul ? srslte_ra_ul_mcs_from_tbs_idx(tbs_idx) : srslte_ra_dl_mcs_from_tbs_idx(tbs_idx);
return is_ul ? srslte_ra_ul_mcs_from_tbs_idx(tbs_idx) : srslte_ra_dl_mcs_from_tbs_idx(tbs_idx, use_tbs_index_alt);
}
/* Table 7.1.7.2.1-1: Transport block size table on 36.213 */

47
lib/src/phy/phch/ra_dl.c
Unescape Escape View File

@ -26,7 +26,6 @@
#include "srslte/phy/utils/debug.h"
#include "srslte/phy/utils/vector.h"
#include "srslte/srslte.h"
#include "tbs_tables.h"
#include <math.h>
#include <stdarg.h>
#include <stdio.h>
@ -321,50 +320,16 @@ int srslte_ra_dl_grant_to_grant_prb_allocation(const srslte_dci_dl_t* dci,
int srslte_dl_fill_ra_mcs(srslte_ra_tb_t* tb, int last_tbs, uint32_t nprb, bool pdsch_use_tbs_index_alt)
{
int i_tbs = 0;
if (!pdsch_use_tbs_index_alt) {
// Implements 3GPP 36.211 Table 3.56.35-431
if (tb->mcs_idx < 10) {
tb->mod = SRSLTE_MOD_QPSK;
i_tbs = tb->mcs_idx;
} else if (tb->mcs_idx < 17) {
tb->mod = SRSLTE_MOD_16QAM;
i_tbs = tb->mcs_idx - 1;
} else if (tb->mcs_idx < 29) {
tb->mod = SRSLTE_MOD_64QAM;
i_tbs = tb->mcs_idx - 2;
} else if (tb->mcs_idx == 29) {
tb->mod = SRSLTE_MOD_QPSK;
i_tbs = -1;
} else if (tb->mcs_idx == 30) {
tb->mod = SRSLTE_MOD_16QAM;
i_tbs = -1;
} else if (tb->mcs_idx == 31) {
tb->mod = SRSLTE_MOD_64QAM;
i_tbs = -1;
}
} else {
if (tb->mcs_idx < 28) {
i_tbs = dl_mcs_tbs_idx_table2[tb->mcs_idx];
} else {
i_tbs = SRSLTE_ERROR;
}
if (tb->mcs_idx < 5 || tb->mcs_idx == 28) {
tb->mod = SRSLTE_MOD_QPSK;
} else if (tb->mcs_idx < 11 || tb->mcs_idx == 29) {
tb->mod = SRSLTE_MOD_16QAM;
} else if (tb->mcs_idx < 20 || tb->mcs_idx == 30) {
tb->mod = SRSLTE_MOD_64QAM;
} else {
tb->mod = SRSLTE_MOD_256QAM;
}
}
// Get modulation
tb->mod = srslte_ra_dl_mod_from_mcs(tb->mcs_idx, pdsch_use_tbs_index_alt);
// Get Transport block size index
int i_tbs = srslte_ra_tbs_idx_from_mcs(tb->mcs_idx, pdsch_use_tbs_index_alt, false);
// If i_tbs = -1, TBS is determined from the latest PDCCH for this TB (7.1.7.2 36.213)
int tbs = 0;
if (i_tbs >= 0) {
tbs = srslte_ra_tbs_from_idx(i_tbs, nprb);
tbs = srslte_ra_tbs_from_idx((uint32_t)i_tbs, nprb);
tb->tbs = tbs;
} else {
tb->tbs = last_tbs;

3
srsenb/hdr/stack/mac/scheduler_ue.h
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@ -64,7 +64,7 @@ struct sched_ue_carrier {
uint32_t ul_cqi_tti = 0;
bool dl_cqi_rx = false;
int max_mcs_dl = 28, max_mcs_ul = 28;
uint32_t max_mcs_dl = 28, max_mcs_dl_alt = 27, max_mcs_ul = 28;
uint32_t max_aggr_level = 3;
int fixed_mcs_ul = 0, fixed_mcs_dl = 0;
@ -187,6 +187,7 @@ public:
uint32_t nof_re,
uint32_t max_mcs,
uint32_t max_Qm,
bool use_tbs_index_alt,
bool is_ul,
uint32_t* mcs);

1
srsenb/hdr/stack/rrc/rrc.h
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@ -306,6 +306,7 @@ private:
asn1::s1ap::ue_security_cap_s security_capabilities;
bool eutra_capabilities_unpacked = false;
asn1::rrc::ue_eutra_cap_s eutra_capabilities;
srslte::rrc_ue_capabilities_t ue_capabilities;
typedef struct {
uint8_t id;

3
srsenb/src/phy/cc_worker.cc
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@ -505,7 +505,8 @@ int cc_worker::encode_pdsch(stack_interface_phy_lte::dl_sched_grant_t* grants, u
srslte_dl_cfg_t dl_cfg = phy->ue_db.get_config(rnti, cc_idx).dl_cfg;
// Compute DL grant
if (srslte_ra_dl_dci_to_grant(&enb_dl.cell, &dl_sf, dl_cfg.tm, false, &grants[i].dci, &dl_cfg.pdsch.grant)) {
if (srslte_ra_dl_dci_to_grant(
&enb_dl.cell, &dl_sf, dl_cfg.tm, dl_cfg.pdsch.use_tbs_index_alt, &grants[i].dci, &dl_cfg.pdsch.grant)) {
Error("Computing DL grant\n");
}

44
srsenb/src/stack/mac/scheduler_ue.cc
Unescape Escape View File

@ -43,9 +43,19 @@ namespace sched_utils {
const uint32_t conres_ce_size = 6;
//! Obtains TB size *in bytes* for a given MCS and N_{PRB}
uint32_t get_tbs_bytes(uint32_t mcs, uint32_t nof_alloc_prb, bool is_ul)
uint32_t get_tbs_bytes(uint32_t mcs, uint32_t nof_alloc_prb, bool use_tbs_index_alt, bool is_ul)
{
return srslte_ra_tbs_from_idx(srslte_ra_tbs_idx_from_mcs(mcs, is_ul), nof_alloc_prb) / 8;
int tbs_idx = srslte_ra_tbs_idx_from_mcs(mcs, use_tbs_index_alt, is_ul);
if (tbs_idx < SRSLTE_SUCCESS) {
tbs_idx = 0;
}
int tbs = srslte_ra_tbs_from_idx((uint32_t)tbs_idx, nof_alloc_prb);
if (tbs < SRSLTE_SUCCESS) {
tbs = 0;
}
return (uint32_t)tbs / 8U;
}
//! TS 36.321 sec 7.1.2 - MAC PDU subheader is 2 bytes if L<=128 and 3 otherwise
@ -535,14 +545,15 @@ std::pair<int, int> sched_ue::compute_mcs_and_tbs(uint32_t ue_cc_i
tbs_bytes = carriers[ue_cc_idx].alloc_tbs_dl(nof_alloc_prbs, nof_re, req_bytes.second, &mcs);
} else {
// Fixed MCS
tbs_bytes = sched_utils::get_tbs_bytes((uint32_t)carriers[ue_cc_idx].fixed_mcs_dl, nof_alloc_prbs, false);
tbs_bytes = sched_utils::get_tbs_bytes(
(uint32_t)carriers[ue_cc_idx].fixed_mcs_dl, nof_alloc_prbs, cfg.use_tbs_index_alt, false);
}
// If the number of prbs is not sufficient to fit minimum required bytes, increase the mcs
// NOTE: this may happen during ConRes CE tx when DL-CQI is still not available
while (tbs_bytes > 0 and (uint32_t) tbs_bytes < req_bytes.first and mcs < 28) {
mcs++;
tbs_bytes = sched_utils::get_tbs_bytes((uint32_t)mcs, nof_alloc_prbs, false);
tbs_bytes = sched_utils::get_tbs_bytes((uint32_t)mcs, nof_alloc_prbs, cfg.use_tbs_index_alt, false);
}
return {mcs, tbs_bytes};
@ -690,7 +701,7 @@ int sched_ue::generate_format0(sched_interface::ul_sched_data_t* data,
nof_retx = (data->needs_pdcch) ? get_max_retx() : max_msg3retx;
if (mcs >= 0) {
tbs = srslte_ra_tbs_from_idx(srslte_ra_tbs_idx_from_mcs(mcs, true), alloc.L) / 8;
tbs = srslte_ra_tbs_from_idx(srslte_ra_tbs_idx_from_mcs(mcs, false, true), alloc.L) / 8;
} else {
// dynamic mcs
uint32_t req_bytes = get_pending_ul_new_data_unlocked(tti);
@ -705,7 +716,7 @@ int sched_ue::generate_format0(sched_interface::ul_sched_data_t* data,
} else {
// retx
h->new_retx(0, tti, &mcs, nullptr, alloc);
tbs = srslte_ra_tbs_from_idx(srslte_ra_tbs_idx_from_mcs(mcs, true), alloc.L) / 8;
tbs = srslte_ra_tbs_from_idx(srslte_ra_tbs_idx_from_mcs(mcs, false, true), alloc.L) / 8;
}
data->tbs = tbs;
@ -1157,6 +1168,7 @@ int sched_ue::cqi_to_tbs(uint32_t cqi,
uint32_t nof_re,
uint32_t max_mcs,
uint32_t max_Qm,
bool use_tbs_index_alt,
bool is_ul,
uint32_t* mcs)
{
@ -1169,10 +1181,11 @@ int sched_ue::cqi_to_tbs(uint32_t cqi,
do {
sel_mcs--;
uint32_t tbs_idx = srslte_ra_tbs_idx_from_mcs(sel_mcs, is_ul);
uint32_t tbs_idx = srslte_ra_tbs_idx_from_mcs(sel_mcs, use_tbs_index_alt, is_ul);
tbs = srslte_ra_tbs_from_idx(tbs_idx, nof_prb);
coderate = srslte_coderate(tbs, nof_re);
srslte_mod_t mod = (is_ul) ? srslte_ra_ul_mod_from_mcs(sel_mcs) : srslte_ra_dl_mod_from_mcs(sel_mcs);
srslte_mod_t mod =
(is_ul) ? srslte_ra_ul_mod_from_mcs(sel_mcs) : srslte_ra_dl_mod_from_mcs(sel_mcs, use_tbs_index_alt);
Qm = SRSLTE_MIN(max_Qm, srslte_mod_bits_x_symbol(mod));
eff_coderate = coderate / Qm;
} while ((sel_mcs > 0 && coderate > max_coderate) || eff_coderate > 0.930);
@ -1206,6 +1219,8 @@ sched_ue_carrier::sched_ue_carrier(const sched_interface::ue_cfg_t& cfg_,
// set max mcs
max_mcs_ul = cell_params->sched_cfg->pusch_max_mcs >= 0 ? cell_params->sched_cfg->pusch_max_mcs : 28;
max_mcs_dl = cell_params->sched_cfg->pdsch_max_mcs >= 0 ? cell_params->sched_cfg->pdsch_max_mcs : 28;
max_mcs_dl_alt =
cell_params->sched_cfg->pdsch_max_mcs >= 0 ? SRSLTE_MIN(cell_params->sched_cfg->pdsch_max_mcs, 27) : 27;
max_aggr_level = cell_params->sched_cfg->max_aggr_level >= 0 ? cell_params->sched_cfg->max_aggr_level : 3;
// set fixed mcs
@ -1280,16 +1295,17 @@ int sched_ue_carrier::alloc_tbs(uint32_t nof_prb, uint32_t nof_re, uint32_t req_
uint32_t sel_mcs = 0;
uint32_t cqi = is_ul ? ul_cqi : dl_cqi;
uint32_t max_mcs = is_ul ? max_mcs_ul : max_mcs_dl;
uint32_t max_mcs = is_ul ? max_mcs_ul : (cfg->use_tbs_index_alt) ? max_mcs_dl_alt : max_mcs_dl;
uint32_t max_Qm = is_ul ? 4 : 6; // Allow 16-QAM in PUSCH Only
// TODO: Compute real spectral efficiency based on PUSCH-UCI configuration
int tbs_bytes = sched_ue::cqi_to_tbs(cqi, nof_prb, nof_re, max_mcs, max_Qm, is_ul, &sel_mcs) / 8;
int tbs_bytes =
sched_ue::cqi_to_tbs(cqi, nof_prb, nof_re, max_mcs, max_Qm, cfg->use_tbs_index_alt, is_ul, &sel_mcs) / 8;
/* If less bytes are requested, lower the MCS */
if (tbs_bytes > (int)req_bytes && req_bytes > 0) {
int req_tbs_idx = srslte_ra_tbs_to_table_idx(req_bytes * 8, nof_prb);
int req_mcs = srslte_ra_mcs_from_tbs_idx(req_tbs_idx, is_ul);
int req_mcs = srslte_ra_mcs_from_tbs_idx(req_tbs_idx, cfg->use_tbs_index_alt, is_ul);
if (req_mcs < (int)sel_mcs) {
sel_mcs = req_mcs;
@ -1299,7 +1315,7 @@ int sched_ue_carrier::alloc_tbs(uint32_t nof_prb, uint32_t nof_re, uint32_t req_
// Avoid the unusual case n_prb=1, mcs=6 tbs=328 (used in voip)
if (nof_prb == 1 && sel_mcs == 6) {
sel_mcs--;
uint32_t tbs_idx = srslte_ra_tbs_idx_from_mcs(sel_mcs, is_ul);
uint32_t tbs_idx = srslte_ra_tbs_idx_from_mcs(sel_mcs, cfg->use_tbs_index_alt, is_ul);
tbs_bytes = srslte_ra_tbs_from_idx(tbs_idx, nof_prb) / 8;
}
@ -1333,7 +1349,7 @@ int sched_ue_carrier::get_required_prb_dl(uint32_t req_bytes, uint32_t nof_ctrl_
if (fixed_mcs_dl < 0 or not dl_cqi_rx) {
tbs = alloc_tbs_dl(n + 1, nof_re, 0, &mcs);
} else {
tbs = srslte_ra_tbs_from_idx(srslte_ra_tbs_idx_from_mcs(fixed_mcs_dl, false), n + 1) / 8;
tbs = srslte_ra_tbs_from_idx(srslte_ra_tbs_idx_from_mcs(fixed_mcs_dl, cfg->use_tbs_index_alt, false), n + 1) / 8;
}
if (tbs > 0) {
nbytes = tbs;
@ -1362,7 +1378,7 @@ uint32_t sched_ue_carrier::get_required_prb_ul(uint32_t req_bytes)
if (fixed_mcs_ul < 0) {
tbs = alloc_tbs_ul(n, nof_re, 0, &mcs);
} else {
tbs = srslte_ra_tbs_from_idx(srslte_ra_tbs_idx_from_mcs(fixed_mcs_ul, true), n) / 8;
tbs = srslte_ra_tbs_from_idx(srslte_ra_tbs_idx_from_mcs(fixed_mcs_ul, false, true), n) / 8;
}
if (tbs > 0) {
nbytes = tbs;

31
srsenb/src/stack/rrc/rrc.cc
Unescape Escape View File

@ -1318,6 +1318,8 @@ bool rrc::ue::handle_ue_cap_info(ue_cap_info_s* msg)
return false;
}
eutra_capabilities_unpacked = true;
srslte::set_rrc_ue_capabilities_t(ue_capabilities, eutra_capabilities);
parent->rrc_log->info("UE rnti: 0x%x category: %d\n", rnti, eutra_capabilities.ue_category);
}
}
@ -1780,10 +1782,6 @@ void rrc::ue::send_connection_reconf(srslte::unique_byte_buffer_t pdu)
conn_reconf->rr_cfg_ded.phys_cfg_ded_present = true;
phys_cfg_ded_s* phy_cfg = &conn_reconf->rr_cfg_ded.phys_cfg_ded;
// Parse UE capabilities
srslte::rrc_ue_eutra_cap_t rrc_ue_eutra_cap;
srslte::set_rrc_ue_eutra_cap_t(rrc_ue_eutra_cap, eutra_capabilities);
// Configure PHY layer
phy_cfg->ant_info_present = true;
phy_cfg->ant_info.set_explicit_value() = parent->cfg.antenna_info;
@ -1823,6 +1821,15 @@ void rrc::ue::send_connection_reconf(srslte::unique_byte_buffer_t pdu)
phy_cfg->pdsch_cfg_ded_present = true;
phy_cfg->pdsch_cfg_ded.p_a = parent->cfg.pdsch_cfg;
// Configure 256QAM
if (ue_capabilities.category_dl >= 11 && ue_capabilities.support_dl_256qam) {
phy_cfg->cqi_report_cfg_pcell_v1250.set_present(true);
cqi_report_cfg_v1250_s* cqi_report_cfg = conn_reconf->rr_cfg_ded.phys_cfg_ded.cqi_report_cfg_pcell_v1250.get();
cqi_report_cfg->alt_cqi_table_r12_present = true;
cqi_report_cfg->alt_cqi_table_r12 = asn1::rrc::cqi_report_cfg_v1250_s::alt_cqi_table_r12_e_::all_sfs;
current_sched_ue_cfg.use_tbs_index_alt = true;
}
// Add SCells
fill_scell_to_addmod_list(conn_reconf);
@ -1849,14 +1856,6 @@ void rrc::ue::send_connection_reconf(srslte::unique_byte_buffer_t pdu)
return;
}
// Configure 256QAM
if (rrc_ue_eutra_cap.category_dl >= 11 && rrc_ue_eutra_cap.support_dl_256qam) {
phy_cfg->cqi_report_cfg_pcell_v1250.set_present(true);
cqi_report_cfg_v1250_s* cqi_report_cfg = conn_reconf->rr_cfg_ded.phys_cfg_ded.cqi_report_cfg_pcell_v1250.get();
cqi_report_cfg->alt_cqi_table_r12_present = true;
cqi_report_cfg->alt_cqi_table_r12 = asn1::rrc::cqi_report_cfg_v1250_s::alt_cqi_table_r12_e_::all_sfs;
}
// Configure SRB2 in RLC and PDCP
parent->rlc->add_bearer(rnti, 2, srslte::rlc_config_t::srb_config(2));
@ -2001,6 +2000,14 @@ void rrc::ue::fill_scell_to_addmod_list(asn1::rrc::rrc_conn_recfg_r8_ies_s* conn
ul_cfg_ded.cqi_report_cfg_scell_r10.nom_pdsch_rs_epre_offset_r10 = 0;
ul_cfg_ded.cqi_report_cfg_scell_r10.cqi_report_periodic_scell_r10_present = true;
// Add 256QAM
if (ue_capabilities.category_dl >= 11 && ue_capabilities.support_dl_256qam) {
cell.rr_cfg_ded_scell_r10.phys_cfg_ded_scell_r10.cqi_report_cfg_scell_v1250.set_present(true);
auto cqi_report_cfg_scell = cell.rr_cfg_ded_scell_r10.phys_cfg_ded_scell_r10.cqi_report_cfg_scell_v1250.get();
cqi_report_cfg_scell->alt_cqi_table_r12_present = true;
cqi_report_cfg_scell->alt_cqi_table_r12 = asn1::rrc::cqi_report_cfg_v1250_s::alt_cqi_table_r12_e_::all_sfs;
}
// Get CQI allocation for secondary cell
auto& cqi_setup = ul_cfg_ded.cqi_report_cfg_scell_r10.cqi_report_periodic_scell_r10.set_setup();
cqi_get(&cqi_setup.cqi_pmi_cfg_idx, &cqi_setup.cqi_pucch_res_idx_r10, scell_idx);

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