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@ -1029,11 +1029,8 @@ rrc::ue::ue(rrc* outer_rrc, uint16_t rnti_, const sched_interface::ue_cfg_t& sch
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apply_setup_phy_common(parent->cfg.sibs[1].sib2().rr_cfg_common);
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// Allocate PUCCH resources
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cqi_allocate(parent->cfg.cqi_cfg.period);
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cqi_allocate(parent->cfg.cqi_cfg.period, 0);
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sr_allocate(parent->cfg.cqi_cfg.period);
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if (parent->cfg.cell_list.size() > 1) {
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n_pucch_cs_allocate();
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}
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}
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rrc::ue::~ue()
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@ -1854,7 +1851,11 @@ void rrc::ue::send_connection_reconf(srslte::unique_byte_buffer_t pdu)
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}
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// Add SCells
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fill_scell_to_addmod_list(conn_reconf);
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if (fill_scell_to_addmod_list(conn_reconf)) {
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parent->rrc_log->warning("Could not create configuration for Scell\n");
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// Should disable R10 extension and not activate SCell??
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return;
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}
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apply_reconf_phy_config(*conn_reconf);
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current_sched_ue_cfg.dl_ant_info = srslte::make_ant_info_ded(phy_cfg->ant_info.explicit_value());
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@ -1955,28 +1956,12 @@ rrc::cell_ctxt_t* rrc::ue::get_ue_cc_cfg(uint32_t ue_cc_idx)
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}
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//! Method to fill SCellToAddModList for SCell info
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void rrc::ue::fill_scell_to_addmod_list(asn1::rrc::rrc_conn_recfg_r8_ies_s* conn_reconf)
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int rrc::ue::fill_scell_to_addmod_list(asn1::rrc::rrc_conn_recfg_r8_ies_s* conn_reconf)
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{
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const cell_ctxt_t* pcell_cfg = get_ue_cc_cfg(UE_PCELL_CC_IDX);
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if (pcell_cfg->cell_cfg.scell_list.size() == 0) {
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return;
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}
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// Set DL HARQ Feedback mode, PUCCH3 by default
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conn_reconf->rr_cfg_ded.phys_cfg_ded.pucch_cfg_ded_v1020.set_present(true);
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conn_reconf->rr_cfg_ded.phys_cfg_ded.pucch_cfg_ded_v1020.get()->pucch_format_r10_present = true;
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conn_reconf->rr_cfg_ded.phys_cfg_ded.ext = true;
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auto pucch_format_r10 = conn_reconf->rr_cfg_ded.phys_cfg_ded.pucch_cfg_ded_v1020.get();
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pucch_format_r10->pucch_format_r10_present = true;
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auto& ch_sel_r10 = pucch_format_r10->pucch_format_r10.set_ch_sel_r10();
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ch_sel_r10.n1_pucch_an_cs_r10_present = true;
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ch_sel_r10.n1_pucch_an_cs_r10.set_setup();
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n1_pucch_an_cs_r10_l item0(4);
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// TODO: should we use a different n1PUCCH-AN-CS-List configuration?
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for (auto& it : item0) {
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get_n_pucch_cs(&it);
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return SRSLTE_SUCCESS;
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}
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ch_sel_r10.n1_pucch_an_cs_r10.setup().n1_pucch_an_cs_list_r10.push_back(item0);
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conn_reconf->non_crit_ext_present = true;
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conn_reconf->non_crit_ext.non_crit_ext_present = true;
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@ -1987,6 +1972,12 @@ void rrc::ue::fill_scell_to_addmod_list(asn1::rrc::rrc_conn_recfg_r8_ies_s* conn
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// Add all SCells configured for the current PCell
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uint32_t scell_idx = 1; // SCell start with 1, zero reserved for PCell
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for (auto& scell : pcell_cfg->cell_cfg.scell_list) {
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// Allocate PUCCH resources
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if (allocate_scell_pucch(scell_idx)) {
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return SRSLTE_ERROR;
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}
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// get corresponding eNB cell context for this scell
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const cell_ctxt_t* cc_cfg = parent->find_cell_ctxt(scell.cell_id);
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if (cc_cfg == nullptr) {
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@ -2096,6 +2087,24 @@ void rrc::ue::fill_scell_to_addmod_list(asn1::rrc::rrc_conn_recfg_r8_ies_s* conn
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scell_idx++;
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}
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// Set DL HARQ Feedback mode
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conn_reconf->rr_cfg_ded.phys_cfg_ded.pucch_cfg_ded_v1020.set_present(true);
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conn_reconf->rr_cfg_ded.phys_cfg_ded.pucch_cfg_ded_v1020.get()->pucch_format_r10_present = true;
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conn_reconf->rr_cfg_ded.phys_cfg_ded.ext = true;
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auto pucch_format_r10 = conn_reconf->rr_cfg_ded.phys_cfg_ded.pucch_cfg_ded_v1020.get();
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pucch_format_r10->pucch_format_r10_present = true;
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auto& ch_sel_r10 = pucch_format_r10->pucch_format_r10.set_ch_sel_r10();
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ch_sel_r10.n1_pucch_an_cs_r10_present = true;
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ch_sel_r10.n1_pucch_an_cs_r10.set_setup();
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n1_pucch_an_cs_r10_l item0(4);
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// TODO: should we use a different n1PUCCH-AN-CS-List configuration?
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for (auto& it : item0) {
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get_n_pucch_cs(&it);
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}
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ch_sel_r10.n1_pucch_an_cs_r10.setup().n1_pucch_an_cs_list_r10.push_back(item0);
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return SRSLTE_SUCCESS;
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}
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void rrc::ue::send_connection_reconf_new_bearer(const asn1::s1ap::erab_to_be_setup_list_bearer_su_req_l& e)
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@ -2482,7 +2491,7 @@ int rrc::ue::get_sr(uint8_t* I_sr, uint16_t* N_pucch_sr)
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}
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}
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void rrc::ue::sr_allocate(uint32_t period)
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int rrc::ue::sr_allocate(uint32_t period)
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{
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uint32_t c = SRSLTE_CP_ISNORM(parent->cfg.cell.cp) ? 3 : 2;
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uint32_t delta_pucch_shift =
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@ -2505,20 +2514,20 @@ void rrc::ue::sr_allocate(uint32_t period)
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if (parent->sr_sched.nof_users[i_min][j_min] > max_users) {
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parent->rrc_log->error("Not enough PUCCH resources to allocate Scheduling Request\n");
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return;
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return SRSLTE_ERROR;
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}
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// Compute I_sr
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if (period != 5 && period != 10 && period != 20 && period != 40 && period != 80) {
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parent->rrc_log->error("Invalid SchedulingRequest period %d ms\n", period);
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return;
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return SRSLTE_ERROR;
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}
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if (parent->cfg.sr_cfg.sf_mapping[j_min] < period) {
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sr_I = period - 5 + parent->cfg.sr_cfg.sf_mapping[j_min];
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} else {
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parent->rrc_log->error(
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"Allocating SR: invalid sf_idx=%d for period=%d\n", parent->cfg.sr_cfg.sf_mapping[j_min], period);
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return;
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return SRSLTE_ERROR;
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}
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// Compute N_pucch_sr
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@ -2538,6 +2547,7 @@ void rrc::ue::sr_allocate(uint32_t period)
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sr_sched_sf_idx,
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sr_N_pucch,
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sr_I);
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return SRSLTE_SUCCESS;
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}
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void rrc::ue::cqi_free()
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@ -2582,7 +2592,23 @@ int rrc::ue::get_cqi(uint16_t* pmi_idx, uint16_t* n_pucch, uint32_t ue_cc_idx)
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}
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}
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void rrc::ue::n_pucch_cs_allocate()
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int rrc::ue::allocate_scell_pucch(uint32_t ue_cc_idx)
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{
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if (cqi_allocate(parent->cfg.cqi_cfg.period, ue_cc_idx)) {
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parent->rrc_log->error("Error allocating CQI resource for ue_cc_idx=%d\n", ue_cc_idx);
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return SRSLTE_ERROR;
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}
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// Allocate resources for Format1b CS (will be optional PUCCH3/CS)
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if (parent->cfg.cell_list.size() == 2 && ue_cc_idx == 1) {
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if (n_pucch_cs_allocate()) {
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parent->rrc_log->error("Error allocating PUCCH Format1b CS resource for ue_cc_idx=%d\n", ue_cc_idx);
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return SRSLTE_ERROR;
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}
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}
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return SRSLTE_SUCCESS;
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}
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int rrc::ue::n_pucch_cs_allocate()
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{
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const sib_type2_s& sib2 = get_ue_cc_cfg(UE_PCELL_CC_IDX)->sib2;
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const uint16_t N_pucch_1 = sib2.rr_cfg_common.pucch_cfg_common.n1_pucch_an;
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@ -2595,13 +2621,14 @@ void rrc::ue::n_pucch_cs_allocate()
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n_pucch_cs_idx = i;
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n_pucch_cs_alloc = true;
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parent->rrc_log->info("Allocated N_pucch_cs=%d\n", n_pucch_cs_idx);
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return;
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return SRSLTE_SUCCESS;
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}
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}
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parent->rrc_log->warning("Could not allocated N_pucch_cs\n");
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return SRSLTE_ERROR;
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}
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void rrc::ue::cqi_allocate(uint32_t period)
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int rrc::ue::cqi_allocate(uint32_t period, uint32_t ue_cc_idx)
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{
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uint32_t c = SRSLTE_CP_ISNORM(parent->cfg.cell.cp) ? 3 : 2;
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uint32_t delta_pucch_shift =
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@ -2609,8 +2636,7 @@ void rrc::ue::cqi_allocate(uint32_t period)
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uint32_t max_users = 12 * c / delta_pucch_shift;
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// Allocate all CQI resources for all carriers nowcqi_alloc6ate
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for (uint32_t cc_idx = 0; cc_idx < parent->cfg.cell_list.size(); cc_idx++) {
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// Allocate all CQI resources for all carriers now
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// Find freq-time resources with least number of users
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int i_min = 0, j_min = 0;
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uint32_t min_users = std::numeric_limits<uint32_t>::max();
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@ -2626,7 +2652,7 @@ void rrc::ue::cqi_allocate(uint32_t period)
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if (parent->cqi_sched.nof_users[i_min][j_min] > max_users) {
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parent->rrc_log->error("Not enough PUCCH resources to allocate Scheduling Request\n");
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return;
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return SRSLTE_ERROR;
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}
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uint16_t pmi_idx = 0;
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@ -2636,7 +2662,7 @@ void rrc::ue::cqi_allocate(uint32_t period)
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if (period != 2 && period != 5 && period != 10 && period != 20 && period != 40 && period != 80 && period != 160 &&
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period != 32 && period != 64 && period != 128) {
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parent->rrc_log->error("Invalid CQI Report period %d ms\n", period);
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return;
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return SRSLTE_ERROR;
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}
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if (parent->cfg.cqi_cfg.sf_mapping[j_min] < period) {
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if (period != 32 && period != 64 && period != 128) {
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@ -2657,7 +2683,7 @@ void rrc::ue::cqi_allocate(uint32_t period)
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} else {
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parent->rrc_log->error(
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"Allocating CQI: invalid sf_idx=%d for period=%d\n", parent->cfg.cqi_cfg.sf_mapping[j_min], period);
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return;
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return SRSLTE_ERROR;
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}
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// Compute n_pucch_2
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@ -2668,19 +2694,20 @@ void rrc::ue::cqi_allocate(uint32_t period)
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// Allocate user
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parent->cqi_sched.nof_users[i_min][j_min]++;
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cqi_allocated = true;
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cqi_res[cc_idx].idx = pmi_idx;
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cqi_res[cc_idx].pucch_res = n_pucch;
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cqi_res[cc_idx].prb_idx = i_min;
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cqi_res[cc_idx].sf_idx = j_min;
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cqi_res[ue_cc_idx].idx = pmi_idx;
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cqi_res[ue_cc_idx].pucch_res = n_pucch;
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cqi_res[ue_cc_idx].prb_idx = i_min;
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cqi_res[ue_cc_idx].sf_idx = j_min;
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parent->rrc_log->info(
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"Allocated CQI resources for cc_idx=%d, time-frequency slot (%d, %d), n_pucch_2=%d, pmi_cfg_idx=%d\n",
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cc_idx,
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"Allocated CQI resources for ue_cc_idx=%d, time-frequency slot (%d, %d), n_pucch_2=%d, pmi_cfg_idx=%d\n",
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ue_cc_idx,
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i_min,
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j_min,
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n_pucch,
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pmi_idx);
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}
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return SRSLTE_SUCCESS;
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}
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int rrc::ue::get_n_pucch_cs(uint16_t* N_pucch_cs)
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