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@ -11,16 +11,15 @@
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*/
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*/
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#include "srsenb/hdr/phy/nr/slot_worker.h"
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#include "srsenb/hdr/phy/nr/slot_worker.h"
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#include <srsran/common/common.h>
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#include "srsran/common/buffer_pool.h"
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#include "srsran/common/common.h"
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namespace srsenb {
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namespace srsenb {
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namespace nr {
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namespace nr {
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slot_worker::slot_worker(srsran::phy_common_interface& common_,
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slot_worker::slot_worker(srsran::phy_common_interface& common_,
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stack_interface_phy_nr& stack_,
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stack_interface_phy_nr& stack_,
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srslog::basic_logger& logger_) :
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srslog::basic_logger& logger_) :
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common(common_),
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common(common_), stack(stack_), logger(logger_)
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stack(stack_),
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logger(logger_)
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{
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{
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// Do nothing
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// Do nothing
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}
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}
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@ -203,12 +202,13 @@ bool slot_worker::work_ul()
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// For each PUSCH...
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// For each PUSCH...
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for (stack_interface_phy_nr::pusch_t& pusch : ul_sched.pusch) {
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for (stack_interface_phy_nr::pusch_t& pusch : ul_sched.pusch) {
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// Get payload PDU
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// Prepare PUSCH
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stack_interface_phy_nr::pusch_info_t pusch_info = {};
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stack_interface_phy_nr::pusch_info_t pusch_info = {};
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pusch_info.uci_cfg = pusch.sch.uci;
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pusch_info.uci_cfg = pusch.sch.uci;
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pusch_info.pid = pusch.pid;
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pusch_info.pid = pusch.pid;
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pusch_info.pusch_data.tb[0].payload = pusch.data[0];
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pusch_info.pdu = srsran::make_byte_buffer();
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pusch_info.pusch_data.tb[1].payload = pusch.data[1];
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pusch_info.pusch_data.tb[0].payload = pusch_info.pdu->data();
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pusch_info.pusch_data.tb[1].payload = pusch_info.pdu->data();
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// Decode PUSCH
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// Decode PUSCH
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if (srsran_gnb_ul_get_pusch(&gnb_ul, &ul_slot_cfg, &pusch.sch, &pusch.sch.grant, &pusch_info.pusch_data) <
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if (srsran_gnb_ul_get_pusch(&gnb_ul, &ul_slot_cfg, &pusch.sch, &pusch.sch.grant, &pusch_info.pusch_data) <
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@ -369,7 +369,10 @@ bool slot_worker::set_common_cfg(const srsran_carrier_nr_t& carrier, const srsra
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// Set gNb UL carrier
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// Set gNb UL carrier
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if (srsran_gnb_ul_set_carrier(&gnb_ul, &carrier) < SRSRAN_SUCCESS) {
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if (srsran_gnb_ul_set_carrier(&gnb_ul, &carrier) < SRSRAN_SUCCESS) {
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logger.error("Error setting UL carrier");
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logger.error("Error setting UL carrier (pci=%d, nof_prb=%d, max_mimo_layers=%d)",
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carrier.pci,
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carrier.nof_prb,
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carrier.max_mimo_layers);
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return false;
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return false;
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}
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}
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