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@ -479,8 +479,26 @@ int sched_ue::generate_format1(uint32_t pid,
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int mcs = 0;
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int tbs = 0;
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dci->alloc_type = SRSLTE_RA_ALLOC_TYPE0;
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dci->type0_alloc.rbg_bitmask = (uint32_t)user_mask.to_uint64();
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// If the size of Format1 and Format1A is ambiguous in the common SS, use Format1A since the UE assumes
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// Common SS when spaces collide
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if (cell.nof_prb == 15 && carriers.size() > 1) {
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dci->alloc_type = SRSLTE_RA_ALLOC_TYPE2;
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dci->type2_alloc.mode = srslte_ra_type2_t::SRSLTE_RA_TYPE2_LOC;
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rbg_interval rbg_int = rbg_interval::rbgmask_to_rbgs(user_mask);
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uint32_t P = srslte_ra_type0_P(15);
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prb_interval prb_int = prb_interval::rbgs_to_prbs(rbg_int, P);
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dci->type2_alloc.riv =
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srslte_ra_type2_to_riv(SRSLTE_MIN(prb_int.length(), cell.nof_prb), prb_int.start(), cell.nof_prb);
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dci->format = SRSLTE_DCI_FORMAT1A;
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if (prb_int.length() != P * user_mask.count()) {
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// This happens if Type0 was using distributed allocation
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Warning("SCHED: Can't use distributed RA due to DCI size ambiguity\n");
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}
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} else {
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dci->alloc_type = SRSLTE_RA_ALLOC_TYPE0;
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dci->type0_alloc.rbg_bitmask = (uint32_t)user_mask.to_uint64();
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dci->format = SRSLTE_DCI_FORMAT1;
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}
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if (h->is_empty(0)) {
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auto ret = allocate_new_dl_mac_pdu(data, h, user_mask, tti_tx_dl, ue_cc_idx, cfi, 0, "1");
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@ -503,8 +521,6 @@ int sched_ue::generate_format1(uint32_t pid,
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next_tpc_pucch = 1;
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data->tbs[0] = (uint32_t)tbs;
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data->tbs[1] = 0;
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dci->format = SRSLTE_DCI_FORMAT1;
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}
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return tbs;
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}
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