mirror of https://github.com/pvnis/srsRAN_4G.git
nr,gnb,sched: implemented sched helper functions, wrote a unit test for PDCCH allocations
Francisco
3 years ago
committed by
Francisco Paisana
parent
de13c68df7
commit
384004d8d1
@ -0,0 +1,228 @@
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/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2021 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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#include "sched_nr_cfg_generators.h"
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#include "sched_nr_common_test.h"
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#include "srsgnb/hdr/stack/mac/sched_nr_helpers.h"
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#include "srsgnb/hdr/stack/mac/sched_nr_interface_utils.h"
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#include "srsgnb/hdr/stack/mac/sched_nr_pdcch.h"
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#include "srsran/common/test_common.h"
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namespace srsenb {
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using namespace sched_nr_impl;
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/**
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* Test for the case CORESET#0 is active.
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* Given only one PDCCH candidate position is supported, only one PDCCH allocation should take place per slot
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* The test additionally verifies that the DCI context content is correct for each PDCCH allocation
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*/
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void test_coreset0_cfg()
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{
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const uint32_t aggr_idx = 2;
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srsran::test_delimit_logger delimiter{"Test PDCCH Allocation in CORESET#0"};
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sched_nr_impl::cell_cfg_t cell_cfg = get_default_sa_cell_cfg_common();
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sched_nr_interface::sched_args_t sched_args;
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bwp_params_t bwp_params{cell_cfg, sched_args, 0, 0};
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// UE config
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ue_cfg_t uecfg = get_rach_ue_cfg(0);
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uecfg.phy_cfg.pdcch = cell_cfg.bwps[0].pdcch; // Starts without UE-specific PDCCH
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ue_carrier_params_t ue_cc{0x46, bwp_params, uecfg};
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pdcch_dl_list_t dl_pdcchs;
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pdcch_ul_list_t ul_pdcchs;
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pdcch_dl_t* dl_pdcch = nullptr;
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pdcch_ul_t* ul_pdcch = nullptr;
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bwp_pdcch_allocator pdcch_sched(bwp_params, 0, dl_pdcchs, ul_pdcchs);
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for (const srsran_coreset_t& cs : view_active_coresets(cell_cfg.bwps[0].pdcch)) {
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// Verify nof CCEs is correctly computed
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TESTASSERT_EQ(coreset_nof_cces(cs), pdcch_sched.nof_cces(cs.id));
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}
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// Slot with SIB1
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TESTASSERT_EQ(0, pdcch_sched.nof_allocations());
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// SIB1 allocation should be successful
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dl_pdcch = pdcch_sched.alloc_si_pdcch(0, aggr_idx);
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TESTASSERT(dl_pdcch != nullptr);
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TESTASSERT_EQ(1, pdcch_sched.nof_allocations());
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TESTASSERT_EQ(srsran_rnti_type_si, dl_pdcch->dci.ctx.rnti_type);
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TESTASSERT_EQ(0, dl_pdcch->dci.ctx.coreset_id);
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test_dci_ctx_consistency(bwp_params.cfg.pdcch, dl_pdcch->dci.ctx);
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// No space for RAR, UE PDSCH/PUSCH
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TESTASSERT(pdcch_sched.alloc_rar_pdcch(0x2, aggr_idx) == nullptr);
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TESTASSERT(pdcch_sched.alloc_dl_pdcch(srsran_rnti_type_c, 1, aggr_idx, ue_cc) == nullptr);
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TESTASSERT(pdcch_sched.alloc_ul_pdcch(1, aggr_idx, ue_cc) == nullptr);
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// Slot with RAR
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pdcch_sched.reset();
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// RAR allocation should be successful
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dl_pdcch = pdcch_sched.alloc_rar_pdcch(0x2, aggr_idx);
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TESTASSERT(dl_pdcch != nullptr);
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TESTASSERT_EQ(1, pdcch_sched.nof_allocations());
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TESTASSERT_EQ(srsran_rnti_type_ra, dl_pdcch->dci.ctx.rnti_type);
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TESTASSERT_EQ(0, dl_pdcch->dci.ctx.coreset_id);
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TESTASSERT_EQ(srsran_search_space_type_common_1, dl_pdcch->dci.ctx.ss_type);
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test_dci_ctx_consistency(bwp_params.cfg.pdcch, dl_pdcch->dci.ctx);
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// No space for RAR, UE PDSCH/PUSCH
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TESTASSERT(pdcch_sched.alloc_dl_pdcch(srsran_rnti_type_c, 1, aggr_idx, ue_cc) == nullptr);
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TESTASSERT(pdcch_sched.alloc_ul_pdcch(1, aggr_idx, ue_cc) == nullptr);
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// Slot with DL PDSCH
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pdcch_sched.reset();
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// 1st PDCCH allocation for DL should be successful
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dl_pdcch = pdcch_sched.alloc_dl_pdcch(srsran_rnti_type_c, 1, aggr_idx, ue_cc);
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TESTASSERT(dl_pdcch != nullptr);
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TESTASSERT_EQ(1, pdcch_sched.nof_allocations());
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TESTASSERT_EQ(srsran_rnti_type_c, dl_pdcch->dci.ctx.rnti_type);
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TESTASSERT_EQ(0u, dl_pdcch->dci.ctx.coreset_id);
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TESTASSERT_EQ(srsran_search_space_type_common_1, dl_pdcch->dci.ctx.ss_type);
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test_dci_ctx_consistency(bwp_params.cfg.pdcch, dl_pdcch->dci.ctx);
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// No space for 2nd PDCCH allocation
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TESTASSERT(pdcch_sched.alloc_ul_pdcch(1, aggr_idx, ue_cc) == nullptr);
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// Slot with UL PDSCH
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pdcch_sched.reset();
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// 1st PDCCH allocation for UL should be successful
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ul_pdcch = pdcch_sched.alloc_ul_pdcch(1, aggr_idx, ue_cc);
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TESTASSERT(ul_pdcch != nullptr);
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TESTASSERT_EQ(1, pdcch_sched.nof_allocations());
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TESTASSERT_EQ(srsran_rnti_type_c, ul_pdcch->dci.ctx.rnti_type);
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TESTASSERT_EQ(0u, ul_pdcch->dci.ctx.coreset_id);
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TESTASSERT_EQ(srsran_search_space_type_common_1, ul_pdcch->dci.ctx.ss_type);
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test_dci_ctx_consistency(bwp_params.cfg.pdcch, ul_pdcch->dci.ctx);
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// No space for 2nd PDCCH allocation
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TESTASSERT(pdcch_sched.alloc_dl_pdcch(srsran_rnti_type_c, 1, aggr_idx, ue_cc) == nullptr);
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}
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/**
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* Test for the case CORESET#2 is active.
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* The PDCCH allocator should find enough space to fit SIB1/RAR (in CORESET#0) and UE-dedicated PDCCHs in (CORESET#2)
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* The test additionally verifies that the DCI context content is correct for each PDCCH allocation and there are no
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* collisions between PDCCH CCE allocations
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*/
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void test_coreset2_cfg()
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{
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const uint32_t aggr_idx = 2;
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srsran::test_delimit_logger delimiter{"Test PDCCH Allocation in CORESET#0 and CORESET#2"};
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sched_nr_impl::cell_cfg_t cell_cfg = get_default_sa_cell_cfg_common();
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cell_cfg.bwps[0].pdcch.search_space_present[2] = true;
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cell_cfg.bwps[0].pdcch.search_space[2] = get_default_ue_specific_search_space(2, 2);
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cell_cfg.bwps[0].pdcch.coreset_present[2] = true;
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cell_cfg.bwps[0].pdcch.coreset[2] = get_default_ue_specific_coreset(2, cell_cfg.carrier.pci);
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sched_nr_interface::sched_args_t sched_args;
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bwp_params_t bwp_params{cell_cfg, sched_args, 0, 0};
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// UE config
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ue_cfg_t uecfg = get_rach_ue_cfg(0);
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uecfg.phy_cfg = get_common_ue_phy_cfg(cell_cfg);
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uecfg.phy_cfg.pdcch = cell_cfg.bwps[0].pdcch; // Starts with UE-specific PDCCH
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ue_carrier_params_t ue_cc{0x46, bwp_params, uecfg};
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pdcch_dl_list_t dl_pdcchs;
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pdcch_ul_list_t ul_pdcchs;
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pdcch_dl_t* dl_pdcch = nullptr;
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pdcch_ul_t* ul_pdcch = nullptr;
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bwp_pdcch_allocator pdcch_sched(bwp_params, 0, dl_pdcchs, ul_pdcchs);
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for (const srsran_coreset_t& cs : view_active_coresets(cell_cfg.bwps[0].pdcch)) {
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// Verify nof CCEs is correctly computed
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TESTASSERT_EQ(coreset_nof_cces(cs), pdcch_sched.nof_cces(cs.id));
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}
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// Slot with SIB1 + DL PDCCH and UL PDCCH
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TESTASSERT_EQ(0, pdcch_sched.nof_allocations());
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// SIB1 allocation should be successful
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dl_pdcch = pdcch_sched.alloc_si_pdcch(0, aggr_idx);
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TESTASSERT(dl_pdcch != nullptr);
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TESTASSERT_EQ(1, pdcch_sched.nof_allocations());
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TESTASSERT_EQ(srsran_rnti_type_si, dl_pdcch->dci.ctx.rnti_type);
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TESTASSERT_EQ(0, dl_pdcch->dci.ctx.coreset_id);
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srsran_dci_location_t expected_loc{aggr_idx, 0};
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TESTASSERT(dl_pdcch->dci.ctx.location == expected_loc);
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test_dci_ctx_consistency(bwp_params.cfg.pdcch, dl_pdcch->dci.ctx);
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// No space for RAR or PDSCH in SS#1
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TESTASSERT(pdcch_sched.alloc_rar_pdcch(0x2, aggr_idx) == nullptr);
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TESTASSERT(pdcch_sched.alloc_dl_pdcch(srsran_rnti_type_c, 1, aggr_idx, ue_cc) == nullptr);
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TESTASSERT(pdcch_sched.alloc_ul_pdcch(1, aggr_idx, ue_cc) == nullptr);
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// there is space for UE DL PDCCH in SS#2
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dl_pdcch = pdcch_sched.alloc_dl_pdcch(srsran_rnti_type_c, 2, aggr_idx, ue_cc);
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TESTASSERT(dl_pdcch != nullptr);
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TESTASSERT_EQ(2, pdcch_sched.nof_allocations());
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TESTASSERT_EQ(srsran_rnti_type_c, dl_pdcch->dci.ctx.rnti_type);
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TESTASSERT_EQ(2u, dl_pdcch->dci.ctx.coreset_id);
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TESTASSERT_EQ(srsran_search_space_type_ue, dl_pdcch->dci.ctx.ss_type);
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expected_loc = srsran_dci_location_t{aggr_idx, 0};
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TESTASSERT(dl_pdcch->dci.ctx.location == expected_loc);
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test_dci_ctx_consistency(bwp_params.cfg.pdcch, dl_pdcch->dci.ctx);
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// there is space for UE UL PDCCH in SS#2
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ul_pdcch = pdcch_sched.alloc_ul_pdcch(2, aggr_idx, ue_cc);
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TESTASSERT(ul_pdcch != nullptr);
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TESTASSERT_EQ(3, pdcch_sched.nof_allocations());
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TESTASSERT_EQ(srsran_rnti_type_c, ul_pdcch->dci.ctx.rnti_type);
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TESTASSERT_EQ(srsran_dci_format_nr_0_0, ul_pdcch->dci.ctx.format);
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TESTASSERT_EQ(2u, ul_pdcch->dci.ctx.coreset_id);
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TESTASSERT_EQ(srsran_search_space_type_ue, ul_pdcch->dci.ctx.ss_type);
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expected_loc = srsran_dci_location_t{aggr_idx, 4};
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TESTASSERT(ul_pdcch->dci.ctx.location == expected_loc);
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test_dci_ctx_consistency(bwp_params.cfg.pdcch, ul_pdcch->dci.ctx);
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// No space for 3rd PDCCH allocation in SS#2
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TESTASSERT(pdcch_sched.alloc_dl_pdcch(srsran_rnti_type_c, 2, aggr_idx, ue_cc) == nullptr);
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// Verify there are no PDCCH collisions
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TESTASSERT_EQ(3, pdcch_sched.nof_allocations());
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TESTASSERT_EQ(2, dl_pdcchs.size());
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TESTASSERT_EQ(1, ul_pdcchs.size());
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test_pdcch_collisions(bwp_params.cfg.pdcch, dl_pdcchs, ul_pdcchs);
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// Verify all coresets are correctly cleaned up
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pdcch_sched.reset();
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TESTASSERT_EQ(0, pdcch_sched.nof_allocations());
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TESTASSERT_EQ(0, dl_pdcchs.size());
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TESTASSERT_EQ(0, ul_pdcchs.size());
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}
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} // namespace srsenb
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int main()
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{
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auto& test_logger = srslog::fetch_basic_logger("TEST");
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test_logger.set_level(srslog::basic_levels::info);
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auto& mac_nr_logger = srslog::fetch_basic_logger("MAC-NR");
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mac_nr_logger.set_level(srslog::basic_levels::debug);
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auto& pool_logger = srslog::fetch_basic_logger("POOL");
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pool_logger.set_level(srslog::basic_levels::debug);
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// Start the log backend.
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srslog::init();
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srsenb::test_coreset0_cfg();
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srsenb::test_coreset2_cfg();
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}
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