Fix DCI NR configuration from main configuration

master
Xavier Arteaga 4 years ago committed by Andre Puschmann
parent 86ad0446e1
commit 334b308c35

@ -43,7 +43,7 @@ struct phy_cfg_nr_t {
{ {
srsran_dci_cfg_nr_t dci_cfg = {}; srsran_dci_cfg_nr_t dci_cfg = {};
// Set bandwidths // Assume BWP bandwidth equals full channel bandwidth
dci_cfg.coreset0_bw = pdcch.coreset_present[0] ? srsran_coreset_get_bw(&pdcch.coreset[0]) : 0; dci_cfg.coreset0_bw = pdcch.coreset_present[0] ? srsran_coreset_get_bw(&pdcch.coreset[0]) : 0;
dci_cfg.bwp_dl_initial_bw = carrier.nof_prb; dci_cfg.bwp_dl_initial_bw = carrier.nof_prb;
dci_cfg.bwp_dl_active_bw = carrier.nof_prb; dci_cfg.bwp_dl_active_bw = carrier.nof_prb;
@ -79,24 +79,45 @@ struct phy_cfg_nr_t {
// Set Format 0_1 and 1_1 parameters // Set Format 0_1 and 1_1 parameters
dci_cfg.carrier_indicator_size = 0; dci_cfg.carrier_indicator_size = 0;
dci_cfg.harq_ack_codebok = harq_ack.harq_ack_codebook; dci_cfg.harq_ack_codebok = harq_ack.harq_ack_codebook;
dci_cfg.nof_rb_groups = 0;
// Format 0_1 specific configuration (for PUSCH only) // Format 0_1 specific configuration (for PUSCH only)
dci_cfg.nof_ul_bwp = 1; dci_cfg.nof_ul_bwp = 0;
dci_cfg.nof_ul_time_res = (pusch.nof_dedicated_time_ra > 0) dci_cfg.nof_ul_time_res = (pusch.nof_dedicated_time_ra > 0)
? pusch.nof_dedicated_time_ra ? pusch.nof_dedicated_time_ra
: (pusch.nof_common_time_ra > 0) ? pusch.nof_common_time_ra : SRSRAN_MAX_NOF_TIME_RA; : (pusch.nof_common_time_ra > 0) ? pusch.nof_common_time_ra : SRSRAN_MAX_NOF_TIME_RA;
dci_cfg.nof_srs = 1; dci_cfg.nof_srs = 1;
dci_cfg.nof_ul_layers = 1; dci_cfg.nof_ul_layers = 1;
dci_cfg.nof_rb_groups = 1; dci_cfg.pusch_nof_cbg = 0;
dci_cfg.report_trigger_size = 0;
dci_cfg.enable_transform_precoding = false;
dci_cfg.dynamic_dual_harq_ack_codebook = false;
dci_cfg.pusch_tx_config_non_codebook = false;
dci_cfg.pusch_dmrs_type2 = false;
dci_cfg.pusch_dmrs_double = false;
dci_cfg.pusch_ptrs = false;
dci_cfg.pusch_dynamic_betas = false;
dci_cfg.pusch_alloc_type = pusch.alloc; dci_cfg.pusch_alloc_type = pusch.alloc;
// Format 1_1 specific configuration (for PDSCH only) // Format 1_1 specific configuration (for PDSCH only)
dci_cfg.nof_dl_bwp = 1; dci_cfg.nof_dl_bwp = 0;
dci_cfg.pdsch_alloc_type = pdsch.alloc;
dci_cfg.nof_dl_time_res = (pdsch.nof_dedicated_time_ra > 0) dci_cfg.nof_dl_time_res = (pdsch.nof_dedicated_time_ra > 0)
? pdsch.nof_dedicated_time_ra ? pdsch.nof_dedicated_time_ra
: (pdsch.nof_common_time_ra > 0) ? pdsch.nof_common_time_ra : SRSRAN_MAX_NOF_TIME_RA; : (pdsch.nof_common_time_ra > 0) ? pdsch.nof_common_time_ra : SRSRAN_MAX_NOF_TIME_RA;
dci_cfg.nof_aperiodic_zp = 0; dci_cfg.nof_aperiodic_zp = 0;
dci_cfg.pdsch_nof_cbg = 0;
dci_cfg.nof_dl_to_ul_ack = harq_ack.nof_dl_data_to_ul_ack;
dci_cfg.pdsch_inter_prb_to_prb = false;
dci_cfg.pdsch_rm_pattern1 = false;
dci_cfg.pdsch_rm_pattern2 = false;
dci_cfg.pdsch_2cw = false;
dci_cfg.multiple_scell = false;
dci_cfg.pdsch_dmrs_type2 = false;
dci_cfg.pdsch_dmrs_double = false;
dci_cfg.pdsch_tci = false;
dci_cfg.pdsch_cbg_flush = false;
dci_cfg.pdsch_dynamic_bundling = false;
dci_cfg.pdsch_alloc_type = pdsch.alloc;
return dci_cfg; return dci_cfg;
}; };

@ -143,8 +143,9 @@ void cc_worker::decode_pdcch_dl()
if (logger.debug.enabled()) { if (logger.debug.enabled()) {
for (uint32_t i = 0; i < ue_dl.pdcch_info_count; i++) { for (uint32_t i = 0; i < ue_dl.pdcch_info_count; i++) {
const srsran_ue_dl_nr_pdcch_info_t* info = &ue_dl.pdcch_info[i]; const srsran_ue_dl_nr_pdcch_info_t* info = &ue_dl.pdcch_info[i];
logger.debug("PDCCH: rnti=0x%x, crst_id=%d, ss_type=%d, ncce=%d, al=%d, EPRE=%+.2f, RSRP=%+.2f, corr=%.3f; " logger.debug("PDCCH: dci=%s, rnti=%x, crst_id=%d, ss_type=%d, ncce=%d, al=%d, EPRE=%+.2f, RSRP=%+.2f, corr=%.3f; "
"nof_bits=%d; crc=%s;", "nof_bits=%d; crc=%s;",
srsran_dci_format_nr_string(info->dci_ctx.format),
info->dci_ctx.rnti, info->dci_ctx.rnti,
info->dci_ctx.coreset_id, info->dci_ctx.coreset_id,
info->dci_ctx.ss_type, info->dci_ctx.ss_type,

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