nr,gnb: generation of CORESET#0 and SearchSpace#0 parameters in rrc. Passing CORESET#0/SS#0 to scheduler

srsgnb/hdr/stack/mac/sched_nr_cfg.h

@@ -16,6 +16,7 @@
 #include "sched_nr_interface.h"
 #include "sched_nr_rb.h"
 #include "srsenb/hdr/common/common_enb.h"
+#include "srsran/adt/optional_array.h"
 
 namespace srsenb {
 
@@ -91,6 +92,8 @@ struct bwp_params_t {
 
   bwp_cce_pos_list rar_cce_list;
 
+  srsran::optional_vector<bwp_cce_pos_list> common_cce_list;
+
   bwp_params_t(const cell_cfg_t& cell, const sched_args_t& sched_cfg_, uint32_t cc, uint32_t bwp_id);
 };
 

srsgnb/hdr/stack/mac/sched_nr_pdcch.h

@@ -63,7 +63,9 @@ private:
   uint32_t                coreset_id;
   uint32_t                slot_idx;
   uint32_t                nof_freq_res = 0;
-  const bwp_cce_pos_list& rar_cce_list;
+
+  const bwp_cce_pos_list&                          rar_cce_list;
+  const srsran::optional_vector<bwp_cce_pos_list>& common_cce_list;
 
   // List of PDCCH grants
   struct alloc_record {

srsgnb/src/stack/mac/sched_nr_cfg.cc

@@ -89,6 +89,24 @@ bwp_params_t::bwp_params_t(const cell_cfg_t& cell, const sched_args_t& sched_cfg
       rar_cce_list[sl][agg_idx].resize(n);
     }
   }
+
+  for (uint32_t ss_id = 0; ss_id < SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE; ++ss_id) {
+    if (cell_cfg.bwps[0].pdcch.search_space_present[ss_id]) {
+      auto& ss      = cell_cfg.bwps[0].pdcch.search_space[ss_id];
+      auto& coreset = cell_cfg.bwps[0].pdcch.coreset[ss.coreset_id];
+      common_cce_list.emplace(ss_id);
+      bwp_cce_pos_list& ss_cce_list = common_cce_list[ss_id];
+      for (uint32_t sl = 0; sl < SRSRAN_NOF_SF_X_FRAME; ++sl) {
+        for (uint32_t agg_idx = 0; agg_idx < MAX_NOF_AGGR_LEVELS; ++agg_idx) {
+          ss_cce_list[sl][agg_idx].resize(SRSRAN_SEARCH_SPACE_MAX_NOF_CANDIDATES_NR);
+          int n = srsran_pdcch_nr_locations_coreset(
+              &coreset, &ss, SRSRAN_SIRNTI, agg_idx, sl, ss_cce_list[sl][agg_idx].data());
+          srsran_assert(n >= 0, "Failed to configure DCI locations of search space id=%d", ss_id);
+          ss_cce_list[sl][agg_idx].resize(n);
+        }
+      }
+    }
+  }
 }
 
 cell_params_t::cell_params_t(uint32_t cc_, const cell_cfg_t& cell, const sched_args_t& sched_cfg_) :

srsgnb/src/stack/mac/sched_nr_grant_allocator.cc

@@ -80,7 +80,7 @@ alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx, uint32_t si_idx, ui
   const uint32_t coreset_id = 0;
   const uint32_t ss_id      = 0;
   if (not bwp_pdcch_slot.coresets[coreset_id]->alloc_dci(pdcch_grant_type_t::sib, aggr_idx, ss_id)) {
-    logger.warning("SCHED: Cannot allocate SIB1.");
+    logger.warning("SCHED: Cannot allocate SIB1 due to lack of PDCCH space.");
     return alloc_result::no_cch_space;
   }
 
@@ -101,7 +101,12 @@ alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx, uint32_t si_idx, ui
   slot_cfg.idx = pdcch_slot.to_uint();
   int code     = srsran_ra_dl_dci_to_grant_nr(
       &cfg.cell_cfg.carrier, &slot_cfg, &cfg.cfg.pdsch, &pdcch.dci, &pdsch.sch, &pdsch.sch.grant);
-  srsran_assert(code == SRSRAN_SUCCESS, "Error converting DCI to grant");
+  if (code != SRSRAN_SUCCESS) {
+    logger.warning("Error generating SIB PDSCH grant.");
+    bwp_pdcch_slot.coresets[coreset_id]->rem_last_dci();
+    bwp_pdcch_slot.dl.phy.pdsch.pop_back();
+    return alloc_result::other_cause;
+  }
 
   // Store SI msg index
   bwp_pdcch_slot.sib_idxs.push_back(si_idx);

srsgnb/src/stack/mac/sched_nr_pdcch.cc

@@ -25,7 +25,8 @@ coreset_region::coreset_region(const bwp_params_t& bwp_cfg_,
   slot_idx(slot_idx_),
   pdcch_dl_list(dl_list_),
   pdcch_ul_list(ul_list_),
-  rar_cce_list(bwp_cfg_.rar_cce_list)
+  rar_cce_list(bwp_cfg_.rar_cce_list),
+  common_cce_list(bwp_cfg_.common_cce_list)
 {
   const bool* res_active = &coreset_cfg->freq_resources[0];
   nof_freq_res           = std::count(res_active, res_active + SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE, true);
@@ -182,6 +183,8 @@ srsran::span<const uint32_t> coreset_region::get_cce_loc_table(const alloc_recor
       return record.ue->cce_pos_list(record.ss_id, slot_idx, record.aggr_idx);
     case pdcch_grant_type_t::rar:
       return rar_cce_list[slot_idx][record.aggr_idx];
+    case pdcch_grant_type_t::sib:
+      return common_cce_list[record.ss_id][slot_idx][record.aggr_idx];
     default:
       break;
   }

srsgnb/src/stack/mac/sched_nr_signalling.cc

@@ -130,7 +130,7 @@ si_sched::si_sched(const bwp_params_t& bwp_cfg_) :
   pending_sis[0].n       = 0;
   pending_sis[0].len     = 77;
   pending_sis[0].period  = 160;
-  pending_sis[0].win_len = 1;
+  pending_sis[0].win_len = 160;
 }
 
 void si_sched::run_slot(bwp_slot_allocator& bwp_alloc)
@@ -166,7 +166,7 @@ void si_sched::run_slot(bwp_slot_allocator& bwp_alloc)
     } else if (si.win_start + si.win_len >= sl_pdcch) {
       // If end of SI message window
       if (si.n == 0) {
-        logger.error("SCHED: Could not allocate SIB1, len=%d. Cause: %s", si.n, si.len, to_string(si.result));
+        logger.error("SCHED: Could not allocate SIB1, len=%d. Cause: %s", si.len, to_string(si.result));
       } else {
         logger.warning(
             "SCHED: Could not allocate SI message idx=%d, len=%d. Cause: %s", si.n, si.len, to_string(si.result));

srsgnb/src/stack/rrc/rrc_nr.cc

@@ -45,6 +45,31 @@ int rrc_nr::init(const rrc_nr_cfg_t&         cfg_,
   rrc_eutra = rrc_eutra_;
 
   cfg = cfg_;
+  if (cfg.is_standalone) {
+    // Generate parameters of Coreset#0 and SS#0
+    // Taken from TS 38.211, Section 7.3.2.2
+    cfg.cell_list[0].phy_cell.pdcch.coreset_present[0]              = true;
+    cfg.cell_list[0].phy_cell.pdcch.coreset[0].id                   = 0;
+    cfg.cell_list[0].phy_cell.pdcch.coreset[0].mapping_type         = srsran_coreset_mapping_type_interleaved;
+    cfg.cell_list[0].phy_cell.pdcch.coreset[0].reg_bundle_size      = srsran_coreset_bundle_size_n6;
+    cfg.cell_list[0].phy_cell.pdcch.coreset[0].interleaver_size     = srsran_coreset_bundle_size_n2;
+    cfg.cell_list[0].phy_cell.pdcch.coreset[0].shift_index          = cfg.cell_list[0].phy_cell.cell_id;
+    cfg.cell_list[0].phy_cell.pdcch.coreset[0].precoder_granularity = srsran_coreset_precoder_granularity_reg_bundle;
+    for (uint32_t i = 0; i < SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE; i++) {
+      cfg.cell_list[0].phy_cell.pdcch.coreset[0].freq_resources[i] = true;
+    }
+    cfg.cell_list[0].phy_cell.pdcch.coreset[0].duration               = 1;
+    cfg.cell_list[0].phy_cell.pdcch.search_space_present[0]           = true;
+    cfg.cell_list[0].phy_cell.pdcch.search_space[0].id                = 0;
+    cfg.cell_list[0].phy_cell.pdcch.search_space[0].coreset_id        = 0;
+    cfg.cell_list[0].phy_cell.pdcch.search_space[0].type              = srsran_search_space_type_common_0;
+    cfg.cell_list[0].phy_cell.pdcch.search_space[0].nof_candidates[0] = 1;
+    cfg.cell_list[0].phy_cell.pdcch.search_space[0].nof_candidates[1] = 1;
+    cfg.cell_list[0].phy_cell.pdcch.search_space[0].nof_candidates[2] = 1;
+    cfg.cell_list[0].phy_cell.pdcch.search_space[0].formats[0]        = srsran_dci_format_nr_1_0;
+    cfg.cell_list[0].phy_cell.pdcch.search_space[0].nof_formats       = 1;
+    cfg.cell_list[0].phy_cell.pdcch.search_space[0].duration          = 1;
+  }
 
   cell_ctxt.reset(new cell_ctxt_t{});
 
@@ -60,10 +85,15 @@ int rrc_nr::init(const rrc_nr_cfg_t&         cfg_,
   int ret = fill_sp_cell_cfg_from_enb_cfg(cfg, UE_PSCELL_CC_IDX, base_sp_cell_cfg);
   srsran_assert(ret == SRSRAN_SUCCESS, "Failed to configure cell");
 
-  // Fill rrc_nr_cfg with UE-specific search spaces and coresets
+  pdcch_cfg_common_s* asn1_pdcch;
-  bool ret2 = srsran::fill_phy_pdcch_cfg_common(
+  if (not cfg.is_standalone) {
-      base_sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.init_dl_bwp.pdcch_cfg_common.setup(),
+    // Fill rrc_nr_cfg with UE-specific search spaces and coresets
-      &cfg.cell_list[0].phy_cell.pdcch);
+    asn1_pdcch =
+        &base_sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.dl_cfg_common.init_dl_bwp.pdcch_cfg_common.setup();
+  } else {
+    asn1_pdcch = &cell_ctxt->sib1.serving_cell_cfg_common.dl_cfg_common.init_dl_bwp.pdcch_cfg_common.setup();
+  }
+  bool ret2 = srsran::fill_phy_pdcch_cfg_common(*asn1_pdcch, &cfg.cell_list[0].phy_cell.pdcch);
   srsran_assert(ret2, "Invalid NR cell configuration.");
   ret2 = srsran::fill_phy_pdcch_cfg(base_sp_cell_cfg.sp_cell_cfg_ded.init_dl_bwp.pdcch_cfg.setup(),
                                     &cfg.cell_list[0].phy_cell.pdcch);
@@ -297,6 +327,10 @@ int32_t rrc_nr::generate_sibs()
     cell_ctxt->mib_buffer = std::move(mib_buf);
   }
 
+  if (not cfg.is_standalone) {
+    return SRSRAN_SUCCESS;
+  }
+
   // SIB1 packing
   fill_sib1_from_enb_cfg(cfg, cell_ctxt->sib1);
   si_sched_info_s::sched_info_list_l_& sched_info = cell_ctxt->sib1.si_sched_info.sched_info_list;