sched,nr: fix Msg3 decoding in PHY to not expect any UCI

master
Francisco Paisana 3 years ago
parent d8d99054d5
commit 2668a8f68b

@ -44,6 +44,7 @@ typedef struct {
/** /**
* @brief Uplink Control Information bits configuration for PUSCH transmission * @brief Uplink Control Information bits configuration for PUSCH transmission
* @attention Set nof_layers, nof_re or R to 0 to indicate this structure is not initialised.
*/ */
typedef struct { typedef struct {
uint32_t l0; ///< First OFDM symbol that does not carry DMRS of the PUSCH, after the first DMRS symbol(s) uint32_t l0; ///< First OFDM symbol that does not carry DMRS of the PUSCH, after the first DMRS symbol(s)
@ -53,12 +54,12 @@ typedef struct {
uint32_t K_sum; ///< Sum of UL-SCH code block sizes, set to zero if no UL-SCH uint32_t K_sum; ///< Sum of UL-SCH code block sizes, set to zero if no UL-SCH
srsran_mod_t modulation; ///< Modulation for the PUSCH srsran_mod_t modulation; ///< Modulation for the PUSCH
uint32_t nof_layers; ///< Number of layers for PUSCH uint32_t nof_layers; ///< Number of layers for PUSCH
uint32_t nof_re; ///< Total number of resource elements allocated for the grant
float R; ///< Code rate of the PUSCH float R; ///< Code rate of the PUSCH
float alpha; ///< Higher layer parameter scaling float alpha; ///< Higher layer parameter scaling
float beta_harq_ack_offset; float beta_harq_ack_offset;
float beta_csi1_offset; float beta_csi1_offset;
float beta_csi2_offset; float beta_csi2_offset;
uint32_t nof_re;
bool csi_part2_present; bool csi_part2_present;
} srsran_uci_nr_pusch_cfg_t; } srsran_uci_nr_pusch_cfg_t;

@ -33,6 +33,40 @@ uint32_t srsran_uci_nr_crc_len(uint32_t A)
return (A <= 11) ? 0 : (A < 20) ? 6 : 11; return (A <= 11) ? 0 : (A < 20) ? 6 : 11;
} }
static inline int uci_nr_pusch_cfg_valid(const srsran_uci_nr_pusch_cfg_t* cfg)
{
// No data pointer
if (cfg == NULL) {
return SRSRAN_ERROR_INVALID_INPUTS;
}
// Unset configuration is unset
if (cfg->nof_re == 0 && cfg->nof_layers == 0 && !isnormal(cfg->R)) {
return SRSRAN_SUCCESS;
}
// Detect invalid number of layers
if (cfg->nof_layers == 0) {
ERROR("Invalid number of layers %d", cfg->nof_layers);
return SRSRAN_ERROR;
}
// Detect invalid number of RE
if (cfg->nof_re == 0) {
ERROR("Invalid number of RE %d", cfg->nof_re);
return SRSRAN_ERROR;
}
// Detect invalid Rate
if (!isnormal(cfg->R)) {
ERROR("Invalid R %f", cfg->R);
return SRSRAN_ERROR;
}
// Otherwise it is set and valid
return 1;
}
int srsran_uci_nr_init(srsran_uci_nr_t* q, const srsran_uci_nr_args_t* args) int srsran_uci_nr_init(srsran_uci_nr_t* q, const srsran_uci_nr_args_t* args)
{ {
if (q == NULL || args == NULL) { if (q == NULL || args == NULL) {
@ -1015,10 +1049,6 @@ uint32_t srsran_uci_nr_info(const srsran_uci_data_nr_t* uci_data, char* str, uin
static int uci_nr_pusch_Q_prime_ack(const srsran_uci_nr_pusch_cfg_t* cfg, uint32_t O_ack) static int uci_nr_pusch_Q_prime_ack(const srsran_uci_nr_pusch_cfg_t* cfg, uint32_t O_ack)
{ {
if (cfg == NULL) {
return SRSRAN_ERROR_INVALID_INPUTS;
}
uint32_t L_ack = srsran_uci_nr_crc_len(O_ack); // Number of CRC bits uint32_t L_ack = srsran_uci_nr_crc_len(O_ack); // Number of CRC bits
uint32_t Qm = srsran_mod_bits_x_symbol(cfg->modulation); // modulation order of the PUSCH uint32_t Qm = srsran_mod_bits_x_symbol(cfg->modulation); // modulation order of the PUSCH
@ -1046,14 +1076,15 @@ static int uci_nr_pusch_Q_prime_ack(const srsran_uci_nr_pusch_cfg_t* cfg, uint32
int srsran_uci_nr_pusch_ack_nof_bits(const srsran_uci_nr_pusch_cfg_t* cfg, uint32_t O_ack) int srsran_uci_nr_pusch_ack_nof_bits(const srsran_uci_nr_pusch_cfg_t* cfg, uint32_t O_ack)
{ {
// Check inputs // Validate configuration
if (cfg == NULL) { int err = uci_nr_pusch_cfg_valid(cfg);
if (err < SRSRAN_SUCCESS) {
return SRSRAN_ERROR_INVALID_INPUTS; return SRSRAN_ERROR_INVALID_INPUTS;
} }
if (cfg->nof_layers == 0) { // Configuration is unset
ERROR("Invalid number of layers (%d)", cfg->nof_layers); if (err == 0) {
return SRSRAN_ERROR; return 0;
} }
int Q_ack_prime = uci_nr_pusch_Q_prime_ack(cfg, O_ack); int Q_ack_prime = uci_nr_pusch_Q_prime_ack(cfg, O_ack);
@ -1177,11 +1208,17 @@ static int uci_nr_pusch_Q_prime_csi1(const srsran_uci_nr_pusch_cfg_t* cfg, uint3
int srsran_uci_nr_pusch_csi1_nof_bits(const srsran_uci_cfg_nr_t* cfg) int srsran_uci_nr_pusch_csi1_nof_bits(const srsran_uci_cfg_nr_t* cfg)
{ {
// Check inputs // Validate configuration
if (cfg == NULL) { int err = uci_nr_pusch_cfg_valid(&cfg->pusch);
if (err < SRSRAN_SUCCESS) {
return SRSRAN_ERROR_INVALID_INPUTS; return SRSRAN_ERROR_INVALID_INPUTS;
} }
// Configuration is unset
if (err == 0) {
return 0;
}
int O_csi1 = srsran_csi_part1_nof_bits(cfg->csi, cfg->nof_csi); int O_csi1 = srsran_csi_part1_nof_bits(cfg->csi, cfg->nof_csi);
if (O_csi1 < SRSRAN_SUCCESS) { if (O_csi1 < SRSRAN_SUCCESS) {
ERROR("Errpr calculating CSI part 1 number of bits"); ERROR("Errpr calculating CSI part 1 number of bits");

@ -174,13 +174,6 @@ void ra_sched::run_slot(bwp_slot_allocator& slot_grid, slot_ue_map_t& slot_ues)
/// See TS 38.321, 5.1.3 - RAP transmission /// See TS 38.321, 5.1.3 - RAP transmission
int ra_sched::dl_rach_info(const dl_sched_rar_info_t& rar_info) int ra_sched::dl_rach_info(const dl_sched_rar_info_t& rar_info)
{ {
logger.info("SCHED: New PRACH slot=%d, preamble=%d, temp_crnti=0x%x, ta_cmd=%d, msg3_size=%d",
rar_info.prach_slot.to_uint(),
rar_info.preamble_idx,
rar_info.temp_crnti,
rar_info.ta_cmd,
rar_info.msg3_size);
// RA-RNTI = 1 + s_id + 14 × t_id + 14 × 80 × f_id + 14 × 80 × 8 × ul_carrier_id // RA-RNTI = 1 + s_id + 14 × t_id + 14 × 80 × f_id + 14 × 80 × 8 × ul_carrier_id
// s_id = index of the first OFDM symbol (0 <= s_id < 14) // s_id = index of the first OFDM symbol (0 <= s_id < 14)
// t_id = index of first slot of the PRACH (0 <= t_id < 80) // t_id = index of first slot of the PRACH (0 <= t_id < 80)
@ -188,6 +181,14 @@ int ra_sched::dl_rach_info(const dl_sched_rar_info_t& rar_info)
// ul_carrier_id = 0 for NUL and 1 for SUL carrier // ul_carrier_id = 0 for NUL and 1 for SUL carrier
uint16_t ra_rnti = 1 + rar_info.ofdm_symbol_idx + 14 * rar_info.prach_slot.slot_idx() + 14 * 80 * rar_info.freq_idx; uint16_t ra_rnti = 1 + rar_info.ofdm_symbol_idx + 14 * rar_info.prach_slot.slot_idx() + 14 * 80 * rar_info.freq_idx;
logger.info("SCHED: New PRACH slot=%d, preamble=%d, ra-rnti=0x%x, temp_crnti=0x%x, ta_cmd=%d, msg3_size=%d",
rar_info.prach_slot.to_uint(),
rar_info.preamble_idx,
ra_rnti,
rar_info.temp_crnti,
rar_info.ta_cmd,
rar_info.msg3_size);
// find pending rar with same RA-RNTI // find pending rar with same RA-RNTI
for (pending_rar_t& r : pending_rars) { for (pending_rar_t& r : pending_rars) {
if (r.prach_slot == rar_info.prach_slot and ra_rnti == r.ra_rnti) { if (r.prach_slot == rar_info.prach_slot and ra_rnti == r.ra_rnti) {

@ -136,20 +136,21 @@ void slot_cc_worker::log_result() const
fmt::memory_buffer fmtbuf; fmt::memory_buffer fmtbuf;
if (pdcch.dci.ctx.rnti_type == srsran_rnti_type_c) { if (pdcch.dci.ctx.rnti_type == srsran_rnti_type_c) {
const slot_ue& ue = slot_ues[pdcch.dci.ctx.rnti]; const slot_ue& ue = slot_ues[pdcch.dci.ctx.rnti];
fmt::format_to(fmtbuf, fmt::format_to(
"SCHED: DL {}, cc={}, rnti=0x{:x}, pid={}, f={}, nrtx={}, dai={}, tbs={}, tti_pdsch={}, tti_ack={}", fmtbuf,
ue.h_dl->nof_retx() == 0 ? "tx" : "retx", "SCHED: DL {}, cc={}, rnti=0x{:x}, pid={}, f={}, nrtx={}, dai={}, tbs={}, tti_pdsch={}, tti_ack={}",
cell.cfg.cc, ue.h_dl->nof_retx() == 0 ? "tx" : "retx",
ue.rnti, cell.cfg.cc,
pdcch.dci.pid, ue.rnti,
srsran_dci_format_nr_string(pdcch.dci.ctx.format), pdcch.dci.pid,
ue.h_dl->nof_retx(), srsran_dci_format_nr_string(pdcch.dci.ctx.format),
pdcch.dci.dai, ue.h_dl->nof_retx(),
ue.h_dl->tbs(), pdcch.dci.dai,
ue.pdsch_slot, ue.h_dl->tbs(),
ue.uci_slot); ue.pdsch_slot,
ue.uci_slot);
} else if (pdcch.dci.ctx.rnti_type == srsran_rnti_type_ra) { } else if (pdcch.dci.ctx.rnti_type == srsran_rnti_type_ra) {
fmt::format_to(fmtbuf, "SCHED: DL RAR, cc={}", cell.cfg.cc); fmt::format_to(fmtbuf, "SCHED: DL RAR, cc={}, ra-rnti=0x{:x}", cell.cfg.cc, pdcch.dci.ctx.rnti);
} else { } else {
fmt::format_to(fmtbuf, "SCHED: unknown format"); fmt::format_to(fmtbuf, "SCHED: unknown format");
} }

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