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Enhanced NR PHY test

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master
Xavier Arteaga 3 years ago committed by Andre Puschmann
parent d12085e8a7
commit 248a52b33d
2 changed files with 60 additions and 54 deletions
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87
test/phy/dummy_gnb_stack.h
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@ -27,20 +27,19 @@
class gnb_dummy_stack : public srsenb::stack_interface_phy_nr class gnb_dummy_stack : public srsenb::stack_interface_phy_nr
{ {
private: private:
srslog::basic_logger& logger = srslog::fetch_basic_logger("GNB STK"); srslog::basic_logger& logger = srslog::fetch_basic_logger("GNB STK");
const uint16_t rnti = 0x1234; const uint16_t rnti = 0x1234;
const uint32_t mcs = 1; struct {
srsran::circular_array<srsran_dci_location_t, SRSRAN_NOF_SF_X_FRAME> dci_dl_location; srsran::circular_array<srsran_dci_location_t, SRSRAN_NOF_SF_X_FRAME> dci_location;
srsran::circular_array<srsran_dci_location_t, SRSRAN_NOF_SF_X_FRAME> dci_ul_location; uint32_t mcs;
srsran::circular_array<uint32_t, SRSRAN_NOF_SF_X_FRAME> dl_data_to_ul_ack; uint32_t freq_res = 0;
uint32_t ss_id = 0; std::set<uint32_t> slots;
uint32_t dl_freq_res = 0; } dl, ul;
uint32_t ul_freq_res = 0; srsran::circular_array<uint32_t, SRSRAN_NOF_SF_X_FRAME> dl_data_to_ul_ack;
srsran_random_t random_gen = nullptr; uint32_t ss_id = 0;
srsran::phy_cfg_nr_t phy_cfg = {}; srsran_random_t random_gen = nullptr;
bool valid = false; srsran::phy_cfg_nr_t phy_cfg = {};
std::set<uint32_t> dl_slots; bool valid = false;
std::set<uint32_t> ul_slots;
std::mutex mac_metrics_mutex; std::mutex mac_metrics_mutex;
srsenb::mac_ue_metrics_t mac_metrics = {}; srsenb::mac_ue_metrics_t mac_metrics = {};
@ -120,7 +119,7 @@ private:
bool schedule_pdsch(const srsran_slot_cfg_t& slot_cfg, dl_sched_t& dl_sched) bool schedule_pdsch(const srsran_slot_cfg_t& slot_cfg, dl_sched_t& dl_sched)
{ {
if (dl_slots.count(SRSRAN_SLOT_NR_MOD(srsran_subcarrier_spacing_15kHz, slot_cfg.idx)) == 0) { if (dl.slots.count(SRSRAN_SLOT_NR_MOD(srsran_subcarrier_spacing_15kHz, slot_cfg.idx)) == 0) {
return true; return true;
} }
@ -135,7 +134,7 @@ private:
pdcch.dci_cfg = phy_cfg.get_dci_cfg(); pdcch.dci_cfg = phy_cfg.get_dci_cfg();
// Fill DCI context // Fill DCI context
if (not phy_cfg.get_dci_ctx_pdsch_rnti_c(ss_id, dci_dl_location[slot_cfg.idx], rnti, pdcch.dci.ctx)) { if (not phy_cfg.get_dci_ctx_pdsch_rnti_c(ss_id, dl.dci_location[slot_cfg.idx], rnti, pdcch.dci.ctx)) {
logger.error("Error filling PDSCH DCI context"); logger.error("Error filling PDSCH DCI context");
return false; return false;
} }
@ -145,9 +144,9 @@ private:
// Fill DCI fields // Fill DCI fields
srsran_dci_dl_nr_t& dci = pdcch.dci; srsran_dci_dl_nr_t& dci = pdcch.dci;
dci.freq_domain_assigment = dl_freq_res; dci.freq_domain_assigment = dl.freq_res;
dci.time_domain_assigment = 0; dci.time_domain_assigment = 0;
dci.mcs = mcs; dci.mcs = dl.mcs;
dci.rv = 0; dci.rv = 0;
dci.ndi = (slot_cfg.idx / SRSRAN_NOF_SF_X_FRAME) % 2; dci.ndi = (slot_cfg.idx / SRSRAN_NOF_SF_X_FRAME) % 2;
dci.pid = slot_cfg.idx % SRSRAN_NOF_SF_X_FRAME; dci.pid = slot_cfg.idx % SRSRAN_NOF_SF_X_FRAME;
@ -198,7 +197,7 @@ private:
bool schedule_pusch(const srsran_slot_cfg_t& slot_cfg, dl_sched_t& dl_sched) bool schedule_pusch(const srsran_slot_cfg_t& slot_cfg, dl_sched_t& dl_sched)
{ {
if (ul_slots.count(SRSRAN_SLOT_NR_MOD(srsran_subcarrier_spacing_15kHz, slot_cfg.idx + 4)) == 0) { if (ul.slots.count(SRSRAN_SLOT_NR_MOD(srsran_subcarrier_spacing_15kHz, slot_cfg.idx + 4)) == 0) {
return true; return true;
} }
@ -209,17 +208,17 @@ private:
pdcch.dci_cfg = phy_cfg.get_dci_cfg(); pdcch.dci_cfg = phy_cfg.get_dci_cfg();
// Fill DCI context // Fill DCI context
if (not phy_cfg.get_dci_ctx_pusch_rnti_c(ss_id, dci_ul_location[slot_cfg.idx], rnti, pdcch.dci.ctx)) { if (not phy_cfg.get_dci_ctx_pusch_rnti_c(ss_id, ul.dci_location[slot_cfg.idx], rnti, pdcch.dci.ctx)) {
logger.error("Error filling PDSCH DCI context"); logger.error("Error filling PDSCH DCI context");
return false; return false;
} }
// Fill DCI fields // Fill DCI fields
srsran_dci_ul_nr_t& dci = pdcch.dci; srsran_dci_ul_nr_t& dci = pdcch.dci;
dci.freq_domain_assigment = ul_freq_res; dci.freq_domain_assigment = ul.freq_res;
dci.time_domain_assigment = 0; dci.time_domain_assigment = 0;
dci.freq_hopping_flag = 0; dci.freq_hopping_flag = 0;
dci.mcs = mcs; dci.mcs = ul.mcs;
dci.rv = 0; dci.rv = 0;
dci.ndi = (slot_cfg.idx / SRSRAN_NOF_SF_X_FRAME) % 2; dci.ndi = (slot_cfg.idx / SRSRAN_NOF_SF_X_FRAME) % 2;
dci.pid = slot_cfg.idx % SRSRAN_NOF_SF_X_FRAME; dci.pid = slot_cfg.idx % SRSRAN_NOF_SF_X_FRAME;
@ -265,29 +264,31 @@ private:
public: public:
struct args_t { struct args_t {
srsran::phy_cfg_nr_t phy_cfg; ///< Physical layer configuration srsran::phy_cfg_nr_t phy_cfg; ///< Physical layer configuration
uint16_t rnti = 0x1234; ///< C-RNTI uint16_t rnti = 0x1234; ///< C-RNTI
uint32_t mcs = 10; ///< Modulation code scheme uint32_t ss_id = 1; ///< Search Space identifier
uint32_t ss_id = 1; ///< Search Space identifier uint32_t pdcch_aggregation_level = 0; ///< PDCCH aggregation level
uint32_t pdcch_aggregation_level = 0; ///< PDCCH aggregation level uint32_t pdcch_dl_candidate = 0; ///< PDCCH DL DCI candidate index
uint32_t pdcch_dl_candidate = 0; ///< PDCCH DL DCI candidate index uint32_t pdcch_ul_candidate = 1; ///< PDCCH UL DCI candidate index
uint32_t pdcch_ul_candidate = 1; ///< PDCCH UL DCI candidate index struct {
uint32_t dl_start_rb = 0; ///< Start resource block uint32_t rb_start = 0; ///< Start frequency domain resource block
uint32_t dl_length_rb = 0; ///< Number of resource blocks uint32_t rb_length = 10; ///< Number of frequency domain resource blocks
std::string dl_sched_slots = "0,1,2,3,4,5"; ///< PDCH Slot list uint32_t mcs = 10; ///< Modulation code scheme
uint32_t ul_start_rb = 0; ///< Start resource block std::string slots = ""; ///< Slot list, empty string means no scheduling
uint32_t ul_length_rb = 0; ///< Number of resource blocks } pdsch, pusch;
std::string ul_sched_slots = "6,7,8,9"; ///< Slot list std::string log_level = "warning";
std::string log_level = "warning";
}; };
gnb_dummy_stack(const args_t& args) : mcs(args.mcs), rnti(args.rnti), phy_cfg(args.phy_cfg), ss_id(args.ss_id) gnb_dummy_stack(const args_t& args) : rnti(args.rnti), phy_cfg(args.phy_cfg), ss_id(args.ss_id)
{ {
random_gen = srsran_random_init(0x1234); random_gen = srsran_random_init(0x1234);
logger.set_level(srslog::str_to_basic_level(args.log_level)); logger.set_level(srslog::str_to_basic_level(args.log_level));
srsran::string_parse_list(args.dl_sched_slots, ',', dl_slots); dl.mcs = args.pdsch.mcs;
srsran::string_parse_list(args.ul_sched_slots, ',', ul_slots); ul.mcs = args.pusch.mcs;
srsran::string_parse_list(args.pdsch.slots, ',', dl.slots);
srsran::string_parse_list(args.pusch.slots, ',', ul.slots);
// Select DCI locations // Select DCI locations
for (uint32_t slot = 0; slot < SRSRAN_NOF_SF_X_FRAME; slot++) { for (uint32_t slot = 0; slot < SRSRAN_NOF_SF_X_FRAME; slot++) {
@ -307,7 +308,7 @@ public:
args.pdcch_aggregation_level); args.pdcch_aggregation_level);
return; return;
} }
dci_dl_location[slot] = locations[args.pdcch_dl_candidate]; dl.dci_location[slot] = locations[args.pdcch_dl_candidate];
// DCI UL // DCI UL
if (args.pdcch_ul_candidate >= locations.size()) { if (args.pdcch_ul_candidate >= locations.size()) {
@ -317,14 +318,14 @@ public:
args.pdcch_aggregation_level); args.pdcch_aggregation_level);
return; return;
} }
dci_ul_location[slot] = locations[args.pdcch_ul_candidate]; ul.dci_location[slot] = locations[args.pdcch_ul_candidate];
} }
// Select DL frequency domain resources // Select DL frequency domain resources
dl_freq_res = srsran_ra_nr_type1_riv(args.phy_cfg.carrier.nof_prb, args.dl_start_rb, args.dl_length_rb); dl.freq_res = srsran_ra_nr_type1_riv(args.phy_cfg.carrier.nof_prb, args.pdsch.rb_start, args.pdsch.rb_length);
// Select DL frequency domain resources // Select DL frequency domain resources
ul_freq_res = srsran_ra_nr_type1_riv(args.phy_cfg.carrier.nof_prb, args.ul_start_rb, args.ul_length_rb); ul.freq_res = srsran_ra_nr_type1_riv(args.phy_cfg.carrier.nof_prb, args.pusch.rb_start, args.pusch.rb_length);
// Setup DL Data to ACK timing // Setup DL Data to ACK timing
for (uint32_t i = 0; i < SRSRAN_NOF_SF_X_FRAME; i++) { for (uint32_t i = 0; i < SRSRAN_NOF_SF_X_FRAME; i++) {

27
test/phy/nr_phy_test.cc
Unescape Escape View File

@ -31,6 +31,9 @@ test_bench::args_t::args_t(int argc, char** argv)
uint16_t rnti = 0x1234; uint16_t rnti = 0x1234;
gnb_stack.pdsch.slots = "0,1,2,3,4,5";
gnb_stack.pusch.slots = "6,7,8,9";
// clang-format off // clang-format off
options.add_options() options.add_options()
("rnti", bpo::value<uint16_t>(&rnti)->default_value(rnti), "UE RNTI") ("rnti", bpo::value<uint16_t>(&rnti)->default_value(rnti), "UE RNTI")
@ -40,14 +43,14 @@ test_bench::args_t::args_t(int argc, char** argv)
options_gnb_stack.add_options() options_gnb_stack.add_options()
("gnb.stack.pdcch.aggregation_level", bpo::value<uint32_t>(&gnb_stack.pdcch_aggregation_level)->default_value(gnb_stack.pdcch_aggregation_level), "PDCCH aggregation level") ("gnb.stack.pdcch.aggregation_level", bpo::value<uint32_t>(&gnb_stack.pdcch_aggregation_level)->default_value(gnb_stack.pdcch_aggregation_level), "PDCCH aggregation level")
("gnb.stack.pdsch.candidate", bpo::value<uint32_t>(&gnb_stack.pdcch_dl_candidate)->default_value(gnb_stack.pdcch_dl_candidate), "PDCCH candidate index for PDSCH") ("gnb.stack.pdsch.candidate", bpo::value<uint32_t>(&gnb_stack.pdcch_dl_candidate)->default_value(gnb_stack.pdcch_dl_candidate), "PDCCH candidate index for PDSCH")
("gnb.stack.pdsch.start", bpo::value<uint32_t>(&gnb_stack.dl_start_rb)->default_value(0), "PDSCH scheduling frequency allocation start") ("gnb.stack.pdsch.start", bpo::value<uint32_t>(&gnb_stack.pdsch.rb_start)->default_value(0), "PDSCH scheduling frequency allocation start")
("gnb.stack.pdsch.length", bpo::value<uint32_t>(&gnb_stack.dl_length_rb)->default_value(gnb_stack.dl_length_rb), "PDSCH scheduling frequency allocation length") ("gnb.stack.pdsch.length", bpo::value<uint32_t>(&gnb_stack.pdsch.rb_length)->default_value(gnb_stack.pdsch.rb_length), "PDSCH scheduling frequency allocation length")
("gnb.stack.pdsch.slots", bpo::value<std::string>(&gnb_stack.dl_sched_slots)->default_value(gnb_stack.dl_sched_slots), "Slots enabled for PDSCH") ("gnb.stack.pdsch.slots", bpo::value<std::string>(&gnb_stack.pdsch.slots)->default_value(gnb_stack.pdsch.slots), "Slots enabled for PDSCH")
("gnb.stack.pdsch.mcs", bpo::value<uint32_t>(&gnb_stack.pdsch.mcs)->default_value(gnb_stack.pdsch.mcs), "PDSCH/PUSCH scheduling modulation code scheme")
("gnb.stack.pusch.candidate", bpo::value<uint32_t>(&gnb_stack.pdcch_ul_candidate)->default_value(gnb_stack.pdcch_ul_candidate), "PDCCH candidate index for PUSCH") ("gnb.stack.pusch.candidate", bpo::value<uint32_t>(&gnb_stack.pdcch_ul_candidate)->default_value(gnb_stack.pdcch_ul_candidate), "PDCCH candidate index for PUSCH")
("gnb.stack.pusch.start", bpo::value<uint32_t>(&gnb_stack.ul_start_rb)->default_value(0), "PUSCH scheduling frequency allocation start") ("gnb.stack.pusch.start", bpo::value<uint32_t>(&gnb_stack.pusch.rb_start)->default_value(0), "PUSCH scheduling frequency allocation start")
("gnb.stack.pusch.length", bpo::value<uint32_t>(&gnb_stack.ul_length_rb)->default_value(gnb_stack.ul_length_rb), "PUSCH scheduling frequency allocation length") ("gnb.stack.pusch.length", bpo::value<uint32_t>(&gnb_stack.pusch.rb_length)->default_value(gnb_stack.pusch.rb_length), "PUSCH scheduling frequency allocation length")
("gnb.stack.pusch.slots", bpo::value<std::string>(&gnb_stack.ul_sched_slots)->default_value(gnb_stack.ul_sched_slots), "Slots enabled for PUSCH") ("gnb.stack.pusch.slots", bpo::value<std::string>(&gnb_stack.pusch.slots)->default_value(gnb_stack.pusch.slots), "Slots enabled for PUSCH")
("gnb.stack.mcs", bpo::value<uint32_t>(&gnb_stack.mcs)->default_value(gnb_stack.mcs), "PDSCH/PUSCH scheduling modulation code scheme")
("gnb.stack.log_level", bpo::value<std::string>(&gnb_stack.log_level)->default_value(gnb_stack.log_level), "Stack log level") ("gnb.stack.log_level", bpo::value<std::string>(&gnb_stack.log_level)->default_value(gnb_stack.log_level), "Stack log level")
; ;
@ -102,12 +105,14 @@ test_bench::args_t::args_t(int argc, char** argv)
gnb_stack.rnti = rnti; gnb_stack.rnti = rnti;
gnb_stack.phy_cfg = phy_cfg; gnb_stack.phy_cfg = phy_cfg;
if (gnb_stack.dl_length_rb == 0) { if (gnb_stack.pdsch.rb_length == 0) {
gnb_stack.dl_length_rb = phy_cfg.carrier.nof_prb; gnb_stack.pdsch.rb_length = phy_cfg.carrier.nof_prb;
gnb_stack.pdsch.rb_start = 0;
} }
if (gnb_stack.ul_length_rb == 0) { if (gnb_stack.pusch.rb_length == 0) {
gnb_stack.ul_length_rb = phy_cfg.carrier.nof_prb; gnb_stack.pusch.rb_length = phy_cfg.carrier.nof_prb;
gnb_stack.pdsch.rb_start = 0;
} }
// Flag configuration as valid // Flag configuration as valid

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