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@ -11,6 +11,7 @@
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*/
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*/
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#include "srslte/phy/ue/ue_dl_nr.h"
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#include "srslte/phy/ue/ue_dl_nr.h"
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#include <complex.h>
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#define UE_DL_NR_PDCCH_CORR_DEFAULT_THR 0.5f
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#define UE_DL_NR_PDCCH_CORR_DEFAULT_THR 0.5f
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#define UE_DL_NR_PDCCH_EPRE_DEFAULT_THR -10.0f
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#define UE_DL_NR_PDCCH_EPRE_DEFAULT_THR -10.0f
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@ -196,6 +197,17 @@ void srslte_ue_dl_nr_estimate_fft(srslte_ue_dl_nr_t* q, const srslte_dl_slot_cfg
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srslte_ofdm_rx_sf(&q->fft[i]);
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srslte_ofdm_rx_sf(&q->fft[i]);
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}
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}
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// Temporary symbol phase shift
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uint32_t nof_re = SRSLTE_NRE * q->carrier.nof_prb;
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for (uint32_t i = 0; i < 2; i++) {
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for (uint32_t j = 0; j < 7; j++) {
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srslte_vec_sc_prod_ccc(&q->sf_symbols[0][(i * 7 + j) * nof_re],
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cexpf(-I * (11.0f * j - 2.0f) * M_PI / 16),
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&q->sf_symbols[0][(i * 7 + j) * nof_re],
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nof_re);
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}
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}
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// Estimate PDCCH channel for every configured CORESET
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// Estimate PDCCH channel for every configured CORESET
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for (uint32_t i = 0; i < SRSLTE_UE_DL_NR_MAX_NOF_CORESET; i++) {
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for (uint32_t i = 0; i < SRSLTE_UE_DL_NR_MAX_NOF_CORESET; i++) {
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if (q->cfg.coreset_present[i]) {
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if (q->cfg.coreset_present[i]) {
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