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nr,gnb,sched: fix si softbuffer allocation. Add extra comments

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master
Francisco 3 years ago committed by Francisco Paisana
parent 360f718a5e
commit 1807ba1e37
5 changed files with 44 additions and 23 deletions
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8
srsgnb/hdr/stack/mac/sched_nr_grant_allocator.h
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@ -54,8 +54,6 @@ struct bwp_slot_grid {
slot_coreset_list coresets;
harq_ack_list_t pending_acks;
srsran::bounded_vector<uint32_t, MAX_GRANTS> sib_idxs;
srsran::unique_pool_ptr<tx_harq_softbuffer> rar_softbuffer;
bwp_slot_grid() = default;
@ -92,7 +90,11 @@ class bwp_slot_allocator
public:
explicit bwp_slot_allocator(bwp_res_grid& bwp_grid_, slot_point pdcch_slot_, slot_ue_map_t& ues_);
alloc_result alloc_si(uint32_t aggr_idx, uint32_t si_idx, uint32_t si_ntx, const prb_interval& prbs);
alloc_result alloc_si(uint32_t aggr_idx,
uint32_t si_idx,
uint32_t si_ntx,
const prb_interval& prbs,
tx_harq_softbuffer& softbuffer);
alloc_result alloc_rar_and_msg3(uint16_t ra_rnti,
uint32_t aggr_idx,
prb_interval interv,

6
srsgnb/hdr/stack/mac/sched_nr_helpers.h
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@ -25,7 +25,11 @@ struct bwp_res_grid;
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
bool fill_dci_sib(prb_interval interv, uint32_t sib_idx, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci);
bool fill_dci_sib(prb_interval interv,
uint32_t sib_idx,
uint32_t si_ntx,
const bwp_params_t& bwp_cfg,
srsran_dci_dl_nr_t& dci);
bool fill_dci_rar(prb_interval interv, uint16_t ra_rnti, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci);

13
srsgnb/hdr/stack/mac/sched_nr_signalling.h
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@ -13,6 +13,7 @@
#ifndef SRSRAN_SCHED_NR_SIGNALLING_H
#define SRSRAN_SCHED_NR_SIGNALLING_H
#include "harq_softbuffer.h"
#include "sched_nr_cfg.h"
#include "sched_nr_interface.h"
#include "srsenb/hdr/stack/mac/sched_common.h"
@ -63,13 +64,17 @@ private:
srslog::basic_logger& logger;
struct si_msg_ctxt_t {
// args
uint32_t n = 0; /// 0 for SIB1, n/index in schedulingInfoList in si-SchedulingInfo in SIB1
uint32_t len = 0;
uint32_t win_len = 0;
uint32_t period = 0;
uint32_t n_tx = 0;
uint32_t len = 0; /// length in bytes of SIB1 / SI message
uint32_t win_len = 0; /// window length in slots
uint32_t period = 0; /// periodicity of SIB1/SI window
// state
uint32_t n_tx = 0; /// nof transmissions of the same SIB1 / SI message
alloc_result result = alloc_result::invalid_coderate; /// last attempt to schedule SI
slot_point win_start; /// start of SI window, invalid if outside
srsran::unique_pool_ptr<tx_harq_softbuffer> si_softbuffer;
};
srsran::bounded_vector<si_msg_ctxt_t, 10> pending_sis; /// configured SIB1 and SI messages
};

11
srsgnb/src/stack/mac/sched_nr_grant_allocator.cc
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@ -66,7 +66,11 @@ bwp_slot_allocator::bwp_slot_allocator(bwp_res_grid& bwp_grid_, slot_point pdcch
logger(bwp_grid_.cfg->logger), cfg(*bwp_grid_.cfg), bwp_grid(bwp_grid_), pdcch_slot(pdcch_slot_), slot_ues(ues_)
{}
alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx, uint32_t si_idx, uint32_t si_ntx, const prb_interval& prbs)
alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx,
uint32_t si_idx,
uint32_t si_ntx,
const prb_interval& prbs,
tx_harq_softbuffer& softbuffer)
{
bwp_slot_grid& bwp_pdcch_slot = bwp_grid[pdcch_slot];
alloc_result ret = verify_pdsch_space(bwp_pdcch_slot, bwp_pdcch_slot);
@ -88,7 +92,7 @@ alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx, uint32_t si_idx, ui
bwp_pdcch_slot.dl_prbs |= prbs;
// Generate DCI for RAR with given RA-RNTI
pdcch_dl_t& pdcch = bwp_pdcch_slot.dl.phy.pdcch_dl.back();
if (not fill_dci_sib(prbs, si_idx, *bwp_grid.cfg, pdcch.dci)) {
if (not fill_dci_sib(prbs, si_idx, si_ntx, *bwp_grid.cfg, pdcch.dci)) {
// Cancel on-going PDCCH allocation
bwp_pdcch_slot.coresets[coreset_id]->rem_last_dci();
return alloc_result::invalid_coderate;
@ -107,9 +111,10 @@ alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx, uint32_t si_idx, ui
bwp_pdcch_slot.dl.phy.pdsch.pop_back();
return alloc_result::other_cause;
}
pdsch.sch.grant.tb[0].softbuffer.tx = softbuffer.get();
// Store SI msg index
bwp_pdcch_slot.sib_idxs.push_back(si_idx);
bwp_pdcch_slot.dl.sib_idxs.push_back(si_idx);
return alloc_result::success;
}

15
srsgnb/src/stack/mac/sched_nr_signalling.cc
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@ -103,7 +103,11 @@ void sched_dl_signalling(bwp_slot_allocator& bwp_alloc)
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
bool fill_dci_sib(prb_interval interv, uint32_t sib_id, const bwp_params_t& bwp_cfg, srsran_dci_dl_nr_t& dci)
bool fill_dci_sib(prb_interval interv,
uint32_t sib_id,
uint32_t si_ntx,
const bwp_params_t& bwp_cfg,
srsran_dci_dl_nr_t& dci)
{
dci.mcs = 5;
dci.ctx.format = srsran_dci_format_nr_1_0;
@ -117,7 +121,7 @@ bool fill_dci_sib(prb_interval interv, uint32_t sib_id, const bwp_params_t& bwp_
dci.bwp_id = bwp_cfg.bwp_id;
dci.cc_id = bwp_cfg.cc;
dci.rv = 0;
dci.sii = sib_id == 1 ? 0 : 1;
dci.sii = sib_id == 0 ? 0 : 1;
return true;
}
@ -131,6 +135,7 @@ si_sched::si_sched(const bwp_params_t& bwp_cfg_) :
pending_sis[0].len = 77;
pending_sis[0].period = 160;
pending_sis[0].win_len = 160;
pending_sis[0].si_softbuffer = harq_softbuffer_pool::get_instance().get_tx(bwp_cfg->nof_prb());
}
void si_sched::run_slot(bwp_slot_allocator& bwp_alloc)
@ -152,10 +157,10 @@ void si_sched::run_slot(bwp_slot_allocator& bwp_alloc)
if (not si.win_start.valid()) {
bool start_window;
if (si.n == 0) {
// SIB1
// SIB1 (slot index zero of even frames)
start_window = sl_pdcch.slot_idx() == 0 and sl_pdcch.sfn() % 2 == 0;
} else {
// SI messages
// 5.2.2.3.2 - Acquisition of SI message
start_window = (sl_pdcch.sfn() % si.period == x / N) and sl_pdcch.slot_idx() == x % bwp_cfg->slots.size();
}
if (start_window) {
@ -194,7 +199,7 @@ void si_sched::run_slot(bwp_slot_allocator& bwp_alloc)
si.result = alloc_result::no_sch_space;
break;
}
si.result = bwp_alloc.alloc_si(si_aggr_level, si.n, si.n_tx, grant);
si.result = bwp_alloc.alloc_si(si_aggr_level, si.n, si.n_tx, grant, *si.si_softbuffer.get());
if (si.result == alloc_result::success) {
// SIB scheduled successfully
si.win_start.clear();

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