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@ -64,6 +64,8 @@ int sched_nr_ue_sim::update(const sched_nr_cc_result_view& cc_out)
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void sched_nr_ue_sim::update_dl_harqs(const sched_nr_cc_result_view& cc_out)
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{
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uint32_t cc = cc_out.cc;
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// Update DL Harqs
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for (uint32_t i = 0; i < cc_out.dl->phy.pdcch_dl.size(); ++i) {
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const auto& data = cc_out.dl->phy.pdcch_dl[i];
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if (data.dci.ctx.rnti != ctxt.rnti) {
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@ -89,6 +91,61 @@ void sched_nr_ue_sim::update_dl_harqs(const sched_nr_cc_result_view& cc_out)
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.dl_data_to_ul_ack[h.last_slot_tx.slot_idx() % ctxt.ue_cfg.phy_cfg.harq_ack.nof_dl_data_to_ul_ack];
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h.nof_txs++;
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}
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// Update UL harqs
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for (uint32_t i = 0; i < cc_out.dl->phy.pdcch_ul.size(); ++i) {
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const auto& data = cc_out.dl->phy.pdcch_ul[i];
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if (data.dci.ctx.rnti != ctxt.rnti) {
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continue;
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}
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auto& h = ctxt.cc_list[cc].ul_harqs[data.dci.pid];
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if (h.nof_txs == 0 or h.ndi != data.dci.ndi) {
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// It is newtx
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h.nof_retxs = 0;
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h.ndi = data.dci.ndi;
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h.first_slot_tx = cc_out.slot + 4; // TODO
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h.dci_loc = data.dci.ctx.location;
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h.tbs = 100; // TODO
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} else {
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// it is retx
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h.nof_retxs++;
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}
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h.active = true;
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h.last_slot_tx = cc_out.slot + 4; // TODO
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h.last_slot_ack = h.last_slot_tx;
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h.nof_txs++;
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}
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uint32_t rar_count = 0;
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for (uint32_t i = 0; i < cc_out.dl->phy.pdcch_dl.size(); ++i) {
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const auto& rar_pdcch = cc_out.dl->phy.pdcch_dl[i];
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if (rar_pdcch.dci.ctx.rnti_type != srsran_rnti_type_ra) {
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continue;
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}
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const auto& rar_data = cc_out.dl->rar[rar_count++];
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for (uint32_t j = 0; j < rar_data.grants.size(); ++j) {
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auto& msg3_grant = rar_data.grants[j];
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if (msg3_grant.msg3_dci.ctx.rnti != ctxt.rnti) {
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continue;
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}
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auto& h = ctxt.cc_list[cc].ul_harqs[msg3_grant.msg3_dci.pid];
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if (h.nof_txs == 0) {
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// It is newtx
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h.nof_retxs = 0;
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h.ndi = msg3_grant.msg3_dci.ndi;
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h.first_slot_tx = cc_out.slot + 4 + MSG3_DELAY_MS; // TODO
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h.dci_loc = msg3_grant.msg3_dci.ctx.location;
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h.tbs = 100; // TODO
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} else {
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// it is retx
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h.nof_retxs++;
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}
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h.active = true;
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h.last_slot_tx = cc_out.slot + 4 + MSG3_DELAY_MS; // TODO
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h.last_slot_ack = h.last_slot_tx;
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h.nof_txs++;
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}
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}
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}
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sched_nr_base_tester::sched_nr_base_tester(const sched_nr_interface::sched_args_t& sched_args,
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@ -98,11 +155,10 @@ sched_nr_base_tester::sched_nr_base_tester(const sched_nr_interface::sched_args_
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logger(srslog::fetch_basic_logger("TEST")),
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mac_logger(srslog::fetch_basic_logger("MAC-NR")),
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sched_ptr(new sched_nr()),
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test_name(std::move(test_name_))
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test_delimiter(new srsran::test_delimit_logger{test_name_.c_str()})
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{
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sem_init(&slot_sem, 0, 1);
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printf("\n=========== Start %s ===========\n", test_name.c_str());
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cell_params.reserve(cell_cfg_list.size());
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for (uint32_t cc = 0; cc < cell_cfg_list.size(); ++cc) {
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cell_params.emplace_back(cc, cell_cfg_list[cc], sched_args);
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@ -136,7 +192,7 @@ void sched_nr_base_tester::stop()
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worker->stop();
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}
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sem_destroy(&slot_sem);
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printf("============ End %s ===========\n", test_name.c_str());
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test_delimiter.reset();
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}
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}
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@ -163,6 +219,14 @@ int sched_nr_base_tester::add_user(uint16_t rnti,
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return SRSRAN_SUCCESS;
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}
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void sched_nr_base_tester::user_cfg(uint16_t rnti, const sched_nr_interface::ue_cfg_t& ue_cfg_)
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{
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TESTASSERT(ue_db.count(rnti) > 0);
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ue_db.at(rnti).get_ctxt().ue_cfg = ue_cfg_;
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sched_ptr->ue_cfg(rnti, ue_cfg_);
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}
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void sched_nr_base_tester::run_slot(slot_point slot_tx)
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{
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srsran_assert(not stopped.load(std::memory_order_relaxed), "Running scheduler when it has already been stopped");
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@ -236,7 +300,7 @@ void sched_nr_base_tester::process_results()
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sched_nr_cc_result_view cc_out = cc_results[cc].res;
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// Run common tests
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test_dl_pdcch_consistency(cc_out.dl->phy.pdcch_dl);
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test_dl_pdcch_consistency(cell_params[cc].cfg, cc_out.dl->phy.pdcch_dl);
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test_pdsch_consistency(cc_out.dl->phy.pdsch);
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test_ssb_scheduled_grant(cc_out.slot, cell_params[cc_out.cc].cfg, cc_out.dl->phy.ssb);
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@ -265,12 +329,12 @@ int sched_nr_base_tester::set_default_slot_events(const sim_nr_ue_ctxt_t& ue_ctx
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auto& ul_h = ue_ctxt.cc_list[enb_cc_idx].ul_harqs[pid];
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// Set default DL ACK
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if (dl_h.active and (dl_h.last_slot_ack) == current_slot_tx) {
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if (dl_h.active and dl_h.last_slot_ack == current_slot_tx) {
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cc_feedback.dl_acks.push_back(ue_nr_slot_events::ack_t{pid, true});
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}
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// Set default UL ACK
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if (ul_h.active and (ul_h.last_slot_tx + 8) == current_slot_tx) {
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if (ul_h.active and ul_h.last_slot_ack == current_slot_tx) {
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cc_feedback.ul_acks.emplace_back(ue_nr_slot_events::ack_t{pid, true});
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}
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@ -314,11 +378,8 @@ int sched_nr_base_tester::apply_slot_events(sim_nr_ue_ctxt_t& ue_ctxt, const ue_
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"UL ACK rnti=0x%x, slot_ul_tx=%u, cc=%d pid=%d", ue_ctxt.rnti, h.last_slot_tx.to_uint(), enb_cc_idx, h.pid);
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}
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// // update scheduler
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// if (sched_ptr->ul_crc_info(events.slot_rx.to_uint(), ue_ctxt.rnti, enb_cc_idx, cc_feedback.ul_ack) < 0) {
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// logger.error("The ACKed UL Harq pid=%d does not exist.", cc_feedback.ul_pid);
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// error_counter++;
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// }
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// update scheduler
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sched_ptr->ul_crc_info(ue_ctxt.rnti, enb_cc_idx, ack.pid, ack.ack);
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}
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}
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