5g-team
/
srsRAN_4G
mirror of https://github.com/pvnis/srsRAN_4G.git
2
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fixed RBG<->PRB conversion. Changed PHICH logging to be single line

Browse Source
master
Francisco Paisana 4 years ago
parent 68e7df1248
commit 0d9ff3ecc7
6 changed files with 102 additions and 44 deletions
Show Stats Download Patch File Download Diff File

3
srsenb/hdr/stack/mac/sched_common.h
Unescape Escape View File

@ -74,7 +74,6 @@ using prbmask_t = srslte::bounded_bitset<100, true>;
struct prb_interval;
struct rbg_interval : public srslte::interval<uint32_t> {
using interval::interval;
static rbg_interval prbs_to_rbgs(const prb_interval& prbs, uint32_t P);
static rbg_interval rbgmask_to_rbgs(const rbgmask_t& mask);
};
@ -82,7 +81,7 @@ struct rbg_interval : public srslte::interval<uint32_t> {
struct prb_interval : public srslte::interval<uint32_t> {
using interval::interval;
static prb_interval rbgs_to_prbs(const rbg_interval& rbgs, uint32_t P);
static prb_interval rbgs_to_prbs(const rbg_interval& rbgs, uint32_t cell_nof_prb);
static prb_interval riv_to_prbs(uint32_t riv, uint32_t nof_prbs, int nof_vrbs = -1);
};

66
srsenb/hdr/stack/mac/sched_helpers.h
Unescape Escape View File

@ -38,8 +38,74 @@ inline uint32_t get_nof_retx(uint32_t rv_idx)
return nof_retxs[rv_idx % 4];
}
/// convert cell nof PRBs to nof RBGs
inline uint32_t cell_nof_prb_to_rbg(uint32_t nof_prbs)
{
switch (nof_prbs) {
case 6:
return 6;
case 15:
return 8;
case 25:
return 13;
case 50:
return 17;
case 75:
return 19;
case 100:
return 25;
default:
srslte::logmap::get("MAC")->error("Provided nof PRBs not valid");
return 0;
}
}
/// convert cell nof RBGs to nof PRBs
inline uint32_t cell_nof_rbg_to_prb(uint32_t nof_rbgs)
{
switch (nof_rbgs) {
case 6:
return 6;
case 8:
return 15;
case 13:
return 25;
case 17:
return 50;
case 19:
return 75;
case 25:
return 100;
default:
srslte::logmap::get("MAC")->error("Provided nof PRBs not valid");
return 0;
}
}
/**
* Count number of PRBs present in a DL RBG mask
* @param cell_nof_prb cell nof prbs
* @param P cell ratio prb/rbg
* @param bitmask DL RBG mask
* @return number of prbs
*/
inline uint32_t count_prb_per_tb(const rbgmask_t& bitmask)
{
uint32_t Nprb = cell_nof_rbg_to_prb(bitmask.size());
uint32_t P = srslte_ra_type0_P(Nprb);
uint32_t nof_prb = P * bitmask.count();
if (bitmask.test(bitmask.size() - 1)) {
nof_prb -= bitmask.size() * P - Nprb;
}
return nof_prb;
}
/// Logs DL MAC PDU contents
void log_dl_cc_results(srslte::log_ref log_h, uint32_t enb_cc_idx, const sched_interface::dl_sched_res_t& result);
/// Logs PHICH contents
void log_phich_cc_results(srslte::log_ref log_h, uint32_t enb_cc_idx, const sched_interface::ul_sched_res_t& result);
/**
* Generate possible CCE locations a user can use to allocate DCIs
* @param regs Regs data for the given cell configuration

1
srsenb/src/stack/mac/sched_carrier.cc
Unescape Escape View File

@ -362,6 +362,7 @@ const cc_sched_result& sched::carrier_sched::generate_tti_result(tti_point tti_r
}
log_dl_cc_results(log_h, enb_cc_idx, cc_result->dl_sched_result);
log_phich_cc_results(log_h, enb_cc_idx, cc_result->ul_sched_result);
return *cc_result;
}

8
srsenb/src/stack/mac/sched_grid.cc
Unescape Escape View File

@ -903,10 +903,6 @@ bool sf_sched::alloc_phich(sched_ue* user, sched_interface::ul_sched_res_t* ul_s
if (h->has_pending_phich()) {
phich_list.phich = h->pop_pending_phich() ? phich_t::ACK : phich_t::NACK;
phich_list.rnti = user->get_rnti();
log_h->debug("SCHED: Allocated PHICH for rnti=0x%x, value=%s\n",
user->get_rnti(),
phich_list.phich == phich_t::ACK ? "ACK" : "NACK");
ul_sf_result->nof_phich_elems++;
return true;
}
@ -923,7 +919,7 @@ void sf_sched::set_bc_sched_result(const pdcch_grid_t::alloc_result_t& dci_resul
bc->dci.location = dci_result[bc_alloc.dci_idx]->dci_pos;
/* Generate DCI format1A */
prb_interval prb_range = prb_interval::rbgs_to_prbs(bc_alloc.rbg_range, cc_cfg->P);
prb_interval prb_range = prb_interval::rbgs_to_prbs(bc_alloc.rbg_range, cc_cfg->nof_prb());
int tbs = generate_format1a(prb_range, bc_alloc.req_bytes, bc_alloc.rv, bc_alloc.rnti, &bc->dci);
// Setup BC/Paging processes
@ -990,7 +986,7 @@ void sf_sched::set_rar_sched_result(const pdcch_grid_t::alloc_result_t& dci_resu
rar->dci.location = dci_result[rar_alloc.alloc_data.dci_idx]->dci_pos;
/* Generate DCI format1A */
prb_interval prb_range = prb_interval::rbgs_to_prbs(rar_alloc.alloc_data.rbg_range, cc_cfg->P);
prb_interval prb_range = prb_interval::rbgs_to_prbs(rar_alloc.alloc_data.rbg_range, cc_cfg->nof_prb());
int tbs = generate_format1a(prb_range, rar_alloc.alloc_data.req_bytes, 0, rar_alloc.alloc_data.rnti, &rar->dci);
if (tbs <= 0) {
log_h->warning("SCHED: Error RAR, ra_rnti_idx=%d, rbgs=%s, dci=(%d,%d)\n",

36
srsenb/src/stack/mac/sched_helpers.cc
Unescape Escape View File

@ -59,14 +59,14 @@ void fill_dl_cc_result_info(custom_mem_buffer& strbuf, const dl_sched_data_t& da
return;
}
const char* prefix = strbuf.size() > 0 ? " | " : "";
fmt::format_to(strbuf, "{}rnti={:0x}: [", prefix, data.dci.rnti);
fmt::format_to(strbuf, "{}rnti=0x{:0x}: [", prefix, data.dci.rnti);
bool ces_found = false;
for (uint32_t i = 0; i < data.nof_pdu_elems[0]; ++i) {
const auto& pdu = data.pdu[0][i];
prefix = (ces_found) ? " | " : "";
srslte::dl_sch_lcid lcid = static_cast<srslte::dl_sch_lcid>(pdu.lcid);
if (srslte::is_mac_ce(lcid)) {
fmt::format_to(strbuf, "{}MAC CE \"{}\"", prefix, srslte::to_string_short(lcid));
fmt::format_to(strbuf, "{}CE \"{}\"", prefix, srslte::to_string_short(lcid));
ces_found = true;
}
}
@ -79,7 +79,7 @@ void fill_dl_cc_result_debug(custom_mem_buffer& strbuf, const dl_sched_data_t& d
return;
}
fmt::format_to(strbuf,
" > rnti={:0x}, tbs={}, f={}, mcs={}: [",
" > rnti=0x{:0x}, tbs={}, f={}, mcs={}: [",
data.dci.rnti,
data.tbs[0],
to_string_short(data.dci.format),
@ -90,9 +90,9 @@ void fill_dl_cc_result_debug(custom_mem_buffer& strbuf, const dl_sched_data_t& d
const char* prefix = (i == 0) ? "" : " | ";
srslte::dl_sch_lcid lcid = static_cast<srslte::dl_sch_lcid>(pdu.lcid);
if (srslte::is_mac_ce(lcid)) {
fmt::format_to(strbuf, "{}MAC CE \"{}\"", prefix, srslte::to_string_short(lcid));
fmt::format_to(strbuf, "{}CE \"{}\"", prefix, srslte::to_string_short(lcid));
} else {
fmt::format_to(strbuf, "{}MAC SDU lcid={}, tb={}, len={} B", prefix, pdu.lcid, tb, pdu.nbytes);
fmt::format_to(strbuf, "{}SDU lcid={}, tb={}, len={} B", prefix, pdu.lcid, tb, pdu.nbytes);
}
}
}
@ -115,21 +115,35 @@ void log_dl_cc_results(srslte::log_ref log_h, uint32_t enb_cc_idx, const sched_i
}
if (strbuf.size() != 0) {
if (log_h->get_level() == srslte::LOG_LEVEL_DEBUG) {
log_h->debug("SCHED: MAC LCID allocs cc=%d:\n%s", enb_cc_idx, fmt::to_string(strbuf).c_str());
log_h->debug("SCHED: DL MAC PDU payload cc=%d:\n%s", enb_cc_idx, fmt::to_string(strbuf).c_str());
} else {
log_h->info("SCHED: MAC CE allocs cc=%d: %s", enb_cc_idx, fmt::to_string(strbuf).c_str());
log_h->info("SCHED: DL MAC CEs cc=%d: %s", enb_cc_idx, fmt::to_string(strbuf).c_str());
}
}
}
rbg_interval rbg_interval::prbs_to_rbgs(const prb_interval& prbs, uint32_t P)
void log_phich_cc_results(srslte::log_ref log_h, uint32_t enb_cc_idx, const sched_interface::ul_sched_res_t& result)
{
return rbg_interval{srslte::ceil_div(prbs.start(), P), srslte::ceil_div(prbs.stop(), P)};
using phich_t = sched_interface::ul_sched_phich_t;
if (log_h->get_level() < srslte::LOG_LEVEL_INFO) {
return;
}
custom_mem_buffer strbuf;
for (uint32_t i = 0; i < result.nof_phich_elems; ++i) {
const phich_t& phich = result.phich[i];
const char* prefix = strbuf.size() > 0 ? " | " : "";
const char* val = phich.phich == phich_t::ACK ? "ACK" : "NACK";
fmt::format_to(strbuf, "{}rnti=0x{:0x}, val={}", prefix, phich.rnti, val);
}
if (strbuf.size() != 0) {
log_h->debug("SCHED: Allocated PHICHs, cc=%d: [%s]", enb_cc_idx, fmt::to_string(strbuf).c_str());
}
}
prb_interval prb_interval::rbgs_to_prbs(const rbg_interval& rbgs, uint32_t P)
prb_interval prb_interval::rbgs_to_prbs(const rbg_interval& rbgs, uint32_t cell_nof_prb)
{
return prb_interval{rbgs.start() * P, rbgs.stop() * P};
uint32_t P = srslte_ra_type0_P(cell_nof_prb);
return prb_interval{rbgs.start() * P, std::min(rbgs.stop() * P, cell_nof_prb)};
}
rbg_interval rbg_interval::rbgmask_to_rbgs(const rbgmask_t& mask)

26
srsenb/src/stack/mac/sched_ue.cc
Unescape Escape View File

@ -48,22 +48,6 @@ uint32_t get_tbs_bytes(uint32_t mcs, uint32_t nof_alloc_prb, bool use_tbs_index_
return (uint32_t)tbs / 8U;
}
/**
* Count number of PRBs present in a DL RBG mask
* @param bitmask DL RBG mask
* @return number of prbs
*/
uint32_t count_prb_per_tb(const sched_cell_params_t& cell_params, const rbgmask_t& bitmask)
{
uint32_t nof_prb = 0;
for (uint32_t i = 0; i < bitmask.size(); i++) {
if (bitmask.test(i)) {
nof_prb += std::min(cell_params.cfg.cell.nof_prb - (i * cell_params.P), cell_params.P);
}
}
return nof_prb;
}
} // namespace sched_utils
bool operator==(const sched_interface::ue_cfg_t::cc_cfg_t& lhs, const sched_interface::ue_cfg_t::cc_cfg_t& rhs)
@ -505,7 +489,7 @@ std::pair<int, int> sched_ue::allocate_new_dl_mac_pdu(sched::dl_sched_data_t* da
uint32_t tb)
{
srslte_dci_dl_t* dci = &data->dci;
uint32_t nof_prb = sched_utils::count_prb_per_tb(*carriers[ue_cc_idx].get_cell_cfg(), user_mask);
uint32_t nof_prb = count_prb_per_tb(user_mask);
auto ret = compute_mcs_and_tbs(ue_cc_idx, tti_tx_dl, nof_prb, cfi, *dci);
int mcs = ret.first;
int tbs = ret.second;
@ -572,14 +556,12 @@ int sched_ue::generate_format1(uint32_t pid,
dci->alloc_type = SRSLTE_RA_ALLOC_TYPE2;
dci->type2_alloc.mode = srslte_ra_type2_t::SRSLTE_RA_TYPE2_LOC;
rbg_interval rbg_int = rbg_interval::rbgmask_to_rbgs(user_mask);
uint32_t P = srslte_ra_type0_P(15);
prb_interval prb_int = prb_interval::rbgs_to_prbs(rbg_int, P);
uint32_t L_crb =
SRSLTE_MIN(sched_utils::count_prb_per_tb(*carriers[ue_cc_idx].get_cell_cfg(), user_mask), cell.nof_prb);
prb_interval prb_int = prb_interval::rbgs_to_prbs(rbg_int, cell.nof_prb);
uint32_t L_crb = prb_int.length();
uint32_t RB_start = prb_int.start();
dci->type2_alloc.riv = srslte_ra_type2_to_riv(L_crb, RB_start, cell.nof_prb);
dci->format = SRSLTE_DCI_FORMAT1A;
if (prb_int.length() != P * user_mask.count()) {
if (L_crb != cell_nof_rbg_to_prb(user_mask.size())) {
// This happens if Type0 was using distributed allocation
Warning("SCHED: Can't use distributed RA due to DCI size ambiguity\n");
}

Write Preview
Loading…
Cancel
Save