rrc,nr: fix conversion from asn1 to phy cfg

master
Francisco 3 years ago committed by Francisco Paisana
parent 47e5e85449
commit 053877f489

@ -1488,8 +1488,9 @@ bool make_pdsch_cfg_from_serv_cell(asn1::rrc_nr::serving_cell_cfg_s& serv_cell,
auto& uecfg_set = sch_hl->nzp_csi_rs_sets[nzp_set.nzp_csi_res_set_id];
uecfg_set.trs_info = nzp_set.trs_info_present;
uecfg_set.count = nzp_set.nzp_csi_rs_res.size();
uint32_t count = 0;
for (uint8_t nzp_rs_idx : nzp_set.nzp_csi_rs_res) {
auto& res = uecfg_set.data[nzp_rs_idx];
auto& res = uecfg_set.data[count++];
if (not srsran::make_phy_nzp_csi_rs_resource(setup.nzp_csi_rs_res_to_add_mod_list[nzp_rs_idx], &res)) {
return false;
}

@ -67,7 +67,7 @@ void fill_nzp_csi_rs_from_enb_cfg(const rrc_nr_cfg_t& cfg, csi_meas_cfg_s& csi_m
{
csi_meas_cfg.nzp_csi_rs_res_to_add_mod_list_present = true;
if (cfg.cell_list[0].duplex_mode == SRSRAN_DUPLEX_MODE_FDD) {
csi_meas_cfg.nzp_csi_rs_res_to_add_mod_list.resize(5);
csi_meas_cfg.nzp_csi_rs_res_to_add_mod_list.resize(3);
auto& nzp_csi_res = csi_meas_cfg.nzp_csi_rs_res_to_add_mod_list;
// item 0
nzp_csi_res[0].nzp_csi_rs_res_id = 0;
@ -89,81 +89,56 @@ void fill_nzp_csi_rs_from_enb_cfg(const rrc_nr_cfg_t& cfg, csi_meas_cfg_s& csi_m
nzp_csi_res[0].qcl_info_periodic_csi_rs_present = true;
nzp_csi_res[0].qcl_info_periodic_csi_rs = 0;
// item 1
nzp_csi_res[1] = nzp_csi_res[0];
nzp_csi_res[1].nzp_csi_rs_res_id = 1;
nzp_csi_res[1].res_map.freq_domain_alloc.set_row1();
nzp_csi_res[1].res_map.freq_domain_alloc.row1().from_number(0b0001);
nzp_csi_res[1].res_map.nrof_ports = asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
nzp_csi_res[1].res_map.first_ofdm_symbol_in_time_domain = 4;
nzp_csi_res[1].res_map.cdm_type = asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
nzp_csi_res[2].res_map.first_ofdm_symbol_in_time_domain = 4;
nzp_csi_res[1].res_map.density.set_three();
nzp_csi_res[1].res_map.freq_band.start_rb = 0;
nzp_csi_res[1].res_map.freq_band.nrof_rbs = 52;
nzp_csi_res[1].pwr_ctrl_offset = 0;
// Skip pwr_ctrl_offset_ss_present
nzp_csi_res[1].scrambling_id = cfg.cell_list[0].phy_cell.cell_id;
nzp_csi_res[1].periodicity_and_offset_present = true;
nzp_csi_res[1].periodicity_and_offset.set_slots40();
nzp_csi_res[1].periodicity_and_offset.slots40() = 11;
// optional
nzp_csi_res[1].qcl_info_periodic_csi_rs_present = true;
nzp_csi_res[1].qcl_info_periodic_csi_rs = 0;
// item 2
nzp_csi_res[2].nzp_csi_rs_res_id = 2;
nzp_csi_res[2].res_map.freq_domain_alloc.set_row1();
nzp_csi_res[2].res_map.freq_domain_alloc.row1().from_number(0b0001);
nzp_csi_res[2].res_map.nrof_ports = asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
nzp_csi_res[2] = nzp_csi_res[1];
nzp_csi_res[2].nzp_csi_rs_res_id = 2;
nzp_csi_res[2].res_map.first_ofdm_symbol_in_time_domain = 8;
nzp_csi_res[2].res_map.cdm_type = asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
nzp_csi_res[2].res_map.density.set_three();
nzp_csi_res[2].res_map.freq_band.start_rb = 0;
nzp_csi_res[2].res_map.freq_band.nrof_rbs = 52;
nzp_csi_res[2].pwr_ctrl_offset = 0;
// Skip pwr_ctrl_offset_ss_present
nzp_csi_res[2].scrambling_id = cfg.cell_list[0].phy_cell.cell_id;
nzp_csi_res[2].periodicity_and_offset_present = true;
nzp_csi_res[2].periodicity_and_offset.set_slots40();
nzp_csi_res[2].periodicity_and_offset.slots40() = 11;
// optional
nzp_csi_res[2].qcl_info_periodic_csi_rs_present = true;
nzp_csi_res[2].qcl_info_periodic_csi_rs = 0;
// item 3
nzp_csi_res[3].nzp_csi_rs_res_id = 3;
nzp_csi_res[3].res_map.freq_domain_alloc.set_row1();
nzp_csi_res[3].res_map.freq_domain_alloc.row1().from_number(0b0001);
nzp_csi_res[3].res_map.nrof_ports = asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
nzp_csi_res[3].res_map.first_ofdm_symbol_in_time_domain = 4;
nzp_csi_res[3].res_map.cdm_type = asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
nzp_csi_res[3].res_map.density.set_three();
nzp_csi_res[3].res_map.freq_band.start_rb = 0;
nzp_csi_res[3].res_map.freq_band.nrof_rbs = 52;
nzp_csi_res[3].pwr_ctrl_offset = 0;
// Skip pwr_ctrl_offset_ss_present
nzp_csi_res[3].scrambling_id = cfg.cell_list[0].phy_cell.cell_id;
nzp_csi_res[3].periodicity_and_offset_present = true;
nzp_csi_res[3].periodicity_and_offset.set_slots40();
nzp_csi_res[3].periodicity_and_offset.slots40() = 12;
// optional
nzp_csi_res[3].qcl_info_periodic_csi_rs_present = true;
nzp_csi_res[3].qcl_info_periodic_csi_rs = 0;
// item 4
nzp_csi_res[4].nzp_csi_rs_res_id = 4;
nzp_csi_res[4].res_map.freq_domain_alloc.set_row1();
nzp_csi_res[4].res_map.freq_domain_alloc.row1().from_number(0b0001);
nzp_csi_res[4].res_map.nrof_ports = asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
nzp_csi_res[4].res_map.first_ofdm_symbol_in_time_domain = 8;
nzp_csi_res[4].res_map.cdm_type = asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm;
nzp_csi_res[4].res_map.density.set_three();
nzp_csi_res[4].res_map.freq_band.start_rb = 0;
nzp_csi_res[4].res_map.freq_band.nrof_rbs = 52;
nzp_csi_res[4].pwr_ctrl_offset = 0;
// Skip pwr_ctrl_offset_ss_present
nzp_csi_res[4].scrambling_id = cfg.cell_list[0].phy_cell.cell_id;
nzp_csi_res[4].periodicity_and_offset_present = true;
nzp_csi_res[4].periodicity_and_offset.set_slots40();
nzp_csi_res[4].periodicity_and_offset.slots40() = 12;
// optional
nzp_csi_res[4].qcl_info_periodic_csi_rs_present = true;
nzp_csi_res[4].qcl_info_periodic_csi_rs = 0;
// nzp_csi_res[3].nzp_csi_rs_res_id = 3;
// nzp_csi_res[3].res_map.freq_domain_alloc.set_row1();
// nzp_csi_res[3].res_map.freq_domain_alloc.row1().from_number(0b0001);
// nzp_csi_res[3].res_map.nrof_ports = asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
// nzp_csi_res[3].res_map.first_ofdm_symbol_in_time_domain = 4;
// nzp_csi_res[3].res_map.cdm_type =
// asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm; nzp_csi_res[3].res_map.density.set_three();
// nzp_csi_res[3].res_map.freq_band.start_rb = 0;
// nzp_csi_res[3].res_map.freq_band.nrof_rbs = 52;
// nzp_csi_res[3].pwr_ctrl_offset = 0;
// // Skip pwr_ctrl_offset_ss_present
// nzp_csi_res[3].scrambling_id = cfg.cell_list[0].phy_cell.cell_id;
// nzp_csi_res[3].periodicity_and_offset_present = true;
// nzp_csi_res[3].periodicity_and_offset.set_slots40();
// nzp_csi_res[3].periodicity_and_offset.slots40() = 12;
// // optional
// nzp_csi_res[3].qcl_info_periodic_csi_rs_present = true;
// nzp_csi_res[3].qcl_info_periodic_csi_rs = 0;
// // item 4
// nzp_csi_res[4].nzp_csi_rs_res_id = 4;
// nzp_csi_res[4].res_map.freq_domain_alloc.set_row1();
// nzp_csi_res[4].res_map.freq_domain_alloc.row1().from_number(0b0001);
// nzp_csi_res[4].res_map.nrof_ports = asn1::rrc_nr::csi_rs_res_map_s::nrof_ports_opts::p1;
// nzp_csi_res[4].res_map.first_ofdm_symbol_in_time_domain = 8;
// nzp_csi_res[4].res_map.cdm_type =
// asn1::rrc_nr::csi_rs_res_map_s::cdm_type_opts::no_cdm; nzp_csi_res[4].res_map.density.set_three();
// nzp_csi_res[4].res_map.freq_band.start_rb = 0;
// nzp_csi_res[4].res_map.freq_band.nrof_rbs = 52;
// nzp_csi_res[4].pwr_ctrl_offset = 0;
// // Skip pwr_ctrl_offset_ss_present
// nzp_csi_res[4].scrambling_id = cfg.cell_list[0].phy_cell.cell_id;
// nzp_csi_res[4].periodicity_and_offset_present = true;
// nzp_csi_res[4].periodicity_and_offset.set_slots40();
// nzp_csi_res[4].periodicity_and_offset.slots40() = 12;
// // optional
// nzp_csi_res[4].qcl_info_periodic_csi_rs_present = true;
// nzp_csi_res[4].qcl_info_periodic_csi_rs = 0;
} else {
csi_meas_cfg.nzp_csi_rs_res_to_add_mod_list.resize(1);
auto& nzp_csi_res = csi_meas_cfg.nzp_csi_rs_res_to_add_mod_list;
@ -188,7 +163,7 @@ void fill_nzp_csi_rs_from_enb_cfg(const rrc_nr_cfg_t& cfg, csi_meas_cfg_s& csi_m
// Fill NZP-CSI Resource Sets
csi_meas_cfg.nzp_csi_rs_res_set_to_add_mod_list_present = true;
if (cfg.cell_list[0].duplex_mode == SRSRAN_DUPLEX_MODE_FDD) {
csi_meas_cfg.nzp_csi_rs_res_set_to_add_mod_list.resize(2);
csi_meas_cfg.nzp_csi_rs_res_set_to_add_mod_list.resize(3);
auto& nzp_csi_res_set = csi_meas_cfg.nzp_csi_rs_res_set_to_add_mod_list;
// item 0
nzp_csi_res_set[0].nzp_csi_res_set_id = 0;
@ -196,12 +171,12 @@ void fill_nzp_csi_rs_from_enb_cfg(const rrc_nr_cfg_t& cfg, csi_meas_cfg_s& csi_m
nzp_csi_res_set[0].nzp_csi_rs_res[0] = 0;
// item 1
nzp_csi_res_set[1].nzp_csi_res_set_id = 1;
nzp_csi_res_set[1].nzp_csi_rs_res.resize(4);
nzp_csi_res_set[1].nzp_csi_rs_res.resize(1);
nzp_csi_res_set[1].nzp_csi_rs_res[0] = 1;
nzp_csi_res_set[1].nzp_csi_rs_res[1] = 2;
nzp_csi_res_set[1].nzp_csi_rs_res[2] = 3;
nzp_csi_res_set[1].nzp_csi_rs_res[3] = 4;
// Skip TRS info
// nzp_csi_res_set[1].nzp_csi_rs_res[2] = 3;
// nzp_csi_res_set[1].nzp_csi_rs_res[3] = 4;
// // Skip TRS info
} else {
csi_meas_cfg.nzp_csi_rs_res_set_to_add_mod_list.resize(1);
auto& nzp_csi_res_set = csi_meas_cfg.nzp_csi_rs_res_set_to_add_mod_list;
@ -254,10 +229,7 @@ int fill_csi_meas_from_enb_cfg(const rrc_nr_cfg_t& cfg, csi_meas_cfg_s& csi_meas
fill_csi_resource_cfg_to_add(cfg, csi_meas_cfg);
// Fill NZP-CSI Resources
if (cfg.cell_list[0].duplex_mode != SRSRAN_DUPLEX_MODE_FDD) {
// TODO: Support nzp-csi for FDD
fill_nzp_csi_rs_from_enb_cfg(cfg, csi_meas_cfg);
}
fill_nzp_csi_rs_from_enb_cfg(cfg, csi_meas_cfg);
// CSI IM config
// TODO: add csi im config

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