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360 lines
11 KiB
C++
360 lines
11 KiB
C++
/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2021 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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#include "sched_nr_sim_ue.h"
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#include "sched_nr_common_test.h"
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#include "sched_nr_ue_ded_test_suite.h"
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#include "srsran/common/test_common.h"
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namespace srsenb {
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sched_nr_ue_sim::sched_nr_ue_sim(uint16_t rnti_,
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const sched_nr_interface::ue_cfg_t& ue_cfg_,
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slot_point prach_slot_rx,
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uint32_t preamble_idx) :
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logger(srslog::fetch_basic_logger("MAC"))
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{
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ctxt.rnti = rnti_;
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ctxt.prach_slot_rx = prach_slot_rx;
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ctxt.preamble_idx = preamble_idx;
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ctxt.ue_cfg = ue_cfg_;
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ctxt.cc_list.resize(ue_cfg_.carriers.size());
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for (auto& cc : ctxt.cc_list) {
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for (size_t pid = 0; pid < SCHED_NR_MAX_HARQ; ++pid) {
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cc.ul_harqs[pid].pid = pid;
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cc.dl_harqs[pid].pid = pid;
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}
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}
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}
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int sched_nr_ue_sim::update(const sched_nr_cc_result_view& cc_out)
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{
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update_dl_harqs(cc_out);
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for (uint32_t i = 0; i < cc_out.dl_cc_result->dl_sched.pdcch_dl.size(); ++i) {
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const auto& data = cc_out.dl_cc_result->dl_sched.pdcch_dl[i];
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if (data.dci.ctx.rnti != ctxt.rnti) {
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continue;
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}
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slot_point pdcch_slot = cc_out.slot;
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uint32_t k1 = ctxt.ue_cfg.phy_cfg.harq_ack
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.dl_data_to_ul_ack[pdcch_slot.slot_idx() % ctxt.ue_cfg.phy_cfg.harq_ack.nof_dl_data_to_ul_ack];
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slot_point uci_slot = pdcch_slot + k1;
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ctxt.cc_list[cc_out.cc].pending_acks[uci_slot.to_uint()]++;
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}
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// clear up old slots
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ctxt.cc_list[cc_out.cc].pending_acks[(cc_out.slot - 1).to_uint()] = 0;
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return SRSRAN_SUCCESS;
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}
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void sched_nr_ue_sim::update_dl_harqs(const sched_nr_cc_result_view& cc_out)
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{
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uint32_t cc = cc_out.cc;
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for (uint32_t i = 0; i < cc_out.dl_cc_result->dl_sched.pdcch_dl.size(); ++i) {
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const auto& data = cc_out.dl_cc_result->dl_sched.pdcch_dl[i];
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if (data.dci.ctx.rnti != ctxt.rnti) {
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continue;
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}
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auto& h = ctxt.cc_list[cc].dl_harqs[data.dci.pid];
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if (h.nof_txs == 0 or h.ndi != data.dci.ndi) {
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// It is newtx
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h.nof_retxs = 0;
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h.ndi = data.dci.ndi;
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h.first_slot_tx = cc_out.slot;
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h.dci_loc = data.dci.ctx.location;
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h.tbs = 100; // TODO
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} else {
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// it is retx
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h.nof_retxs++;
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}
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h.active = true;
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h.last_slot_tx = cc_out.slot;
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h.last_slot_ack =
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h.last_slot_tx +
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ctxt.ue_cfg.phy_cfg.harq_ack
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.dl_data_to_ul_ack[h.last_slot_tx.slot_idx() % ctxt.ue_cfg.phy_cfg.harq_ack.nof_dl_data_to_ul_ack];
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h.nof_txs++;
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}
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}
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namespace detail {
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sched_nr_sim_base::sched_nr_sim_base(const sched_nr_interface::sched_args_t& sched_args,
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const std::vector<sched_nr_interface::cell_cfg_t>& cell_cfg_list,
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std::string test_name_) :
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logger(srslog::fetch_basic_logger("TEST")),
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mac_logger(srslog::fetch_basic_logger("MAC")),
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sched_ptr(new sched_nr()),
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test_name(std::move(test_name_))
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{
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logger.info("\n=========== Start %s ===========", test_name.c_str());
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cell_params.reserve(cell_cfg_list.size());
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for (uint32_t cc = 0; cc < cell_cfg_list.size(); ++cc) {
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cell_params.emplace_back(cc, cell_cfg_list[cc], sched_args);
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}
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sched_ptr->config(sched_args, cell_cfg_list); // call parent cfg
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cc_results.resize(cell_params.size());
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TESTASSERT(cell_params.size() > 0);
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}
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sched_nr_sim_base::~sched_nr_sim_base()
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{
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logger.info("=========== End %s ==========\n", test_name.c_str());
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}
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int sched_nr_sim_base::add_user(uint16_t rnti,
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const sched_nr_interface::ue_cfg_t& ue_cfg_,
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slot_point tti_rx,
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uint32_t preamble_idx)
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{
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sched_ptr->ue_cfg(rnti, ue_cfg_);
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std::lock_guard<std::mutex> lock(std::mutex);
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TESTASSERT(ue_db.count(rnti) == 0);
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ue_db.insert(std::make_pair(rnti, sched_nr_ue_sim(rnti, ue_cfg_, current_slot_tx, preamble_idx)));
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sched_nr_interface::rar_info_t rach_info{};
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rach_info.temp_crnti = rnti;
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rach_info.prach_slot = tti_rx;
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rach_info.preamble_idx = preamble_idx;
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rach_info.msg3_size = 7;
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sched_ptr->dl_rach_info(ue_cfg_.carriers[0].cc, rach_info);
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return SRSRAN_SUCCESS;
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}
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void sched_nr_sim_base::new_slot_(slot_point slot_tx)
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{
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logger.set_context(slot_tx.to_uint());
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mac_logger.set_context(slot_tx.to_uint());
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// Clear previous slot results
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for (uint32_t cc = 0; cc < cc_results.size(); ++cc) {
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cc_results[cc] = {};
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}
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logger.info("---------------- TTI=%d ---------------", slot_tx.to_uint());
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// Process pending feedback
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for (auto& ue : ue_db) {
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ue_nr_slot_events events;
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set_default_slot_events(ue.second.get_ctxt(), events);
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set_external_slot_events(ue.second.get_ctxt(), events);
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apply_slot_events(ue.second.get_ctxt(), events);
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}
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}
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void sched_nr_sim_base::generate_cc_result_(uint32_t cc)
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{
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// Run scheduler
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auto tp1 = std::chrono::steady_clock::now();
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sched_ptr->run_slot(current_slot_tx, cc, cc_results[cc].dl_res);
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sched_ptr->get_ul_sched(current_slot_tx, cc, cc_results[cc].ul_res);
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auto tp2 = std::chrono::steady_clock::now();
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cc_results[cc].sched_latency_ns = std::chrono::duration_cast<std::chrono::nanoseconds>(tp2 - tp1);
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}
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void sched_nr_sim_base::process_results()
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{
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sched_nr_cc_result_view cc_out;
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cc_out.slot = current_slot_tx;
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for (uint32_t cc = 0; cc < cell_params.size(); ++cc) {
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cc_out.cc = cc;
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cc_out.dl_cc_result = &cc_results[cc].dl_res;
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cc_out.ul_cc_result = &cc_results[cc].ul_res;
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// Run common tests
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test_dl_pdcch_consistency(cc_out.dl_cc_result->dl_sched.pdcch_dl);
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test_pdsch_consistency(cc_out.dl_cc_result->dl_sched.pdsch);
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test_ssb_scheduled_grant(cc_out.slot, cell_params[cc_out.cc].cfg, cc_out.dl_cc_result->dl_sched.ssb);
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// Run UE-dedicated tests
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sim_nr_enb_ctxt_t ctxt;
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ctxt = get_enb_ctxt();
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test_dl_sched_result(ctxt, cc_out);
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// Derived class-defined tests
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process_cc_result(cc_results[cc]);
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// Update UE state
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for (auto& u : ue_db) {
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u.second.update(cc_out);
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}
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}
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}
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int sched_nr_sim_base::set_default_slot_events(const sim_nr_ue_ctxt_t& ue_ctxt, ue_nr_slot_events& pending_events)
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{
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pending_events.cc_list.clear();
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pending_events.cc_list.resize(cell_params.size());
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pending_events.slot_rx = current_slot_tx;
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for (uint32_t enb_cc_idx = 0; enb_cc_idx < pending_events.cc_list.size(); ++enb_cc_idx) {
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auto& cc_feedback = pending_events.cc_list[enb_cc_idx];
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cc_feedback.configured = true;
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for (uint32_t pid = 0; pid < SCHED_NR_MAX_HARQ; ++pid) {
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auto& dl_h = ue_ctxt.cc_list[enb_cc_idx].dl_harqs[pid];
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auto& ul_h = ue_ctxt.cc_list[enb_cc_idx].ul_harqs[pid];
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// Set default DL ACK
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if (dl_h.active and (dl_h.last_slot_ack) == current_slot_tx) {
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cc_feedback.dl_acks.push_back(ue_nr_slot_events::ack_t{pid, true});
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}
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// Set default UL ACK
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if (ul_h.active and (ul_h.last_slot_tx + 8) == current_slot_tx) {
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cc_feedback.ul_acks.emplace_back(ue_nr_slot_events::ack_t{pid, true});
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}
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// TODO: other CSI
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}
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}
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return SRSRAN_SUCCESS;
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}
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int sched_nr_sim_base::apply_slot_events(sim_nr_ue_ctxt_t& ue_ctxt, const ue_nr_slot_events& events)
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{
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for (uint32_t enb_cc_idx = 0; enb_cc_idx < events.cc_list.size(); ++enb_cc_idx) {
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const auto& cc_feedback = events.cc_list[enb_cc_idx];
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if (not cc_feedback.configured) {
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continue;
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}
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for (auto& ack : cc_feedback.dl_acks) {
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auto& h = ue_ctxt.cc_list[enb_cc_idx].dl_harqs[ack.pid];
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if (ack.ack) {
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logger.info(
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"DL ACK rnti=0x%x slot_dl_tx=%u cc=%d pid=%d", ue_ctxt.rnti, h.last_slot_tx.to_uint(), enb_cc_idx, ack.pid);
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}
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// update scheduler
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sched_ptr->dl_ack_info(ue_ctxt.rnti, enb_cc_idx, h.pid, 0, ack.ack);
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// update UE sim context
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if (ack.ack or ue_ctxt.is_last_dl_retx(enb_cc_idx, h.pid)) {
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h.active = false;
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}
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}
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for (auto& ack : cc_feedback.ul_acks) {
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auto& h = ue_ctxt.cc_list[enb_cc_idx].ul_harqs[ack.pid];
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if (ack.ack) {
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logger.info(
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"UL ACK rnti=0x%x, slot_ul_tx=%u, cc=%d pid=%d", ue_ctxt.rnti, h.last_slot_tx.to_uint(), enb_cc_idx, h.pid);
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}
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// // update scheduler
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// if (sched_ptr->ul_crc_info(events.slot_rx.to_uint(), ue_ctxt.rnti, enb_cc_idx, cc_feedback.ul_ack) < 0) {
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// logger.error("The ACKed UL Harq pid=%d does not exist.", cc_feedback.ul_pid);
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// error_counter++;
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// }
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}
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}
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return SRSRAN_SUCCESS;
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}
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sim_nr_enb_ctxt_t sched_nr_sim_base::get_enb_ctxt() const
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{
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sim_nr_enb_ctxt_t ctxt;
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ctxt.cell_params = cell_params;
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for (auto& ue_pair : ue_db) {
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ctxt.ue_db.insert(std::make_pair(ue_pair.first, &ue_pair.second.get_ctxt()));
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}
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return ctxt;
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}
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} // namespace detail
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void sched_nr_sim::new_slot(slot_point slot_tx)
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{
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current_slot_tx = slot_tx;
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nof_cc_remaining = cell_params.size();
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this->new_slot_(slot_tx);
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}
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void sched_nr_sim::generate_cc_result(uint32_t cc)
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{
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// Run scheduler
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this->generate_cc_result_(cc);
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if (--nof_cc_remaining > 0) {
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// there are still missing CC results
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return;
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}
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// Run tests and update UE state
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this->process_results();
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}
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void sched_nr_sim_parallel::new_slot(slot_point slot_tx)
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{
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// Block concurrent or out-of-order calls to the scheduler
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{
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std::unique_lock<std::mutex> lock(mutex);
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while (nof_cc_remaining > 0 or (current_slot_tx.valid() and current_slot_tx + 1 != slot_tx)) {
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cvar.wait(lock);
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}
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current_slot_tx = slot_tx;
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nof_cc_remaining = cell_params.size();
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}
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// Run common new_slot updates
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this->new_slot_(slot_tx);
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}
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void sched_nr_sim_parallel::generate_cc_result(uint32_t cc)
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{
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// Run scheduler
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this->generate_cc_result_(cc);
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{
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std::unique_lock<std::mutex> lock(mutex);
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if (--nof_cc_remaining > 0) {
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// there are still missing CC results
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return;
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}
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// Run tests and update UE state
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this->process_results();
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}
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// Notify waiting workers
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cvar.notify_one();
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}
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sched_nr_sim_parallel::~sched_nr_sim_parallel()
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{
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stop();
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}
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void sched_nr_sim_parallel::stop()
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{
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std::unique_lock<std::mutex> lock(mutex);
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while (nof_cc_remaining > 0) {
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cvar.wait(lock);
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}
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}
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} // namespace srsenb
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