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282 lines
10 KiB
C++
282 lines
10 KiB
C++
/**
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*
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* \section COPYRIGHT
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*
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* Copyright 2013-2020 Software Radio Systems Limited
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*
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* By using this file, you agree to the terms and conditions set
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* forth in the LICENSE file which can be found at the top level of
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* the distribution.
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*
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*/
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#include "sched_test_common.h"
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#include "sched_test_utils.h"
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#include "srsenb/hdr/stack/mac/sched.h"
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#include "srslte/mac/pdu.h"
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using namespace srsenb;
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uint32_t const seed = std::chrono::system_clock::now().time_since_epoch().count();
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/*******************
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* Logging *
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*******************/
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/// RAII style class that prints the test diagnostic info on destruction.
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class sched_diagnostic_printer
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{
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public:
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explicit sched_diagnostic_printer(srslte::log_sink_spy& s) : s(s) {}
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~sched_diagnostic_printer()
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{
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auto& logger = srslog::fetch_basic_logger("TEST");
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logger.info("[TESTER] Number of assertion warnings: %u", s.get_warning_counter());
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logger.info("[TESTER] Number of assertion errors: %u", s.get_error_counter());
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logger.info("[TESTER] This was the seed: %u", seed);
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srslog::flush();
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}
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private:
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srslte::log_sink_spy& s;
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};
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/******************************
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* Scheduler Tests
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*****************************/
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sim_sched_args generate_default_sim_args(uint32_t nof_prb, uint32_t nof_ccs)
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{
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sim_sched_args sim_args;
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sim_args.default_ue_sim_cfg.ue_cfg = generate_default_ue_cfg2();
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// setup two cells
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std::vector<srsenb::sched_interface::cell_cfg_t> cell_cfg(nof_ccs, generate_default_cell_cfg(nof_prb));
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cell_cfg[0].scell_list.resize(1);
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cell_cfg[0].scell_list[0].enb_cc_idx = 1;
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cell_cfg[0].scell_list[0].cross_carrier_scheduling = false;
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cell_cfg[0].scell_list[0].ul_allowed = true;
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cell_cfg[1].cell.id = 2; // id=2
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cell_cfg[1].scell_list = cell_cfg[0].scell_list;
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cell_cfg[1].scell_list[0].enb_cc_idx = 0;
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sim_args.cell_cfg = std::move(cell_cfg);
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/* Setup Derived Params */
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sim_args.default_ue_sim_cfg.ue_cfg.supported_cc_list.resize(nof_ccs);
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for (uint32_t i = 0; i < sim_args.default_ue_sim_cfg.ue_cfg.supported_cc_list.size(); ++i) {
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sim_args.default_ue_sim_cfg.ue_cfg.supported_cc_list[i].active = true;
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sim_args.default_ue_sim_cfg.ue_cfg.supported_cc_list[i].enb_cc_idx = i;
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}
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return sim_args;
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}
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struct test_scell_activation_params {
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uint32_t pcell_idx = 0;
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};
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int test_scell_activation(test_scell_activation_params params)
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{
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std::array<uint32_t, 6> prb_list{6, 15, 25, 50, 75, 100};
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/* Simulation Configuration Arguments */
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uint32_t nof_prb = prb_list[std::uniform_int_distribution<uint32_t>{0, 5}(get_rand_gen())];
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uint32_t nof_ccs = 2;
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uint32_t start_tti = 0; // rand_int(0, 10240);
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/* Internal configurations. Do not touch */
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float ul_sr_exps[] = {1, 4}; // log rand
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float dl_data_exps[] = {1, 4}; // log rand
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float P_ul_sr = randf() * 0.5, P_dl = randf() * 0.5;
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const uint16_t rnti1 = 70;
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/* Setup Simulation */
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uint32_t prach_tti = 1;
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uint32_t msg4_size = 40; // TODO: Check
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uint32_t duration = 1000;
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// Generate Cell order
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std::vector<uint32_t> cc_idxs(nof_ccs);
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std::iota(cc_idxs.begin(), cc_idxs.end(), 0);
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std::shuffle(cc_idxs.begin(), cc_idxs.end(), get_rand_gen());
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std::iter_swap(cc_idxs.begin(), std::find(cc_idxs.begin(), cc_idxs.end(), params.pcell_idx));
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/* Setup simulation arguments struct */
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sim_sched_args sim_args = generate_default_sim_args(nof_prb, nof_ccs);
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sim_args.start_tti = start_tti;
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sim_args.default_ue_sim_cfg.ue_cfg.supported_cc_list.resize(1);
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sim_args.default_ue_sim_cfg.ue_cfg.supported_cc_list[0].active = true;
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sim_args.default_ue_sim_cfg.ue_cfg.supported_cc_list[0].enb_cc_idx = cc_idxs[0];
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sim_args.default_ue_sim_cfg.ue_cfg.supported_cc_list[0].dl_cfg.cqi_report.periodic_configured = true;
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sim_args.default_ue_sim_cfg.ue_cfg.supported_cc_list[0].dl_cfg.cqi_report.pmi_idx = 37;
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/* Simulation Objects Setup */
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sched_sim_event_generator generator;
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// Setup scheduler
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common_sched_tester tester;
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tester.init(nullptr);
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tester.sim_cfg(sim_args);
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/* Simulation */
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// Event PRACH: PRACH takes place for "rnti1", and carrier "pcell_idx"
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generator.step_until(prach_tti);
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tti_ev::user_cfg_ev* user = generator.add_new_default_user(duration, sim_args.default_ue_sim_cfg);
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user->rnti = rnti1;
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tester.test_next_ttis(generator.tti_events);
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TESTASSERT(tester.sched_sim->user_exists(rnti1));
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// Event (TTI=prach_tti+msg4_tot_delay): First Tx (Msg4). Goes in SRB0 and contains ConRes
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while (not tester.sched_sim->find_rnti(rnti1)->get_ctxt().msg3_tti_rx.is_valid() or
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srsenb::to_tx_ul(tester.sched_sim->find_rnti(rnti1)->get_ctxt().msg3_tti_rx).to_uint() >
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generator.tti_counter) {
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generator.step_tti();
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tester.test_next_ttis(generator.tti_events);
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}
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generator.step_tti();
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generator.add_dl_data(rnti1, msg4_size);
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tester.test_next_ttis(generator.tti_events);
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while (not tester.sched_sim->find_rnti(rnti1)->get_ctxt().conres_rx) {
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generator.step_tti();
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tester.test_next_ttis(generator.tti_events);
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}
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// Event (20 TTIs): Data back and forth
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auto generate_data = [&](uint32_t nof_ttis, float prob_dl, float prob_ul, float rand_exp) {
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for (uint32_t i = 0; i < nof_ttis; ++i) {
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generator.step_tti();
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bool ul_flag = randf() < prob_ul, dl_flag = randf() < prob_dl;
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if (dl_flag) {
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float exp = dl_data_exps[0] + rand_exp * (dl_data_exps[1] - dl_data_exps[0]);
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generator.add_dl_data(rnti1, pow(10, exp));
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}
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if (ul_flag) {
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float exp = ul_sr_exps[0] + rand_exp * (ul_sr_exps[1] - ul_sr_exps[0]);
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generator.add_ul_data(rnti1, pow(10, exp));
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}
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}
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};
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generate_data(20, 1.0, P_ul_sr, randf());
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tester.test_next_ttis(generator.tti_events);
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// Event: Reconf Complete. Activate SCells. Check if CE correctly transmitted
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generator.step_tti();
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user = generator.user_reconf(rnti1);
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user->ue_sim_cfg->ue_cfg =
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*tester.get_current_ue_cfg(rnti1); // use current cfg as starting point, and add more supported ccs
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user->ue_sim_cfg->ue_cfg.supported_cc_list.resize(nof_ccs);
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for (uint32_t i = 0; i < user->ue_sim_cfg->ue_cfg.supported_cc_list.size(); ++i) {
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user->ue_sim_cfg->ue_cfg.supported_cc_list[i].active = true;
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user->ue_sim_cfg->ue_cfg.supported_cc_list[i].enb_cc_idx = cc_idxs[i];
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}
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tester.test_next_ttis(generator.tti_events);
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auto activ_list = tester.get_enb_ue_cc_map(rnti1);
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for (uint32_t i = 0; i < cc_idxs.size(); ++i) {
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TESTASSERT(activ_list[i] >= 0);
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}
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// TEST: When a DL newtx takes place, it should also encode the CE
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for (uint32_t i = 0; i < 100; ++i) {
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if (tester.tti_info.dl_sched_result[params.pcell_idx].nof_data_elems > 0) {
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// DL data was allocated
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if (tester.tti_info.dl_sched_result[params.pcell_idx].data[0].nof_pdu_elems[0] > 0) {
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// it is a new DL tx
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TESTASSERT(tester.tti_info.dl_sched_result[params.pcell_idx].data[0].pdu[0][0].lcid ==
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(uint32_t)srslte::dl_sch_lcid::SCELL_ACTIVATION);
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break;
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}
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}
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generator.step_tti();
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tester.test_next_ttis(generator.tti_events);
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}
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// Event: Wait for UE to receive and ack CE. Send cqi==0, which should not activate the SCell
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uint32_t cqi = 0;
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for (uint32_t cidx = 1; cidx < cc_idxs.size(); ++cidx) {
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for (uint32_t i = 0; i < FDD_HARQ_DELAY_UL_MS; ++i) {
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tester.dl_cqi_info(tester.tti_rx.to_uint(), rnti1, cc_idxs[cidx], cqi);
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generator.step_tti();
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}
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}
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tester.test_next_ttis(generator.tti_events);
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// The UE should now have received the CE
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// Event: Generate a bit more data, it should *not* go through SCells until we send a CQI
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generate_data(5, P_dl, P_ul_sr, randf());
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tester.test_next_ttis(generator.tti_events);
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TESTASSERT(tester.sched_stats->users[rnti1].tot_dl_sched_data[params.pcell_idx] > 0);
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TESTASSERT(tester.sched_stats->users[rnti1].tot_ul_sched_data[params.pcell_idx] > 0);
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for (uint32_t i = 1; i < cc_idxs.size(); ++i) {
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TESTASSERT(tester.sched_stats->users[rnti1].tot_dl_sched_data[cc_idxs[i]] == 0);
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TESTASSERT(tester.sched_stats->users[rnti1].tot_ul_sched_data[cc_idxs[i]] == 0);
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}
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// Event: Scheduler receives dl_cqi for SCell. Data should go through SCells
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cqi = 14;
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for (uint32_t i = 1; i < cc_idxs.size(); ++i) {
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tester.dl_cqi_info(tester.tti_rx.to_uint(), rnti1, cc_idxs[i], cqi);
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}
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generate_data(10, 1.0, 1.0, 1.0);
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tester.test_next_ttis(generator.tti_events);
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uint64_t tot_dl_sched_data = 0;
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uint64_t tot_ul_sched_data = 0;
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for (const auto& c : cc_idxs) {
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tot_dl_sched_data += tester.sched_stats->users[rnti1].tot_dl_sched_data[c];
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tot_ul_sched_data += tester.sched_stats->users[rnti1].tot_ul_sched_data[c];
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}
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TESTASSERT(tot_dl_sched_data > 0);
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TESTASSERT(tot_ul_sched_data > 0);
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srslog::fetch_basic_logger("TEST").info("[TESTER] Sim1 finished successfully");
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return SRSLTE_SUCCESS;
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}
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int main()
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{
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// Setup rand seed
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set_randseed(seed);
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// Setup the log spy to intercept error and warning log entries.
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if (!srslog::install_custom_sink(
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srslte::log_sink_spy::name(),
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std::unique_ptr<srslte::log_sink_spy>(new srslte::log_sink_spy(srslog::get_default_log_formatter())))) {
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return SRSLTE_ERROR;
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}
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auto* spy = static_cast<srslte::log_sink_spy*>(srslog::find_sink(srslte::log_sink_spy::name()));
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if (!spy) {
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return SRSLTE_ERROR;
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}
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auto& mac_log = srslog::fetch_basic_logger("MAC");
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mac_log.set_level(srslog::basic_levels::info);
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auto& test_log = srslog::fetch_basic_logger("TEST", *spy, false);
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test_log.set_level(srslog::basic_levels::info);
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// Start the log backend.
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srslog::init();
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sched_diagnostic_printer printer(*spy);
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srslte::logmap::set_default_log_level(srslte::LOG_LEVEL_INFO);
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printf("[TESTER] This is the chosen seed: %u\n", seed);
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uint32_t N_runs = 20;
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for (uint32_t n = 0; n < N_runs; ++n) {
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printf("Sim run number: %u\n", n + 1);
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test_scell_activation_params p = {};
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p.pcell_idx = 0;
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TESTASSERT(test_scell_activation(p) == SRSLTE_SUCCESS);
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p = {};
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p.pcell_idx = 1;
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TESTASSERT(test_scell_activation(p) == SRSLTE_SUCCESS);
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}
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srslog::flush();
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return 0;
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}
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