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285 lines
9.1 KiB
C++
285 lines
9.1 KiB
C++
/*
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* Copyright 2013-2019 Software Radio Systems Limited
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*
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* This file is part of srsLTE.
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*
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* srsLTE is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Affero General Public License as
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* published by the Free Software Foundation, either version 3 of
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* the License, or (at your option) any later version.
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*
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* srsLTE is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Affero General Public License for more details.
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*
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* A copy of the GNU Affero General Public License can be found in
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* the LICENSE file in the top-level directory of this distribution
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* and at http://www.gnu.org/licenses/.
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*
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*/
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#include "srslte/common/common.h"
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#include "srslte/srslte.h"
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#include <vector>
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#ifndef SRSLTE_SCHED_INTERFACE_H
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#define SRSLTE_SCHED_INTERFACE_H
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namespace srsenb {
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class sched_interface
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{
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public:
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virtual ~sched_interface() = default;
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const static uint32_t max_cce = 128;
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const static uint32_t max_prb = 100;
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const static uint32_t max_rbg = 25;
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const static int MAX_SIB_PAYLOAD_LEN = 2048;
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const static int MAX_SIBS = 16;
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const static int MAX_LC = 6;
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const static int MAX_DATA_LIST = 32;
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const static int MAX_RAR_LIST = 8;
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const static int MAX_BC_LIST = 8;
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const static int MAX_RLC_PDU_LIST = 8;
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const static int MAX_PHICH_LIST = 8;
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typedef struct {
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uint32_t len;
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uint32_t period_rf;
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} cell_cfg_sib_t;
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struct sched_args_t {
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int pdsch_mcs = -1;
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int pdsch_max_mcs = 28;
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int pusch_mcs = -1;
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int pusch_max_mcs = 28;
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int nof_ctrl_symbols = 3;
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int max_aggr_level = 3;
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};
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struct cell_cfg_t {
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// Main cell configuration (used to calculate DCI locations in scheduler)
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srslte_cell_t cell;
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/* SIB configuration */
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cell_cfg_sib_t sibs[MAX_SIBS];
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uint32_t si_window_ms;
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/* pusch configuration */
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srslte_pusch_hopping_cfg_t pusch_hopping_cfg;
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/* prach configuration */
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uint32_t prach_config;
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uint32_t prach_nof_preambles;
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uint32_t prach_freq_offset;
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uint32_t prach_rar_window;
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uint32_t prach_contention_resolution_timer;
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uint32_t maxharq_msg3tx;
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uint32_t n1pucch_an;
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uint32_t delta_pucch_shift;
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// If non-negative, statically allocate N prbs at the edges of the uplink for PUCCH
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int nrb_pucch;
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uint32_t nrb_cqi;
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uint32_t ncs_an;
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uint32_t srs_subframe_config;
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uint32_t srs_subframe_offset;
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uint32_t srs_bw_config;
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struct scell_cfg_t {
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uint32_t enb_cc_idx = 0;
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bool cross_carrier_scheduling = false;
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bool ul_allowed = false;
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};
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std::vector<scell_cfg_t> scell_list;
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};
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struct ue_bearer_cfg_t {
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int priority = 0;
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int bsd = 0;
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int pbr = 0;
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int group = 0;
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enum { IDLE = 0, UL, DL, BOTH } direction = IDLE;
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};
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struct ant_info_ded_t {
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enum class tx_mode_t { tm1, tm2, tm3, tm4, tm5, tm6, tm7, tm8_v920, nulltype } tx_mode = tx_mode_t::tm1;
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enum class codebook_t {
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n2_tx_ant_tm3,
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n4_tx_ant_tm3,
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n2_tx_ant_tm4,
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n4_tx_ant_tm4,
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n2_tx_ant_tm5,
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n4_tx_ant_tm5,
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n2_tx_ant_tm6,
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n4_tx_ant_tm6,
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none
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} cookbook_subset_type = codebook_t::none;
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uint64_t codebook_subset_restrict;
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enum class ue_tx_ant_sel_t { release, closed_loop, open_loop } ue_tx_ant_sel = ue_tx_ant_sel_t::release;
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};
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struct ue_cfg_t {
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struct cc_cfg_t {
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bool active = false;
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uint32_t enb_cc_idx = 0; ///< eNB CC index
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};
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/* ue capabilities, etc */
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uint32_t maxharq_tx = 5;
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bool continuous_pusch;
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srslte_uci_offset_cfg_t uci_offset;
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srslte_pucch_cfg_t pucch_cfg = {};
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uint32_t aperiodic_cqi_period = 0; // if 0 is periodic CQI
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srslte_dl_cfg_t dl_cfg;
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std::array<ue_bearer_cfg_t, MAX_LC> ue_bearers = {};
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std::vector<cc_cfg_t> supported_cc_list; ///< list of UE supported CCs. First index for PCell
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ant_info_ded_t dl_ant_info;
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};
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typedef struct {
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uint32_t lcid;
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uint32_t nbytes;
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} dl_sched_pdu_t;
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typedef struct {
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uint32_t lcid;
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uint32_t lcid_buffer_size;
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uint32_t stop;
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uint8_t* mtch_payload;
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} dl_mtch_sched_t;
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typedef struct {
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dl_sched_pdu_t pdu[20];
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dl_mtch_sched_t mtch_sched[8];
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uint32_t num_mtch_sched;
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uint8_t* mcch_payload;
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uint32_t current_sf_allocation_num;
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} dl_pdu_mch_t;
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struct dl_sched_data_t {
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srslte_dci_dl_t dci;
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uint32_t tbs[SRSLTE_MAX_TB];
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bool mac_ce_ta;
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bool mac_ce_rnti;
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uint32_t nof_pdu_elems[SRSLTE_MAX_TB];
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dl_sched_pdu_t pdu[SRSLTE_MAX_TB][MAX_RLC_PDU_LIST];
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};
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typedef struct {
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bool needs_pdcch;
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uint32_t current_tx_nb;
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uint32_t tbs;
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srslte_dci_ul_t dci;
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} ul_sched_data_t;
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struct dl_sched_rar_info_t {
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uint32_t preamble_idx;
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uint32_t ta_cmd;
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uint16_t temp_crnti;
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uint32_t msg3_size;
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uint32_t prach_tti;
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};
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typedef struct {
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dl_sched_rar_info_t data;
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srslte_dci_rar_grant_t grant;
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} dl_sched_rar_grant_t;
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typedef struct {
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uint32_t tbs;
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srslte_dci_dl_t dci;
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uint32_t nof_grants;
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dl_sched_rar_grant_t msg3_grant[MAX_RAR_LIST];
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} dl_sched_rar_t;
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typedef struct {
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srslte_dci_dl_t dci;
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enum bc_type { BCCH, PCCH } type;
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uint32_t index;
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uint32_t tbs;
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} dl_sched_bc_t;
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typedef struct {
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uint32_t cfi;
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uint32_t nof_data_elems;
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uint32_t nof_rar_elems;
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uint32_t nof_bc_elems;
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dl_sched_data_t data[MAX_DATA_LIST];
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dl_sched_rar_t rar[MAX_RAR_LIST];
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dl_sched_bc_t bc[MAX_BC_LIST];
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} dl_sched_res_t;
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typedef struct {
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uint16_t rnti;
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enum phich_elem { ACK, NACK } phich;
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} ul_sched_phich_t;
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typedef struct {
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uint32_t nof_dci_elems;
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uint32_t nof_phich_elems;
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ul_sched_data_t pusch[MAX_DATA_LIST];
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ul_sched_phich_t phich[MAX_PHICH_LIST];
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} ul_sched_res_t;
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/******************* Scheduler Control ****************************/
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/* Provides cell configuration including SIB periodicity, etc. */
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virtual int cell_cfg(const std::vector<cell_cfg_t>& cell_cfg) = 0;
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virtual int reset() = 0;
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/* Manages UE scheduling context */
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virtual int ue_cfg(uint16_t rnti, const ue_cfg_t& cfg) = 0;
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virtual int ue_rem(uint16_t rnti) = 0;
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virtual bool ue_exists(uint16_t rnti) = 0;
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/* Manages UE bearers and associated configuration */
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virtual int bearer_ue_cfg(uint16_t rnti, uint32_t lc_id, ue_bearer_cfg_t* cfg) = 0;
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virtual int bearer_ue_rem(uint16_t rnti, uint32_t lc_id) = 0;
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virtual uint32_t get_ul_buffer(uint16_t rnti) = 0;
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virtual uint32_t get_dl_buffer(uint16_t rnti) = 0;
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/******************* Scheduling Interface ***********************/
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/* DL buffer status report */
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virtual int dl_rlc_buffer_state(uint16_t rnti, uint32_t lc_id, uint32_t tx_queue, uint32_t retx_queue) = 0;
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virtual int dl_mac_buffer_state(uint16_t rnti, uint32_t ce_code) = 0;
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/* DL information */
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virtual int dl_ack_info(uint32_t tti, uint16_t rnti, uint32_t enb_cc_idx, uint32_t tb_idx, bool ack) = 0;
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virtual int dl_rach_info(uint32_t enb_cc_idx, dl_sched_rar_info_t rar_info) = 0;
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virtual int dl_ri_info(uint32_t tti, uint16_t rnti, uint32_t enb_cc_idx, uint32_t ri_value) = 0;
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virtual int dl_pmi_info(uint32_t tti, uint16_t rnti, uint32_t enb_cc_idx, uint32_t pmi_value) = 0;
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virtual int dl_cqi_info(uint32_t tti, uint16_t rnti, uint32_t enb_cc_idx, uint32_t cqi_value) = 0;
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/* UL information */
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virtual int ul_crc_info(uint32_t tti, uint16_t rnti, uint32_t enb_cc_idx, bool crc) = 0;
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virtual int ul_sr_info(uint32_t tti, uint16_t rnti) = 0;
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virtual int ul_bsr(uint16_t rnti, uint32_t lcid, uint32_t bsr, bool set_value = true) = 0;
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virtual int ul_recv_len(uint16_t rnti, uint32_t lcid, uint32_t len) = 0;
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virtual int ul_phr(uint16_t rnti, int phr) = 0;
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virtual int ul_cqi_info(uint32_t tti, uint16_t rnti, uint32_t enb_cc_idx, uint32_t cqi, uint32_t ul_ch_code) = 0;
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/* Run Scheduler for this tti */
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virtual int dl_sched(uint32_t tti, uint32_t enb_cc_idx, dl_sched_res_t& sched_result) = 0;
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virtual int ul_sched(uint32_t tti, uint32_t enb_cc_idx, ul_sched_res_t& sched_result) = 0;
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/* Custom */
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virtual void set_dl_tti_mask(uint8_t* tti_mask, uint32_t nof_sfs) = 0;
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virtual const ue_cfg_t* get_ue_cfg(uint16_t rnti) = 0;
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};
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} // namespace srsenb
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#endif // SRSLTE_SCHED_INTERFACE_H
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