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260 lines
7.4 KiB
C++
260 lines
7.4 KiB
C++
/*
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* Copyright 2013-2019 Software Radio Systems Limited
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*
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* This file is part of srsLTE.
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*
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* srsLTE is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Affero General Public License as
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* published by the Free Software Foundation, either version 3 of
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* the License, or (at your option) any later version.
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*
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* srsLTE is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Affero General Public License for more details.
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*
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* A copy of the GNU Affero General Public License can be found in
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* the LICENSE file in the top-level directory of this distribution
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* and at http://www.gnu.org/licenses/.
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*
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*/
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#ifndef SRSENB_SCHEDULER_H
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#define SRSENB_SCHEDULER_H
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#include "scheduler_harq.h"
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#include "scheduler_ue.h"
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#include "srslte/common/bounded_bitset.h"
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#include "srslte/common/log.h"
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#include "srslte/interfaces/enb_interfaces.h"
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#include "srslte/interfaces/sched_interface.h"
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#include <map>
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#include <pthread.h>
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namespace srsenb {
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/* Caution: User addition (ue_cfg) and removal (ue_rem) are not thread-safe
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* Rest of operations are thread-safe
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*
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* The subclass sched_ue is thread-safe so that access to shared variables like buffer states
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* from scheduler thread and other threads is protected for each individual user.
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*/
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class sched : public sched_interface
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{
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public:
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/*************************************************************
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*
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* Scheduling metric interface definition
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*
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************************************************************/
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class metric_dl
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{
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public:
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/* Virtual methods for user metric calculation */
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virtual void
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sched_users(std::map<uint16_t, sched_ue>& ue_db, rbgmask_t* dl_mask, uint32_t nof_ctrl_symbols, uint32_t tti) = 0;
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};
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class metric_ul
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{
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public:
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/* Virtual methods for user metric calculation */
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virtual void sched_users(std::map<uint16_t, sched_ue>& ue_db, ul_mask_t* ul_mask, uint32_t tti) = 0;
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virtual bool update_allocation(ul_harq_proc::ul_alloc_t alloc) = 0;
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};
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/*************************************************************
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*
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* FAPI-like Interface
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*
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************************************************************/
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sched();
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~sched();
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void init(rrc_interface_mac *rrc, srslte::log *log);
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void set_metric(metric_dl *dl_metric, metric_ul *ul_metric);
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int cell_cfg(cell_cfg_t *cell_cfg);
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void set_sched_cfg(sched_args_t *sched_cfg);
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int reset();
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int ue_cfg(uint16_t rnti, ue_cfg_t *ue_cfg);
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int ue_rem(uint16_t rnti);
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bool ue_exists(uint16_t rnti);
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void phy_config_enabled(uint16_t rnti, bool enabled);
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int bearer_ue_cfg(uint16_t rnti, uint32_t lc_id, ue_bearer_cfg_t *cfg);
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int bearer_ue_rem(uint16_t rnti, uint32_t lc_id);
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uint32_t get_ul_buffer(uint16_t rnti);
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uint32_t get_dl_buffer(uint16_t rnti);
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int dl_rlc_buffer_state(uint16_t rnti, uint32_t lc_id, uint32_t tx_queue, uint32_t retx_queue);
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int dl_mac_buffer_state(uint16_t rnti, uint32_t ce_code);
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int dl_ant_info(uint16_t rnti, asn1::rrc::phys_cfg_ded_s::ant_info_c_* dedicated);
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int dl_ack_info(uint32_t tti, uint16_t rnti, uint32_t tb_idx, bool ack);
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int dl_rach_info(uint32_t tti, uint32_t ra_id, uint16_t rnti, uint32_t estimated_size);
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int dl_ri_info(uint32_t tti, uint16_t rnti, uint32_t ri_value);
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int dl_pmi_info(uint32_t tti, uint16_t rnti, uint32_t pmi_value);
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int dl_cqi_info(uint32_t tti, uint16_t rnti, uint32_t cqi_value);
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int ul_crc_info(uint32_t tti, uint16_t rnti, bool crc);
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int ul_sr_info(uint32_t tti, uint16_t rnti);
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int ul_bsr(uint16_t rnti, uint32_t lcid, uint32_t bsr, bool set_value = true);
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int ul_recv_len(uint16_t rnti, uint32_t lcid, uint32_t len);
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int ul_phr(uint16_t rnti, int phr);
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int ul_cqi_info(uint32_t tti, uint16_t rnti, uint32_t cqi, uint32_t ul_ch_code);
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int dl_sched(uint32_t tti, dl_sched_res_t *sched_result);
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int ul_sched(uint32_t tti, ul_sched_res_t *sched_result);
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/* Custom TPC functions
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*/
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void tpc_inc(uint16_t rnti);
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void tpc_dec(uint16_t rnti);
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static uint32_t get_rvidx(uint32_t retx_idx) {
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const static int rv_idx[4] = {0, 2, 3, 1};
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return rv_idx[retx_idx%4];
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}
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static void generate_cce_location(
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srslte_regs_t* regs, sched_ue::sched_dci_cce_t* location, uint32_t cfi, uint32_t sf_idx = 0, uint16_t rnti = 0);
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protected:
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metric_dl *dl_metric;
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metric_ul *ul_metric;
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srslte::log *log_h;
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rrc_interface_mac *rrc;
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pthread_rwlock_t rwlock;
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pthread_mutex_t sched_mutex;
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cell_cfg_t cfg;
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sched_args_t sched_cfg;
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const static int MAX_PRB = 100;
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const static int MAX_RBG = 25;
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const static int MAX_CCE = 128;
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// This is for computing DCI locations
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srslte_regs_t regs;
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class sched_vars
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{
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public:
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struct tti_vars_t {
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srslte::bounded_bitset<MAX_CCE, true> used_cce;
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uint32_t tti_rx = 0;
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tti_vars_t() : used_cce(MAX_CCE) {}
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};
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void init(sched* parent_);
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tti_vars_t& new_tti(uint32_t tti_rx);
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tti_vars_t& tti_vars(uint32_t tti_rx);
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private:
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static const uint32_t tti_array_size = 16;
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sched* parent = NULL;
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tti_vars_t tti_vars_[tti_array_size];
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};
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sched_vars sched_vars;
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typedef struct {
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int buf_rar;
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uint16_t rnti;
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uint32_t ra_id;
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uint32_t rar_tti;
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} sched_rar_t;
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typedef struct {
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bool is_in_window;
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uint32_t window_start;
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uint32_t n_tx;
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} sched_sib_t;
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int dl_sched_bc(dl_sched_bc_t bc[MAX_BC_LIST]);
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int dl_sched_rar(dl_sched_rar_t rar[MAX_RAR_LIST]);
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int dl_sched_data(dl_sched_data_t data[MAX_DATA_LIST]);
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void ul_sched_msg3();
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int generate_format1a(
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uint32_t rb_start, uint32_t l_crb, uint32_t tbs, uint32_t rv, uint16_t rnti, srslte_dci_dl_t* dci);
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int find_empty_dci(sched_ue::sched_dci_cce_t* locations,
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uint32_t aggr_level,
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sched_vars::tti_vars_t* tti_vars,
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sched_ue* user = NULL);
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bool generate_dci(srslte_dci_location_t* sched_location,
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sched_ue::sched_dci_cce_t* locations,
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uint32_t aggr_level,
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sched_vars::tti_vars_t* tti_vars,
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sched_ue* user = NULL);
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std::map<uint16_t, sched_ue> ue_db;
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typedef std::map<uint16_t, sched_ue>::iterator ue_db_it_t;
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sched_sib_t pending_sibs[MAX_SIBS];
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typedef struct {
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bool enabled;
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uint16_t rnti;
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uint32_t L;
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uint32_t n_prb;
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uint32_t mcs;
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} pending_msg3_t;
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const static int SCHED_MAX_PENDING_RAR = 8;
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sched_rar_t pending_rar[SCHED_MAX_PENDING_RAR];
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pending_msg3_t pending_msg3[10];
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// Allowed DCI locations for SIB and RAR per CFI
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sched_ue::sched_dci_cce_t common_locations[3];
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sched_ue::sched_dci_cce_t rar_locations[3][10];
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uint32_t bc_aggr_level;
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uint32_t rar_aggr_level;
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uint32_t pdsch_re[10];
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uint32_t avail_rbg;
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uint32_t P;
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uint32_t start_rbg;
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uint32_t si_n_rbg;
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uint32_t rar_n_rbg;
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uint32_t nof_rbg;
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uint32_t sf_idx;
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uint32_t sfn;
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uint32_t current_tti;
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uint32_t current_cfi;
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ul_mask_t ul_mask;
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rbgmask_t dl_mask;
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bool fail_dci_alloc = false;
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bool configured;
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};
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}
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#endif // SRSENB_SCHEDULER_H
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