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Andre Puschmann 16b5f4c3db ue_dl_nr_file_test: add further IQ capture with coreset0_idx=6 ... Cell 0x01: nr_arfcn=368500 ul_nr_arfcn=349500 pci=500 mode=FDD rat=nr n_rb_dl=52 n_rb_ul=52 dl_mu=0 ul_mu=0 ssb_mu=0 ssb_arfcn=368410 ssb_prb=13:21 k_ssb=6 coreset0_prb=1:48 coreset0_idx=6 12:58:46.197 [PHY] DL - 01 ffff 556.0 PDSCH: harq=si prb=1:7 symb=2:12 CW0: tb_len=84 mod=2 rv_idx=2 cr=0.44 0000: 74 81 01 70 10 40 04 02 00 00 c8 00 24 68 a0 38 t..p.@......$h.8 0010: 05 01 00 40 1a 00 00 06 6c 6d 92 21 f3 70 40 20 ...@....lm.!.p@ 0020: 00 00 80 80 00 41 06 80 a0 90 9c 20 08 55 19 40 .....A..... .U.@ 0030: 00 00 33 a1 c6 d9 22 40 10 00 1e b8 94 63 c0 09 ..3..."@.....c.. 0040: 28 c4 1b 8a 36 e1 5b 1c 3a 01 3c 5b 46 14 00 00 (...6.[.:.<[F... 0050: 00 00 00 00 .... 12:58:46.197 [PHY] DL - 01 ffff 556.0 PDCCH: ss_id=0 cce_index=0 al=4 dci=1_0 rb_alloc=0x120 time_domain_rsc=0 vrb_to_prb_map=0 mcs=6 rv_idx=2 si_indicator=0 dci_len=39		3 years ago
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examples	Batch of LGTM fixes.	3 years ago
include	rrc_nr_cfg: set default PLMN for NR cell to 00101	3 years ago
src	ue_dl_nr_file_test: add further IQ capture with coreset0_idx=6	3 years ago
test	rlc_um_nr_test: add extra check to verify reassembly timer isn't running	3 years ago
CMakeLists.txt	rename srsLTE to srsRAN	4 years ago