21 Commits (f9a668861acb40d033f526f9dd630bf4e8d95808)

Author	SHA1	Message	Date
Xavier Arteaga	baac179d95	Added vector complex sine generator	6 years ago
Xavier Arteaga	06a9d8eb6f	Added vector estimate frequency	6 years ago
Andre Puschmann	4b01a2e4a0	update copyright notice	6 years ago
Ismael Gomez	bc9d342959	New optimization on the PHY for both UE and eNodeB (#251) ... * New parallel Turbodecoder implementation in SSE/AVX 16-bit and 8-bit * Optimised UL Interleaver * Include TB CRC calculation in FEC encoder * New threading priorities	6 years ago
Ismael Gomez	e18ba937dc	Limit uplink signal normalization to avoid clipping	6 years ago
Xavier Arteaga	681b98ae50	Added vector CFO	7 years ago
Ismael Gomez	384e0f8649	Fixed UL interleaver (missing SIMD deinterleaver)	7 years ago
David Rupprecht	9d71bec7b6	Unified include guards	7 years ago
Andre Puschmann	57e0c01fc4	check max buffer length in hex print	7 years ago
Ismael Gomez	e16839d7a7	Merge branch 'next' into 16bit_avx_viterbi	7 years ago
yagoda	d749ee66f4	introducing 16 bit viterbi support	7 years ago
Xavier Arteaga	a01c5ea08f	Fixes #119: channel estimation subframe averaging	7 years ago
Ismael Gomez	a3a1d268b7	Improved CFO estimation/correction by filtering central 6 PRB. Cleaned ue_sync/sync/pss objects. Used const attr in vector and other objects	7 years ago
yagoda	38903de07c	adding simd xor functionality	7 years ago
Ismael Gomez	dbae016b00	Removed unused vector functions	7 years ago
Xavier Arteaga	9e5f999666	Added more functions	7 years ago
Xavier Arteaga	c9f6bfccd4	Refactored vector library with SIMD independent architecture inline functions test-benchmark	7 years ago
Xavier Arteaga	0947173fc1	Merge branch 'next' into next_mimo	7 years ago
Ismael Gomez	616e18c570	fixed PUCCH correlation estimator	7 years ago
Xavier Arteaga	48d508aeba	Added srs_lte_cpy for aligned copy which improves a bit performance for aligned data	7 years ago
Andre Puschmann	d079d25b2c	rename srslte folder and src subfolder	8 years ago