1950 Commits (39bec9aab18d88006efa833e93c1496aee4f6631)

Author SHA1 Message Date
Xavier Arteaga 39bec9aab1 SRSLTE: fix RLC reordering and segment overlaping 5 years ago
Xavier Arteaga d3537fc340 srsLTE: expanded RLC stress test with the addition of multiple PDU per TTI in reverse order 5 years ago
Francisco Paisana 5ae3afd2b8 created cbit_ref for unpacking const buffers 5 years ago
Francisco Paisana 58e555e86c update all asn1 files 5 years ago
Francisco Paisana 5468189cd9 fix some variables' naming (e.g. x2_ap -> x2ap, e_rab -> erab) 5 years ago
Francisco Paisana 2a83eee0ee fix security key setup 5 years ago
Francisco Paisana ee24b59924 converted s1ap to new s1ap asn1 lib. Cleaned up bitstring packing/unpacking and bitstring types 5 years ago
Francisco Paisana 25bb36cdc3 converted ho preparation to new s1ap asn1 lib. Extended s1ap test 5 years ago
Francisco Paisana 3066b404ac fix integer ext asn1 generation 5 years ago
Francisco Paisana c87de9d889 added s1ap_asn1_test 5 years ago
Francisco Paisana b6c53d786b updated s1ap rrc interface with new asn1 lib types 5 years ago
Francisco Paisana 61b3e6b57e imported new s1ap asn1 lib 5 years ago
Andre Puschmann b43c531c15 adding CMW500 SLSS capture and enable PSBCH test 5 years ago
Andre Puschmann d98bc71057 fix PSBCH and use UL-SCH interleaver 5 years ago
Andre Puschmann 9012ca5faa fix PSBCH tests 5 years ago
Andre Puschmann 2e7a357226 expose UL-SCH interleaver to use in Sidelink 5 years ago
Andre Puschmann b0bfc7956d use const& in metrics interface 5 years ago
Xavier Arteaga bca5d1a95a srsLTE: extend viterbi test 5 years ago
Francisco Paisana 182a721329 fix some integer printf potential warnings 5 years ago
Xavier Arteaga 8a666ee455 srsLTE: Increase UHD default sampling rate. Enables warning if USB2 is used. 5 years ago
Andre Puschmann be4ba504bd fix another bunch of uninit memory in tests, and one in srsENB 5 years ago
Andre Puschmann 0554064bf0 refactor NPBCH init, fix memset with zero length 5 years ago
Andre Puschmann 0394d21dd2 fix uninit memory in chest sl test when not test is executed 5 years ago
Andre Puschmann 06afe74bef add virtual dtor in sched_interface base class 5 years ago
Andre Puschmann 6ec573987a remove default value for 'blocking' param from pdcp::write_sdu()
there were two defaults and one was shadowing the other. This
commit removes both defaults and uses blocking-mode for RRC
calls to PDCP in the UE. The eNB write_sdu() uses the non-blocking
mode by default. We have to review the eNB's RRC perhaps and use blocking
there too and non-blocking only for data plane
5 years ago
Andre Puschmann 1155adf007 fixing printfs in asn1_utils 5 years ago
Andre Puschmann 0bd493b567 call byte_buffer cleanup in two enb tests and fix typo 5 years ago
Andre Puschmann c54fa568be fixing typo in CMake for PHY DL test 5 years ago
Andre Puschmann 03512547f5 add test for Sidelink channel estimator 5 years ago
Xavier Arteaga 0912701cb0 srsLTE: sidelink minor corrections 5 years ago
Andre Puschmann 7de51c8236 refactor Sidelink PSBCH and DMRS code 5 years ago
Xavier Arteaga 36b2102de8 SRSUE: avoid testing ue_phy_test 5 years ago
Xavier Arteaga 307c27dc30 srsLTE: ZMQ renamed struct field 5 years ago
Xavier Arteaga 2d98f92823 srsLTE: upgraded ZMQ for supporting frequency selection 5 years ago
Xavier Arteaga 11eafa8ab4 srsLTE: FFTW wisdom gets loaded and saved by default 5 years ago
Xavier Arteaga 892ece8cdd srsLTE: reduce number of SF for rf_zmq_test 5 years ago
Xavier Arteaga c92dce71b7 srsLTE: AGC only uses boundaries for requesting gain to Radio 5 years ago
Xavier Arteaga 097f492430 srsLTE: fix ZMQ RF module gain 5 years ago
Andre Puschmann 9e1b8bc95e disabling certain PHY DL tests that aren't working on ARM due to Turbo issues 5 years ago
Pedro Alvarez 6d4303cd94 Added option to force 32bit compilation (useful for debug). Fixed various warnings when compiling in a 32 bit arch. 5 years ago
Xavier Arteaga a96a7fe20a Removed srsue_phy from thread_test 5 years ago
Xavier Arteaga 089a5e21dc Label test that memcheck is excessively long 5 years ago
Xavier Arteaga b1c4cd7189 srsLTE: removed timout in tti semaphore 5 years ago
Xavier Arteaga 6bef91a788 srsLTE: TTI sempahore wait for all resuses wait code. 5 years ago
Xavier Arteaga ad46fc006f srsLTE: Fix thread memory leak. Moved test. Fix CLang warnings. 5 years ago
Xavier Arteaga a7e92c384e srsLTE: applied minor comments in tti semaphore 5 years ago
Xavier Arteaga 447ede327c srsLTE: removed unused argument 5 years ago
Xavier Arteaga 384c420c7c SRSUE: fix phy workers concurrency issue 5 years ago
Xavier Arteaga 173defd676 srsLTE: Execute load and save FFTW wisdom automatically 5 years ago
Xavier Arteaga 9c51af491a SRSUE: phy default arguments are set in constructor 5 years ago