42 Commits (37fc1c59e382b9d3547303a5c1b88eadeb04c6b1)

Author	SHA1	Message	Date
Andre Puschmann	07d2bc4fe8	change license header to agnostic version with hint to root LICENSE file	4 years ago
Xavier Arteaga	35bf5b8c6d	Added generic memory malloc	4 years ago
Xavier Arteaga	83dddae525	Added vector zero	4 years ago
Xavier Arteaga	2c4aa1e379	Added Polar and LDPC forward error correction	4 years ago
Xavier Arteaga	ede58319ae	Vector: added conjugate complex float to short	4 years ago
yagoda	ec7873e7cc	refactoring PRACH, adding phase correction to successive cancellation	4 years ago
Xavier Arteaga	2d39c7261c	renamed vector copy prefix from to	5 years ago
luis_pereira87	baf0ad5bf4	PSSCH implementation	5 years ago
Xavier Arteaga	562590e595	Fix LGTM warnings	5 years ago
Andre Puschmann	e495c4d553	vector: add uint8 zero'ing function	5 years ago
Xavier Arteaga	8bf7acdeaf	Added vector malloc for i32 and u32	5 years ago
Xavier Arteaga	e832769ae6	Updated copyright	5 years ago
Xavier Arteaga	44a5ce172e	Added vector srslte_vec_avg_power_sf	5 years ago
Xavier Arteaga	f261365c91	Initial EVM calculation commit and other easthetic changes	5 years ago
Xavier Arteaga	9ee651d094	srsLTE: Added set vector zeros for float and cf	5 years ago
Xavier Arteaga	bca5d1a95a	srsLTE: extend viterbi test	5 years ago
Pedro Alvarez	c5979f59eb	Clang format UE, eNB and lib (#850) ... * Clang-formated UE, eNB and lib. * Fixed compiling errors from clang-format. * Fix linking issues introduced by clang-format * Fix poor formating in initializing arrays of arrays. * Fix mistake in conflict resolution on rm_turbo.c * Re-apply clang format to gtpc_ies.h	5 years ago
Xavier Arteaga	78dd9d7854	SRSLTE: Added float and complex vector allocation	5 years ago
Xavier Arteaga	8dd1c59e18	Added amplitude and power conversions to dB and viceversa	5 years ago
Xavier Arteaga	423475173d	Refactored magnitude and argument extraction from sf_worker	5 years ago
Xavier Arteaga	10480f62b3	SRSENB: Split sf_worker and cc_worker	5 years ago
Xavier Arteaga	baac179d95	Added vector complex sine generator	6 years ago
Xavier Arteaga	06a9d8eb6f	Added vector estimate frequency	6 years ago
Andre Puschmann	4b01a2e4a0	update copyright notice	6 years ago
Ismael Gomez	bc9d342959	New optimization on the PHY for both UE and eNodeB (#251) ... * New parallel Turbodecoder implementation in SSE/AVX 16-bit and 8-bit * Optimised UL Interleaver * Include TB CRC calculation in FEC encoder * New threading priorities	6 years ago
Ismael Gomez	e18ba937dc	Limit uplink signal normalization to avoid clipping	7 years ago
Xavier Arteaga	681b98ae50	Added vector CFO	7 years ago
Ismael Gomez	384e0f8649	Fixed UL interleaver (missing SIMD deinterleaver)	7 years ago
David Rupprecht	9d71bec7b6	Unified include guards	7 years ago
Andre Puschmann	57e0c01fc4	check max buffer length in hex print	7 years ago
Ismael Gomez	e16839d7a7	Merge branch 'next' into 16bit_avx_viterbi	7 years ago
yagoda	d749ee66f4	introducing 16 bit viterbi support	7 years ago
Xavier Arteaga	a01c5ea08f	Fixes #119: channel estimation subframe averaging	7 years ago
Ismael Gomez	a3a1d268b7	Improved CFO estimation/correction by filtering central 6 PRB. Cleaned ue_sync/sync/pss objects. Used const attr in vector and other objects	7 years ago
yagoda	38903de07c	adding simd xor functionality	7 years ago
Ismael Gomez	dbae016b00	Removed unused vector functions	7 years ago
Xavier Arteaga	9e5f999666	Added more functions	7 years ago
Xavier Arteaga	c9f6bfccd4	Refactored vector library with SIMD independent architecture inline functions test-benchmark	7 years ago
Xavier Arteaga	0947173fc1	Merge branch 'next' into next_mimo	7 years ago
Ismael Gomez	616e18c570	fixed PUCCH correlation estimator	7 years ago
Xavier Arteaga	48d508aeba	Added srs_lte_cpy for aligned copy which improves a bit performance for aligned data	7 years ago
Andre Puschmann	d079d25b2c	rename srslte folder and src subfolder	8 years ago