From fe0db905c21a6b8ede89fb31344d78b8dd0ab925 Mon Sep 17 00:00:00 2001 From: Andre Puschmann Date: Tue, 16 Nov 2021 21:14:31 +0100 Subject: [PATCH] sched_nr: move DCI config for SIB to fill_dci_sib() --- srsgnb/src/stack/mac/sched_nr_grant_allocator.cc | 3 --- srsgnb/src/stack/mac/sched_nr_signalling.cc | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/srsgnb/src/stack/mac/sched_nr_grant_allocator.cc b/srsgnb/src/stack/mac/sched_nr_grant_allocator.cc index 6dab7df6d..52b448935 100644 --- a/srsgnb/src/stack/mac/sched_nr_grant_allocator.cc +++ b/srsgnb/src/stack/mac/sched_nr_grant_allocator.cc @@ -99,9 +99,6 @@ alloc_result bwp_slot_allocator::alloc_si(uint32_t aggr_idx, return alloc_result::invalid_coderate; } - pdcch.dci.coreset0_bw = pdcch.dci_cfg.coreset0_bw; - pdcch.dci.ctx.coreset_start_rb = cfg.cfg.pdcch.coreset[0].offset_rb; - // Generate PDSCH bwp_pdcch_slot.dl.phy.pdsch.emplace_back(); pdsch_t& pdsch = bwp_pdcch_slot.dl.phy.pdsch.back(); diff --git a/srsgnb/src/stack/mac/sched_nr_signalling.cc b/srsgnb/src/stack/mac/sched_nr_signalling.cc index 753203d9c..f87fb67b2 100644 --- a/srsgnb/src/stack/mac/sched_nr_signalling.cc +++ b/srsgnb/src/stack/mac/sched_nr_signalling.cc @@ -114,6 +114,8 @@ bool fill_dci_sib(prb_interval interv, dci.ctx.rnti_type = srsran_rnti_type_si; dci.ctx.rnti = SRSRAN_SIRNTI; dci.ctx.coreset_id = 0; + dci.ctx.coreset_start_rb = bwp_cfg.cfg.pdcch.coreset[0].offset_rb; + dci.coreset0_bw = srsran_coreset_get_bw(&bwp_cfg.cfg.pdcch.coreset[0]); dci.freq_domain_assigment = srsran_ra_nr_type1_riv(srsran_coreset_get_bw(&bwp_cfg.cfg.pdcch.coreset[0]), interv.start(), interv.length()); dci.time_domain_assigment = 0;