From d61d6aa59fd8088c7b7b5088521ce14e500b31de Mon Sep 17 00:00:00 2001 From: Xavier Arteaga Date: Tue, 17 Aug 2021 13:36:23 +0200 Subject: [PATCH] Integrated CORESET0 into UE's RRC --- lib/src/phy/ch_estimation/dmrs_pdcch.c | 5 +++- lib/src/phy/phch/pdcch_nr.c | 7 +++-- srsue/src/stack/rrc/rrc_nr.cc | 40 ++++++++++++++++++++++++++ 3 files changed, 48 insertions(+), 4 deletions(-) diff --git a/lib/src/phy/ch_estimation/dmrs_pdcch.c b/lib/src/phy/ch_estimation/dmrs_pdcch.c index 914992fdc..9cc1a00bf 100644 --- a/lib/src/phy/ch_estimation/dmrs_pdcch.c +++ b/lib/src/phy/ch_estimation/dmrs_pdcch.c @@ -290,6 +290,9 @@ void srsran_dmrs_pdcch_estimator_free(srsran_dmrs_pdcch_estimator_t* q) static void srsran_dmrs_pdcch_extract(srsran_dmrs_pdcch_estimator_t* q, uint32_t cinit, const cf_t* sf_symbol, cf_t* lse) { + // Get CORESET offset + uint32_t offset_k = q->coreset.offset_rb * SRSRAN_NRE; + // Initialise pseudo-random sequence srsran_sequence_state_t sequence_state = {}; srsran_sequence_state_init(&sequence_state, cinit); @@ -328,7 +331,7 @@ srsran_dmrs_pdcch_extract(srsran_dmrs_pdcch_estimator_t* q, uint32_t cinit, cons uint32_t k = n * SRSRAN_NRE + 4 * k_prime + 1; // Extract symbol - lse[idx] = sf_symbol[k]; + lse[idx] = sf_symbol[k + offset_k]; } } diff --git a/lib/src/phy/phch/pdcch_nr.c b/lib/src/phy/phch/pdcch_nr.c index 055f8bb3a..b5be24d35 100644 --- a/lib/src/phy/phch/pdcch_nr.c +++ b/lib/src/phy/phch/pdcch_nr.c @@ -310,7 +310,8 @@ static uint32_t pdcch_nr_cp(const srsran_pdcch_nr_t* q, cf_t* symbols, bool put) { - uint32_t L = 1U << dci_location->L; + uint32_t offset_k = q->coreset.offset_rb * SRSRAN_NRE; + uint32_t L = 1U << dci_location->L; // Calculate begin and end sub-carrier index for the selected candidate uint32_t k_begin = (dci_location->ncce * SRSRAN_NRE * 6) / q->coreset.duration; @@ -327,9 +328,9 @@ static uint32_t pdcch_nr_cp(const srsran_pdcch_nr_t* q, for (uint32_t i = r * 6 * SRSRAN_NRE; i < (r + 1) * 6 * SRSRAN_NRE; i++, k++) { if (k >= k_begin && k < k_end && k % 4 != 1) { if (put) { - slot_grid[q->carrier.nof_prb * SRSRAN_NRE * l + i] = symbols[count++]; + slot_grid[q->carrier.nof_prb * SRSRAN_NRE * l + i + offset_k] = symbols[count++]; } else { - symbols[count++] = slot_grid[q->carrier.nof_prb * SRSRAN_NRE * l + i]; + symbols[count++] = slot_grid[q->carrier.nof_prb * SRSRAN_NRE * l + i + offset_k]; } } } diff --git a/srsue/src/stack/rrc/rrc_nr.cc b/srsue/src/stack/rrc/rrc_nr.cc index a5caada5c..f151d859c 100644 --- a/srsue/src/stack/rrc/rrc_nr.cc +++ b/srsue/src/stack/rrc/rrc_nr.cc @@ -16,6 +16,7 @@ #include "srsran/interfaces/ue_pdcp_interfaces.h" #include "srsran/interfaces/ue_rlc_interfaces.h" #include "srsue/hdr/stack/upper/usim.h" +#include "srsran/common/band_helper.h" #define Error(fmt, ...) rrc_ptr->logger.error("Proc \"%s\" - " fmt, name(), ##__VA_ARGS__) #define Warning(fmt, ...) rrc_ptr->logger.warning("Proc \"%s\" - " fmt, name(), ##__VA_ARGS__) @@ -784,6 +785,45 @@ bool rrc_nr::apply_dl_common_cfg(const asn1::rrc_nr::dl_cfg_common_s& dl_cfg_com if (dl_cfg_common.init_dl_bwp.pdsch_cfg_common.type() == asn1::rrc_nr::setup_release_c::types_opts::setup) { const pdcch_cfg_common_s& pdcch_cfg_common = dl_cfg_common.init_dl_bwp.pdcch_cfg_common.setup(); + + // Load CORESET Zero + if (pdcch_cfg_common.ctrl_res_set_zero_present) { + srsran::srsran_band_helper band_helper; + + // Get band number + uint16_t band = band_helper.get_band_from_dl_arfcn(phy_cfg.carrier.absolute_frequency_point_a); + + // Get pointA and SSB absolute frequencies + double pointA_abs_freq_Hz = band_helper.nr_arfcn_to_freq(phy_cfg.carrier.absolute_frequency_point_a); + double ssb_abs_freq_Hz = band_helper.nr_arfcn_to_freq(phy_cfg.carrier.absolute_frequency_ssb); + + // Calculate integer SSB to pointA frequency offset in Hz + uint32_t ssb_pointA_freq_offset_Hz = + (ssb_abs_freq_Hz > pointA_abs_freq_Hz) ? (uint32_t)(ssb_abs_freq_Hz - pointA_abs_freq_Hz) : 0; + + // TODO: Select subcarrier spacing from SSB (depending on band) + srsran_subcarrier_spacing_t ssb_scs = srsran_subcarrier_spacing_30kHz ; + + // Select PDCCH subcarrrier spacing from PDCCH BWP + srsran_subcarrier_spacing_t pdcch_scs = phy_cfg.carrier.scs; + + // Make CORESET Zero from provided field and given subcarrier spacing + srsran_coreset_t coreset0 = {}; + if (srsran_coreset_zero( + ssb_pointA_freq_offset_Hz, ssb_scs, pdcch_scs, pdcch_cfg_common.ctrl_res_set_zero, &coreset0) < + SRSASN_SUCCESS) { + logger.warning("Not possible to create CORESET Zero (ssb_scs=%s, pdcch_scs=%s, idx=%d)", + srsran_subcarrier_spacing_to_str(ssb_scs), + srsran_subcarrier_spacing_to_str(pdcch_scs), + pdcch_cfg_common.ctrl_res_set_zero); + return false; + } + + // Write CORESET Zero in index 0 + phy_cfg.pdcch.coreset[0] = coreset0; + phy_cfg.pdcch.coreset_present[0] = true; + } + if (pdcch_cfg_common.common_ctrl_res_set_present) { srsran_coreset_t coreset; if (make_phy_coreset_cfg(pdcch_cfg_common.common_ctrl_res_set, &coreset) == true) {