From d39183419c875bf597bc8a499ae8f2fd6a50d179 Mon Sep 17 00:00:00 2001 From: Francisco Paisana Date: Tue, 27 Apr 2021 10:12:40 +0100 Subject: [PATCH] Separate TPC PUSCH and PUCCH target SINR (#2740) * separate target pusch and pucch sinr configurations in tpc class and rr.conf --- .../interfaces/enb_rrc_interface_types.h | 3 +- .../srsran/interfaces/sched_interface.h | 5 ++- srsenb/hdr/stack/mac/sched_ue_ctrl/tpc.h | 25 ++++++++++----- srsenb/rr.conf.example | 4 ++- srsenb/src/enb_cfg_parser.cc | 3 +- .../stack/mac/sched_ue_ctrl/sched_ue_cell.cc | 5 ++- srsenb/src/stack/rrc/rrc.cc | 21 +++++++------ srsenb/test/mac/sched_test_rand.cc | 3 +- srsenb/test/mac/sched_test_utils.h | 31 ++++++++++--------- srsenb/test/mac/sched_tpc_test.cc | 4 +-- 10 files changed, 64 insertions(+), 40 deletions(-) diff --git a/lib/include/srsran/interfaces/enb_rrc_interface_types.h b/lib/include/srsran/interfaces/enb_rrc_interface_types.h index e90017768..093bcb343 100644 --- a/lib/include/srsran/interfaces/enb_rrc_interface_types.h +++ b/lib/include/srsran/interfaces/enb_rrc_interface_types.h @@ -56,7 +56,8 @@ struct cell_cfg_t { double dl_freq_hz; uint32_t ul_earfcn; double ul_freq_hz; - int target_ul_sinr_db; + int target_pucch_sinr_db; + int target_pusch_sinr_db; uint32_t initial_dl_cqi; bool enable_phr_handling; std::vector scell_list; diff --git a/lib/include/srsran/interfaces/sched_interface.h b/lib/include/srsran/interfaces/sched_interface.h index 3ac0091ae..bbb8e9956 100644 --- a/lib/include/srsran/interfaces/sched_interface.h +++ b/lib/include/srsran/interfaces/sched_interface.h @@ -65,9 +65,12 @@ public: cell_cfg_sib_t sibs[MAX_SIBS]; uint32_t si_window_ms; + /* pucch configuration */ + float target_pucch_ul_sinr; + /* pusch configuration */ srsran_pusch_hopping_cfg_t pusch_hopping_cfg; - float target_ul_sinr; + float target_pusch_ul_sinr; bool enable_phr_handling; bool enable_64qam; diff --git a/srsenb/hdr/stack/mac/sched_ue_ctrl/tpc.h b/srsenb/hdr/stack/mac/sched_ue_ctrl/tpc.h index ed2c5b6d7..e65b86149 100644 --- a/srsenb/hdr/stack/mac/sched_ue_ctrl/tpc.h +++ b/srsenb/hdr/stack/mac/sched_ue_ctrl/tpc.h @@ -35,15 +35,23 @@ public: static constexpr uint32_t PUSCH_CODE = 0, PUCCH_CODE = 1; static constexpr int PHR_NEG_NOF_PRB = 1; - explicit tpc(uint32_t cell_nof_prb, float target_snr_dB_ = -1.0, bool phr_handling_flag_ = false) : + explicit tpc(uint32_t cell_nof_prb, + float target_pucch_snr_dB_ = -1.0, + float target_pusch_sn_dB_ = -1.0, + bool phr_handling_flag_ = false) : nof_prb(cell_nof_prb), - target_snr_dB(target_snr_dB_), - snr_estim_list({ul_ch_snr_estim{target_snr_dB_}, ul_ch_snr_estim{target_snr_dB_}}), + target_pucch_snr_dB(target_pucch_snr_dB_), + target_pusch_snr_dB(target_pusch_sn_dB_), + snr_estim_list({ul_ch_snr_estim{target_pusch_snr_dB}, ul_ch_snr_estim{target_pucch_snr_dB}}), phr_handling_flag(phr_handling_flag_) { max_prbs_cached = nof_prb; } - void set_cfg(float target_snr_dB_) { target_snr_dB = target_snr_dB_; } + void set_cfg(float target_pusch_snr_dB_, float target_pucch_snr_dB_) + { + target_pucch_snr_dB = target_pucch_snr_dB_; + target_pusch_snr_dB = target_pusch_snr_dB_; + } void set_snr(float snr, uint32_t ul_ch_code) { @@ -72,7 +80,9 @@ public: void new_tti() { - for (auto& ch_snr : snr_estim_list) { + for (size_t chidx = 0; chidx < 2; ++chidx) { + float target_snr_dB = chidx == PUSCH_CODE ? target_pusch_snr_dB : target_pucch_snr_dB; + auto& ch_snr = snr_estim_list[chidx]; if (target_snr_dB < 0) { ch_snr.pending_delta = 0; continue; @@ -130,7 +140,8 @@ private: } uint8_t enconde_tpc(uint32_t cc) { - auto& ch_snr = snr_estim_list[cc]; + float target_snr_dB = cc == PUSCH_CODE ? target_pusch_snr_dB : target_pucch_snr_dB; + auto& ch_snr = snr_estim_list[cc]; assert(ch_snr.pending_delta == 0); // ensure called once per {cc,tti} if (target_snr_dB < 0) { // undefined target SINR case. Increase Tx power once per PHR, considering the number of allocable PRBs remains @@ -158,7 +169,7 @@ private: } uint32_t nof_prb; - float target_snr_dB; + float target_pucch_snr_dB, target_pusch_snr_dB; bool phr_handling_flag; // PHR-related variables diff --git a/srsenb/rr.conf.example b/srsenb/rr.conf.example index 77362484e..1390f179f 100644 --- a/srsenb/rr.conf.example +++ b/srsenb/rr.conf.example @@ -62,7 +62,9 @@ cell_list = //ul_earfcn = 21400; ho_active = false; //meas_gap_period = 0; // 0 (inactive), 40 or 80 - //allowed_meas_bw = 6; + // target_pusch_sinr = -1; + // target_pucch_sinr = -1; + // allowed_meas_bw = 6; // CA cells scell_list = ( diff --git a/srsenb/src/enb_cfg_parser.cc b/srsenb/src/enb_cfg_parser.cc index 547fe34a5..98d8127ef 100644 --- a/srsenb/src/enb_cfg_parser.cc +++ b/srsenb/src/enb_cfg_parser.cc @@ -749,7 +749,8 @@ static int parse_cell_list(all_args_t* args, rrc_cfg_t* rrc_cfg, Setting& root) cell_cfg.root_seq_idx, cellroot, "root_seq_idx", rrc_cfg->sibs[1].sib2().rr_cfg_common.prach_cfg.root_seq_idx); parse_default_field(cell_cfg.initial_dl_cqi, cellroot, "initial_dl_cqi", 5u); parse_default_field(cell_cfg.meas_cfg.meas_gap_period, cellroot, "meas_gap_period", 0u); - HANDLEPARSERCODE(parse_default_field(cell_cfg.target_ul_sinr_db, cellroot, "target_ul_sinr", -1)); + HANDLEPARSERCODE(parse_default_field(cell_cfg.target_pusch_sinr_db, cellroot, "target_pusch_sinr", -1)); + HANDLEPARSERCODE(parse_default_field(cell_cfg.target_pucch_sinr_db, cellroot, "target_pucch_sinr", -1)); HANDLEPARSERCODE(parse_default_field(cell_cfg.enable_phr_handling, cellroot, "enable_phr_handling", false)); parse_default_field(cell_cfg.meas_cfg.allowed_meas_bw, cellroot, "allowed_meas_bw", 6u); srsran_assert(srsran::is_lte_cell_nof_prb(cell_cfg.meas_cfg.allowed_meas_bw), "Invalid measurement Bandwidth"); diff --git a/srsenb/src/stack/mac/sched_ue_ctrl/sched_ue_cell.cc b/srsenb/src/stack/mac/sched_ue_ctrl/sched_ue_cell.cc index fba4cb40d..f1ec7c8ef 100644 --- a/srsenb/src/stack/mac/sched_ue_ctrl/sched_ue_cell.cc +++ b/srsenb/src/stack/mac/sched_ue_ctrl/sched_ue_cell.cc @@ -27,7 +27,10 @@ sched_ue_cell::sched_ue_cell(uint16_t rnti_, const sched_cell_params_t& cell_cfg cell_cfg(&cell_cfg_), dci_locations(generate_cce_location_table(rnti_, cell_cfg_)), harq_ent(SCHED_MAX_HARQ_PROC, SCHED_MAX_HARQ_PROC), - tpc_fsm(cell_cfg->nof_prb(), cell_cfg->cfg.target_ul_sinr, cell_cfg->cfg.enable_phr_handling), + tpc_fsm(cell_cfg->nof_prb(), + cell_cfg->cfg.target_pucch_ul_sinr, + cell_cfg->cfg.target_pusch_ul_sinr, + cell_cfg->cfg.enable_phr_handling), fixed_mcs_dl(cell_cfg_.sched_cfg->pdsch_mcs), fixed_mcs_ul(cell_cfg_.sched_cfg->pusch_mcs), current_tti(current_tti_), diff --git a/srsenb/src/stack/rrc/rrc.cc b/srsenb/src/stack/rrc/rrc.cc index c4015e277..c85aec7c9 100644 --- a/srsenb/src/stack/rrc/rrc.cc +++ b/srsenb/src/stack/rrc/rrc.cc @@ -724,16 +724,17 @@ void rrc::config_mac() item.si_window_ms = cfg.sib1.si_win_len.to_number(); item.prach_rar_window = cfg.sibs[1].sib2().rr_cfg_common.rach_cfg_common.ra_supervision_info.ra_resp_win_size.to_number(); - item.prach_freq_offset = cfg.sibs[1].sib2().rr_cfg_common.prach_cfg.prach_cfg_info.prach_freq_offset; - item.maxharq_msg3tx = cfg.sibs[1].sib2().rr_cfg_common.rach_cfg_common.max_harq_msg3_tx; - item.enable_64qam = cfg.sibs[1].sib2().rr_cfg_common.pusch_cfg_common.pusch_cfg_basic.enable64_qam; - item.initial_dl_cqi = cfg.cell_list[ccidx].initial_dl_cqi; - item.target_ul_sinr = cfg.cell_list[ccidx].target_ul_sinr_db; - item.enable_phr_handling = cfg.cell_list[ccidx].enable_phr_handling; - item.delta_pucch_shift = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.delta_pucch_shift.to_number(); - item.ncs_an = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.ncs_an; - item.n1pucch_an = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.n1_pucch_an; - item.nrb_cqi = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.nrb_cqi; + item.prach_freq_offset = cfg.sibs[1].sib2().rr_cfg_common.prach_cfg.prach_cfg_info.prach_freq_offset; + item.maxharq_msg3tx = cfg.sibs[1].sib2().rr_cfg_common.rach_cfg_common.max_harq_msg3_tx; + item.enable_64qam = cfg.sibs[1].sib2().rr_cfg_common.pusch_cfg_common.pusch_cfg_basic.enable64_qam; + item.initial_dl_cqi = cfg.cell_list[ccidx].initial_dl_cqi; + item.target_pucch_ul_sinr = cfg.cell_list[ccidx].target_pucch_sinr_db; + item.target_pusch_ul_sinr = cfg.cell_list[ccidx].target_pusch_sinr_db; + item.enable_phr_handling = cfg.cell_list[ccidx].enable_phr_handling; + item.delta_pucch_shift = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.delta_pucch_shift.to_number(); + item.ncs_an = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.ncs_an; + item.n1pucch_an = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.n1_pucch_an; + item.nrb_cqi = cfg.sibs[1].sib2().rr_cfg_common.pucch_cfg_common.nrb_cqi; item.nrb_pucch = SRSRAN_MAX(cfg.sr_cfg.nof_prb, cfg.cqi_cfg.nof_prb); logger.info("Allocating %d PRBs for PUCCH", item.nrb_pucch); diff --git a/srsenb/test/mac/sched_test_rand.cc b/srsenb/test/mac/sched_test_rand.cc index c1ff6b4e1..e63519f06 100644 --- a/srsenb/test/mac/sched_test_rand.cc +++ b/srsenb/test/mac/sched_test_rand.cc @@ -271,7 +271,8 @@ sched_sim_events rand_sim_params(uint32_t nof_ttis) sched_sim_event_generator generator; sim_gen.sim_args.cell_cfg = {generate_default_cell_cfg(nof_prb)}; - sim_gen.sim_args.cell_cfg[0].target_ul_sinr = pick_random_uniform({10, 15, 20, -1}); + sim_gen.sim_args.cell_cfg[0].target_pucch_ul_sinr = pick_random_uniform({10, 15, 20, -1}); + sim_gen.sim_args.cell_cfg[0].target_pusch_ul_sinr = pick_random_uniform({10, 15, 20, -1}); sim_gen.sim_args.cell_cfg[0].enable_phr_handling = false; sim_gen.sim_args.default_ue_sim_cfg.ue_cfg = generate_default_ue_cfg(); sim_gen.sim_args.default_ue_sim_cfg.periodic_cqi = true; diff --git a/srsenb/test/mac/sched_test_utils.h b/srsenb/test/mac/sched_test_utils.h index f1efd695c..003724629 100644 --- a/srsenb/test/mac/sched_test_utils.h +++ b/srsenb/test/mac/sched_test_utils.h @@ -40,21 +40,22 @@ inline srsenb::sched_interface::cell_cfg_t generate_default_cell_cfg(uint32_t no cell_cfg_phy.phich_length = SRSRAN_PHICH_NORM; cell_cfg_phy.phich_resources = SRSRAN_PHICH_R_1; - cell_cfg.sibs[0].len = 18; - cell_cfg.sibs[0].period_rf = 8; - cell_cfg.sibs[1].len = 41; - cell_cfg.sibs[1].period_rf = 16; - cell_cfg.si_window_ms = 40; - cell_cfg.nrb_pucch = (cell_cfg_phy.nof_prb == 6) ? 1 : 2; - cell_cfg.prach_freq_offset = (cell_cfg_phy.nof_prb == 6) ? 0 : 4; - cell_cfg.prach_rar_window = 3; - cell_cfg.maxharq_msg3tx = 3; - cell_cfg.initial_dl_cqi = 6; - cell_cfg.target_ul_sinr = -1; - cell_cfg.nrb_cqi = 1; - cell_cfg.n1pucch_an = 12; - cell_cfg.delta_pucch_shift = 1; - cell_cfg.ncs_an = 0; + cell_cfg.sibs[0].len = 18; + cell_cfg.sibs[0].period_rf = 8; + cell_cfg.sibs[1].len = 41; + cell_cfg.sibs[1].period_rf = 16; + cell_cfg.si_window_ms = 40; + cell_cfg.nrb_pucch = (cell_cfg_phy.nof_prb == 6) ? 1 : 2; + cell_cfg.prach_freq_offset = (cell_cfg_phy.nof_prb == 6) ? 0 : 4; + cell_cfg.prach_rar_window = 3; + cell_cfg.maxharq_msg3tx = 3; + cell_cfg.initial_dl_cqi = 6; + cell_cfg.target_pusch_ul_sinr = -1; + cell_cfg.target_pucch_ul_sinr = -1; + cell_cfg.nrb_cqi = 1; + cell_cfg.n1pucch_an = 12; + cell_cfg.delta_pucch_shift = 1; + cell_cfg.ncs_an = 0; return cell_cfg; } diff --git a/srsenb/test/mac/sched_tpc_test.cc b/srsenb/test/mac/sched_tpc_test.cc index 014b5e863..f928fcaa0 100644 --- a/srsenb/test/mac/sched_tpc_test.cc +++ b/srsenb/test/mac/sched_tpc_test.cc @@ -26,7 +26,7 @@ int test_finite_target_snr() const uint32_t nof_prbs = 50; const int target_snr = 15; - tpc tpcfsm(nof_prbs, 15, true); + tpc tpcfsm(nof_prbs, 15, 15, true); // TEST: While no SNR info is provided, no TPC commands are sent for (uint32_t i = 0; i < 100; ++i) { @@ -73,7 +73,7 @@ int test_undefined_target_snr() { const uint32_t nof_prbs = 50; - tpc tpcfsm(nof_prbs, -1, true); + tpc tpcfsm(nof_prbs, -1, -1, true); TESTASSERT(tpcfsm.max_ul_prbs() == 50); // TEST: While the PHR is not updated, a limited number of TPC commands should be sent