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@ -22,6 +22,7 @@
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#include "srsenb/hdr/stack/rrc/rrc_ue.h"
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#include "srsenb/hdr/stack/rrc/mac_controller.h"
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#include "srsenb/hdr/stack/rrc/rrc_mobility.h"
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#include "srsenb/hdr/stack/rrc/ue_rr_cfg.h"
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#include "srslte/asn1/rrc_asn1_utils.h"
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#include "srslte/common/int_helpers.h"
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@ -254,17 +255,16 @@ void rrc::ue::send_connection_setup()
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dl_ccch_msg_s dl_ccch_msg;
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dl_ccch_msg.msg.set_c1();
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dl_ccch_msg.msg.c1().set_rrc_conn_setup();
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dl_ccch_msg.msg.c1().rrc_conn_setup().rrc_transaction_id = (uint8_t)((transaction_id++) % 4);
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rrc_conn_setup_r8_ies_s& setup = dl_ccch_msg.msg.c1().rrc_conn_setup().crit_exts.set_c1().set_rrc_conn_setup_r8();
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rr_cfg_ded_s* rr_cfg = &setup.rr_cfg_ded;
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rrc_conn_setup_s& rrc_setup = dl_ccch_msg.msg.c1().set_rrc_conn_setup();
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rrc_setup.rrc_transaction_id = (uint8_t)((transaction_id++) % 4);
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rrc_conn_setup_r8_ies_s& setup_r8 = rrc_setup.crit_exts.set_c1().set_rrc_conn_setup_r8();
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rr_cfg_ded_s& rr_cfg = setup_r8.rr_cfg_ded;
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// Fill RR config dedicated
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fill_rrc_setup_rr_config_dedicated(rr_cfg);
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phys_cfg_ded_s* phy_cfg = &rr_cfg->phys_cfg_ded;
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fill_rr_cfg_ded_setup(rr_cfg, parent->cfg, cell_ded_list);
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// Apply ConnectionSetup Configuration to MAC scheduler
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mac_ctrl->handle_con_setup(setup);
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mac_ctrl->handle_con_setup(setup_r8);
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// Add SRBs/DRBs, and configure RLC+PDCP
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apply_pdcp_srb_updates();
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@ -272,7 +272,7 @@ void rrc::ue::send_connection_setup()
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apply_rlc_rb_updates();
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// Configure PHY layer
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apply_setup_phy_config_dedicated(*phy_cfg); // It assumes SCell has not been set before
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apply_setup_phy_config_dedicated(rr_cfg.phys_cfg_ded); // It assumes SCell has not been set before
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send_dl_ccch(&dl_ccch_msg);
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}
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@ -397,22 +397,19 @@ void rrc::ue::send_connection_reest(uint8_t ncc)
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bearer_list.add_srb(1);
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dl_ccch_msg_s dl_ccch_msg;
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dl_ccch_msg.msg.set_c1();
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dl_ccch_msg.msg.c1().set_rrc_conn_reest();
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dl_ccch_msg.msg.c1().rrc_conn_reest().rrc_transaction_id = (uint8_t)((transaction_id++) % 4);
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rrc_conn_reest_r8_ies_s& reest = dl_ccch_msg.msg.c1().rrc_conn_reest().crit_exts.set_c1().set_rrc_conn_reest_r8();
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rr_cfg_ded_s* rr_cfg = &reest.rr_cfg_ded;
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auto& reest = dl_ccch_msg.msg.set_c1().set_rrc_conn_reest();
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reest.rrc_transaction_id = (uint8_t)((transaction_id++) % 4);
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rrc_conn_reest_r8_ies_s& reest_r8 = reest.crit_exts.set_c1().set_rrc_conn_reest_r8();
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rr_cfg_ded_s& rr_cfg = reest_r8.rr_cfg_ded;
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// Fill RR config dedicated
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fill_rrc_setup_rr_config_dedicated(rr_cfg);
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phys_cfg_ded_s* phy_cfg = &rr_cfg->phys_cfg_ded;
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fill_rr_cfg_ded_setup(rr_cfg, parent->cfg, cell_ded_list);
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// Set NCC
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reest.next_hop_chaining_count = ncc;
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reest_r8.next_hop_chaining_count = ncc;
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// Apply ConnectionReest Configuration to MAC scheduler
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mac_ctrl->handle_con_reest(reest);
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mac_ctrl->handle_con_reest(reest_r8);
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// Add SRBs/DRBs, and configure RLC+PDCP
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apply_pdcp_srb_updates();
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@ -420,7 +417,7 @@ void rrc::ue::send_connection_reest(uint8_t ncc)
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apply_rlc_rb_updates();
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// Configure PHY layer
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apply_setup_phy_config_dedicated(*phy_cfg); // It assumes SCell has not been set before
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apply_setup_phy_config_dedicated(rr_cfg.phys_cfg_ded); // It assumes SCell has not been set before
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send_dl_ccch(&dl_ccch_msg);
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}
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@ -1208,82 +1205,6 @@ void rrc::ue::handle_ho_preparation_complete(bool is_success, srslte::unique_byt
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/********************** HELPERS ***************************/
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// Helper method to fill in rr_config_dedicated
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void rrc::ue::fill_rrc_setup_rr_config_dedicated(asn1::rrc::rr_cfg_ded_s* rr_cfg)
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{
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// Fill drbsToAddModList/srbsToAddModList/drbsToReleaseList
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bearer_list.fill_rr_cfg_ded(*rr_cfg);
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// Fill mac-MainConfig
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rr_cfg->mac_main_cfg_present = true;
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mac_main_cfg_s* mac_cfg = &rr_cfg->mac_main_cfg.set_explicit_value();
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mac_cfg->ul_sch_cfg_present = true;
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mac_cfg->ul_sch_cfg = parent->cfg.mac_cnfg.ul_sch_cfg;
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mac_cfg->phr_cfg_present = true;
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mac_cfg->phr_cfg = parent->cfg.mac_cnfg.phr_cfg;
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mac_cfg->time_align_timer_ded = parent->cfg.mac_cnfg.time_align_timer_ded;
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// Fill physicalConfigDedicated
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rr_cfg->phys_cfg_ded_present = true;
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phys_cfg_ded_s* phy_cfg = &rr_cfg->phys_cfg_ded;
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phy_cfg->pusch_cfg_ded_present = true;
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phy_cfg->pusch_cfg_ded = parent->cfg.pusch_cfg;
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phy_cfg->sched_request_cfg_present = true;
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phy_cfg->sched_request_cfg.set_setup();
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phy_cfg->sched_request_cfg.setup().dsr_trans_max = parent->cfg.sr_cfg.dsr_max;
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// set default antenna config
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phy_cfg->ant_info_present = true;
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phy_cfg->ant_info.set_explicit_value();
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if (parent->cfg.cell.nof_ports == 1) {
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phy_cfg->ant_info.explicit_value().tx_mode.value = ant_info_ded_s::tx_mode_e_::tm1;
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} else {
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phy_cfg->ant_info.explicit_value().tx_mode.value = ant_info_ded_s::tx_mode_e_::tm2;
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}
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phy_cfg->ant_info.explicit_value().ue_tx_ant_sel.set(setup_e::release);
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phy_cfg->sched_request_cfg.setup().sr_cfg_idx = (uint8_t)cell_ded_list.get_sr_res()->sr_I;
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phy_cfg->sched_request_cfg.setup().sr_pucch_res_idx = (uint16_t)cell_ded_list.get_sr_res()->sr_N_pucch;
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// Power control
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phy_cfg->ul_pwr_ctrl_ded_present = true;
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phy_cfg->ul_pwr_ctrl_ded.p0_ue_pusch = 0;
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phy_cfg->ul_pwr_ctrl_ded.delta_mcs_enabled = ul_pwr_ctrl_ded_s::delta_mcs_enabled_e_::en0;
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phy_cfg->ul_pwr_ctrl_ded.accumulation_enabled = true;
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phy_cfg->ul_pwr_ctrl_ded.p0_ue_pucch = 0;
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phy_cfg->ul_pwr_ctrl_ded.psrs_offset = 3;
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// PDSCH
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phy_cfg->pdsch_cfg_ded_present = true;
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phy_cfg->pdsch_cfg_ded.p_a = parent->cfg.pdsch_cfg;
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// PUCCH
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phy_cfg->pucch_cfg_ded_present = true;
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phy_cfg->pucch_cfg_ded.ack_nack_repeat.set(pucch_cfg_ded_s::ack_nack_repeat_c_::types::release);
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phy_cfg->cqi_report_cfg_present = true;
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if (parent->cfg.cqi_cfg.mode == RRC_CFG_CQI_MODE_APERIODIC) {
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phy_cfg->cqi_report_cfg.cqi_report_mode_aperiodic_present = true;
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phy_cfg->cqi_report_cfg.cqi_report_mode_aperiodic = cqi_report_mode_aperiodic_e::rm30;
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} else {
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phy_cfg->cqi_report_cfg.cqi_report_periodic_present = true;
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phy_cfg->cqi_report_cfg.cqi_report_periodic.set_setup();
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phy_cfg->cqi_report_cfg.cqi_report_periodic.setup().cqi_format_ind_periodic.set(
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cqi_report_periodic_c::setup_s_::cqi_format_ind_periodic_c_::types::wideband_cqi);
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phy_cfg->cqi_report_cfg.cqi_report_periodic.setup().simul_ack_nack_and_cqi = parent->cfg.cqi_cfg.simultaneousAckCQI;
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if (get_cqi(&phy_cfg->cqi_report_cfg.cqi_report_periodic.setup().cqi_pmi_cfg_idx,
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&phy_cfg->cqi_report_cfg.cqi_report_periodic.setup().cqi_pucch_res_idx,
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UE_PCELL_CC_IDX)) {
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parent->rrc_log->error("Allocating CQI resources for rnti=%d\n", rnti);
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return;
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}
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}
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phy_cfg->cqi_report_cfg.nom_pdsch_rs_epre_offset = 0;
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rr_cfg->rlf_timers_and_consts_r9.set_present(false);
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rr_cfg->sps_cfg_present = false;
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}
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void rrc::ue::send_dl_ccch(dl_ccch_msg_s* dl_ccch_msg)
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{
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// Allocate a new PDU buffer, pack the message and send to PDCP
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