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sched,nr: pass asn1 TDD configuration to scheduler as defined in ORAN

Browse Source
master
Francisco 3 years ago committed by Francisco Paisana
parent f1831d9027
commit 7f200ac7f7
31 changed files with 289 additions and 170 deletions
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3
lib/include/srsran/asn1/rrc_nr_utils.h
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@ -84,6 +84,9 @@ bool make_phy_rach_cfg(const asn1::rrc_nr::rach_cfg_common_s& asn1_type, srsran_
bool make_phy_tdd_cfg(const asn1::rrc_nr::tdd_ul_dl_cfg_common_s& tdd_ul_dl_cfg_common,
srsran_duplex_config_nr_t* srsran_duplex_config_nr);
bool make_phy_tdd_cfg(const srsran_duplex_config_nr_t& srsran_duplex_config_nr,
srsran_subcarrier_spacing_t scs,
asn1::rrc_nr::tdd_ul_dl_cfg_common_s* tdd_ul_dl_cfg_common);
bool make_phy_harq_ack_cfg(const asn1::rrc_nr::phys_cell_group_cfg_s& phys_cell_group_cfg,
srsran_harq_ack_cfg_hl_t* srsran_ue_dl_nr_harq_ack_cfg);
bool make_phy_coreset_cfg(const asn1::rrc_nr::ctrl_res_set_s& ctrl_res_set, srsran_coreset_t* srsran_coreset);

2
lib/include/srsran/interfaces/gnb_mac_interfaces.h
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@ -22,7 +22,7 @@ class mac_interface_rrc_nr
{
public:
// Provides cell configuration including SIB periodicity, etc.
virtual int cell_cfg(const std::vector<srsenb::sched_nr_interface::cell_cfg_t>& nr_cells) = 0;
virtual int cell_cfg(const std::vector<sched_nr_cell_cfg_t>& nr_cells) = 0;
/// Allocates a new user/RNTI at MAC. Returns RNTI on success or SRSRAN_INVALID_RNTI otherwise.
virtual uint16_t reserve_rnti(uint32_t enb_cc_idx, const sched_nr_interface::ue_cfg_t& uecfg) = 0;

63
lib/src/asn1/rrc_nr_utils.cc
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@ -375,6 +375,69 @@ bool make_phy_tdd_cfg(const tdd_ul_dl_cfg_common_s& tdd_ul_dl_cfg_common,
return true;
}
bool make_phy_tdd_cfg(const srsran_duplex_config_nr_t& srsran_duplex_config_nr,
srsran_subcarrier_spacing_t scs,
asn1::rrc_nr::tdd_ul_dl_cfg_common_s* tdd_ul_dl_cfg_common)
{
if (srsran_duplex_config_nr.mode == SRSRAN_DUPLEX_MODE_FDD) {
return true;
}
tdd_ul_dl_cfg_common->ref_subcarrier_spacing.value = (asn1::rrc_nr::subcarrier_spacing_e::options)scs;
switch (srsran_duplex_config_nr.tdd.pattern1.period_ms) {
case 1:
tdd_ul_dl_cfg_common->pattern1.dl_ul_tx_periodicity = tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms1;
break;
case 2:
tdd_ul_dl_cfg_common->pattern1.dl_ul_tx_periodicity = tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms2;
break;
case 5:
tdd_ul_dl_cfg_common->pattern1.dl_ul_tx_periodicity = tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms5;
break;
case 10:
tdd_ul_dl_cfg_common->pattern1.dl_ul_tx_periodicity = tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms10;
break;
default:
asn1::log_warning("Invalid option for dl_ul_tx_periodicity_opts %d",
srsran_duplex_config_nr.tdd.pattern1.period_ms);
return false;
}
tdd_ul_dl_cfg_common->pattern1.nrof_dl_slots = srsran_duplex_config_nr.tdd.pattern1.nof_dl_slots;
tdd_ul_dl_cfg_common->pattern1.nrof_dl_symbols = srsran_duplex_config_nr.tdd.pattern1.nof_dl_symbols;
tdd_ul_dl_cfg_common->pattern1.nrof_ul_slots = srsran_duplex_config_nr.tdd.pattern1.nof_ul_slots;
tdd_ul_dl_cfg_common->pattern1.nrof_ul_symbols = srsran_duplex_config_nr.tdd.pattern1.nof_ul_symbols;
if (srsran_duplex_config_nr.tdd.pattern2.period_ms == 0) {
return true;
}
tdd_ul_dl_cfg_common->pattern2_present = true;
switch (srsran_duplex_config_nr.tdd.pattern2.period_ms) {
case 1:
tdd_ul_dl_cfg_common->pattern2.dl_ul_tx_periodicity.value = tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms1;
break;
case 2:
tdd_ul_dl_cfg_common->pattern2.dl_ul_tx_periodicity.value = tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms2;
break;
case 5:
tdd_ul_dl_cfg_common->pattern2.dl_ul_tx_periodicity.value = tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms5;
break;
case 10:
tdd_ul_dl_cfg_common->pattern2.dl_ul_tx_periodicity.value = tdd_ul_dl_pattern_s::dl_ul_tx_periodicity_opts::ms10;
break;
default:
asn1::log_warning("Invalid option for pattern2 dl_ul_tx_periodicity_opts %d",
srsran_duplex_config_nr.tdd.pattern2.period_ms);
return false;
}
tdd_ul_dl_cfg_common->pattern2.nrof_dl_slots = srsran_duplex_config_nr.tdd.pattern2.nof_dl_slots;
tdd_ul_dl_cfg_common->pattern2.nrof_dl_symbols = srsran_duplex_config_nr.tdd.pattern2.nof_dl_symbols;
tdd_ul_dl_cfg_common->pattern2.nrof_ul_slots = srsran_duplex_config_nr.tdd.pattern2.nof_ul_slots;
tdd_ul_dl_cfg_common->pattern2.nrof_ul_symbols = srsran_duplex_config_nr.tdd.pattern2.nof_ul_symbols;
return true;
}
bool make_phy_harq_ack_cfg(const phys_cell_group_cfg_s& phys_cell_group_cfg,
srsran_harq_ack_cfg_hl_t* in_srsran_ue_dl_nr_harq_ack_cfg)
{

8
srsgnb/hdr/stack/common/test/dummy_nr_classes.h
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@ -62,7 +62,7 @@ public:
class mac_nr_dummy : public mac_interface_rrc_nr
{
public:
int cell_cfg(const std::vector<srsenb::sched_nr_interface::cell_cfg_t>& nr_cells_) override
int cell_cfg(const std::vector<sched_nr_cell_cfg_t>& nr_cells_) override
{
nr_cells = nr_cells_;
return SRSRAN_SUCCESS;
@ -78,9 +78,9 @@ public:
int remove_ue(uint16_t rnti) override { return SRSRAN_SUCCESS; }
std::vector<srsenb::sched_nr_interface::cell_cfg_t> nr_cells;
uint16_t last_ue_cfg_rnti = SRSRAN_INVALID_RNTI;
sched_nr_interface::ue_cfg_t last_ue_cfg{};
std::vector<sched_nr_cell_cfg_t> nr_cells;
uint16_t last_ue_cfg_rnti = SRSRAN_INVALID_RNTI;
sched_nr_interface::ue_cfg_t last_ue_cfg{};
};
class phy_nr_dummy : public phy_interface_stack_nr

8
srsgnb/hdr/stack/mac/mac_nr.h
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@ -57,7 +57,7 @@ public:
void get_metrics(srsenb::mac_metrics_t& metrics);
// MAC interface for RRC
int cell_cfg(const std::vector<srsenb::sched_nr_interface::cell_cfg_t>& nr_cells) override;
int cell_cfg(const std::vector<srsenb::sched_nr_cell_cfg_t>& nr_cells) override;
uint16_t reserve_rnti(uint32_t enb_cc_idx, const sched_nr_interface::ue_cfg_t& uecfg) override;
int read_pdu_bcch_bch(uint8_t* payload);
int ue_cfg(uint16_t rnti, const sched_nr_interface::ue_cfg_t& ue_cfg) override;
@ -118,9 +118,9 @@ private:
std::atomic<bool> started = {false};
const static uint32_t NUMEROLOGY_IDX = 0; /// only 15kHz supported at this stage
std::unique_ptr<srsenb::sched_nr> sched;
std::vector<sched_nr_interface::cell_cfg_t> cell_config;
const static uint32_t NUMEROLOGY_IDX = 0; /// only 15kHz supported at this stage
std::unique_ptr<srsenb::sched_nr> sched;
std::vector<sched_nr_cell_cfg_t> cell_config;
// Map of active UEs
pthread_rwlock_t rwmutex = {};

2
srsgnb/hdr/stack/mac/sched_nr.h
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@ -38,7 +38,7 @@ public:
~sched_nr() override;
void stop();
int config(const sched_args_t& sched_cfg, srsran::const_span<cell_cfg_t> cell_list) override;
int config(const sched_args_t& sched_cfg, srsran::const_span<sched_nr_cell_cfg_t> cell_list) override;
void ue_cfg(uint16_t rnti, const ue_cfg_t& cfg) override;
void ue_rem(uint16_t rnti) override;

48
srsgnb/hdr/stack/mac/sched_nr_cfg.h
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@ -40,8 +40,7 @@ using nzp_csi_rs_list = srsran::bounded_vector<srsran_csi_rs_nzp_resource_t,
using ssb_t = mac_interface_phy_nr::ssb_t;
using ssb_list = srsran::bounded_vector<ssb_t, mac_interface_phy_nr::MAX_SSB>;
using sched_args_t = sched_nr_interface::sched_args_t;
using cell_cfg_t = sched_nr_interface::cell_cfg_t;
using bwp_cfg_t = sched_nr_interface::bwp_cfg_t;
using bwp_cfg_t = sched_nr_bwp_cfg_t;
using ue_cc_cfg_t = sched_nr_interface::ue_cc_cfg_t;
using pdcch_cce_pos_list = srsran::bounded_vector<uint32_t, SRSRAN_SEARCH_SPACE_MAX_NOF_CANDIDATES_NR>;
using bwp_cce_pos_list = std::array<std::array<pdcch_cce_pos_list, MAX_NOF_AGGR_LEVELS>, SRSRAN_NOF_SF_X_FRAME>;
@ -57,20 +56,23 @@ void get_dci_locs(const srsran_coreset_t& coreset,
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
struct cell_params_t;
/// Structure that extends the sched_nr_interface::bwp_cfg_t passed by upper layers with other
/// derived BWP-specific params
struct bwp_params_t {
const uint32_t bwp_id;
const uint32_t cc;
const bwp_cfg_t& cfg;
const cell_cfg_t& cell_cfg;
const sched_args_t& sched_cfg;
const uint32_t bwp_id;
const uint32_t cc;
const bwp_cfg_t cfg;
const cell_params_t& cell_cfg;
const sched_args_t& sched_cfg;
sched_nr_bwp_cfg_t bwp_cfg;
// derived params
srslog::basic_logger& logger;
uint32_t P;
uint32_t N_rbg;
uint32_t nof_prb() const { return cell_cfg.carrier.nof_prb; }
uint32_t nof_prb;
/// Table specifying if a slot has DL or UL enabled
struct slot_cfg {
@ -91,7 +93,7 @@ struct bwp_params_t {
srsran::optional_vector<bwp_cce_pos_list> common_cce_list;
bwp_params_t(const cell_cfg_t& cell, const sched_args_t& sched_cfg_, uint32_t cc, uint32_t bwp_id);
bwp_params_t(const cell_params_t& cell, uint32_t bwp_id, const sched_nr_bwp_cfg_t& bwp_cfg);
prb_interval coreset_prb_range(uint32_t cs_id) const { return coresets[cs_id].prb_limits; }
prb_interval dci_fmt_1_0_prb_lims(uint32_t cs_id) const { return coresets[cs_id].dci_1_0_prb_limits; }
@ -114,14 +116,28 @@ private:
/// Structure packing a single cell config params, and sched args
struct cell_params_t {
const uint32_t cc;
const cell_cfg_t cfg;
const sched_args_t& sched_args;
std::vector<bwp_params_t> bwps;
cell_params_t(uint32_t cc_, const cell_cfg_t& cell, const sched_args_t& sched_cfg_);
const uint32_t cc;
srsran_carrier_nr_t carrier = {};
srsran::phy_cfg_nr_t::ssb_cfg_t ssb = {};
std::vector<bwp_params_t> bwps; // idx0 for BWP-common
srsran_mib_nr_t mib;
std::vector<sched_nr_cell_cfg_sib_t> sibs;
asn1::copy_ptr<asn1::rrc_nr::dl_cfg_common_sib_s> dl_cfg_common;
asn1::copy_ptr<asn1::rrc_nr::ul_cfg_common_sib_s> ul_cfg_common;
srsran_duplex_config_nr_t duplex = {};
const sched_args_t& sched_args;
const srsran::phy_cfg_nr_t default_ue_phy_cfg;
cell_params_t(uint32_t cc_, const sched_nr_cell_cfg_t& cell, const sched_args_t& sched_args_);
uint32_t nof_prb() const { return carrier.nof_prb; }
uint32_t nof_prb() const { return cfg.carrier.nof_prb; }
/// Table specifying if a slot has DL or UL enabled
struct slot_cfg {
bool is_dl;
bool is_ul;
};
srsran::bounded_vector<slot_cfg, SRSRAN_NOF_SF_X_FRAME> slots;
};
/// Structure packing both the sched args and all gNB NR cell configurations

69
srsgnb/hdr/stack/mac/sched_nr_interface.h
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@ -56,43 +56,44 @@ struct sched_nr_ue_cfg_t {
std::vector<uint32_t> lc_ch_to_rem;
};
struct sched_nr_bwp_cfg_t {
uint32_t start_rb = 0;
uint32_t rb_width = 100;
srsran_pdcch_cfg_nr_t pdcch = {};
srsran_sch_hl_cfg_nr_t pdsch = {};
srsran_sch_hl_cfg_nr_t pusch = {};
srsran_pucch_nr_hl_cfg_t pucch = {};
srsran_prach_cfg_t prach = {};
srsran_harq_ack_cfg_hl_t harq_ack = {};
uint32_t rar_window_size = 10; // See TS 38.331, ra-ResponseWindow: {1, 2, 4, 8, 10, 20, 40, 80}
uint32_t numerology_idx = 0;
};
struct sched_nr_cell_cfg_sib_t {
uint32_t len;
uint32_t period_rf;
uint32_t si_window_slots;
};
struct sched_nr_cell_cfg_t {
static const size_t MAX_SIBS = 2;
srsran_carrier_nr_t carrier = {};
srsran::phy_cfg_nr_t::ssb_cfg_t ssb = {};
std::vector<sched_nr_bwp_cfg_t> bwps{1}; // idx0 for BWP-common
srsran_mib_nr_t mib;
std::vector<sched_nr_cell_cfg_sib_t> sibs;
asn1::copy_ptr<asn1::rrc_nr::dl_cfg_common_sib_s> dl_cfg_common;
asn1::copy_ptr<asn1::rrc_nr::ul_cfg_common_sib_s> ul_cfg_common;
asn1::copy_ptr<asn1::rrc_nr::tdd_ul_dl_cfg_common_s> tdd_ul_dl_cfg_common;
};
class sched_nr_interface
{
public:
static const size_t MAX_GRANTS = mac_interface_phy_nr::MAX_GRANTS;
static const size_t MAX_SIBS = 2;
static const size_t MAX_SUBPDUS = 8;
///// Configuration /////
struct bwp_cfg_t {
uint32_t start_rb = 0;
uint32_t rb_width = 100;
srsran_pdcch_cfg_nr_t pdcch = {};
srsran_sch_hl_cfg_nr_t pdsch = {};
srsran_sch_hl_cfg_nr_t pusch = {};
srsran_pucch_nr_hl_cfg_t pucch = {};
srsran_prach_cfg_t prach = {};
srsran_harq_ack_cfg_hl_t harq_ack = {};
uint32_t rar_window_size = 10; // See TS 38.331, ra-ResponseWindow: {1, 2, 4, 8, 10, 20, 40, 80}
uint32_t numerology_idx = 0;
};
struct cell_cfg_sib_t {
uint32_t len;
uint32_t period_rf;
uint32_t si_window_slots;
};
struct cell_cfg_t {
srsran_carrier_nr_t carrier = {};
srsran_duplex_config_nr_t duplex = {};
srsran::phy_cfg_nr_t::ssb_cfg_t ssb = {};
srsran::bounded_vector<bwp_cfg_t, SCHED_NR_MAX_BWP_PER_CELL> bwps{1}; // idx0 for BWP-common
srsran_mib_nr_t mib;
srsran::bounded_vector<cell_cfg_sib_t, MAX_SIBS> sibs;
};
struct sched_args_t {
bool pdsch_enabled = true;
bool pusch_enabled = true;
@ -145,10 +146,10 @@ public:
sched_sib_list_t sib_idxs;
};
virtual ~sched_nr_interface() = default;
virtual int config(const sched_args_t& sched_cfg, srsran::const_span<sched_nr_interface::cell_cfg_t> ue_cfg) = 0;
virtual void ue_cfg(uint16_t rnti, const ue_cfg_t& ue_cfg) = 0;
virtual void ue_rem(uint16_t rnti) = 0;
virtual ~sched_nr_interface() = default;
virtual int config(const sched_args_t& sched_cfg, srsran::const_span<sched_nr_cell_cfg_t> ue_cfg) = 0;
virtual void ue_cfg(uint16_t rnti, const ue_cfg_t& ue_cfg) = 0;
virtual void ue_rem(uint16_t rnti) = 0;
virtual void slot_indication(slot_point slot_tx) = 0;
virtual dl_res_t* get_dl_sched(slot_point slot_rx, uint32_t cc) = 0;

2
srsgnb/hdr/stack/mac/sched_nr_interface_utils.h
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@ -61,7 +61,7 @@ inline bool operator==(srsran_dci_location_t lhs, srsran_dci_location_t rhs)
//////////////////////////////////// UE configuration Helpers ////////////////////////////////////////////
srsran::phy_cfg_nr_t get_common_ue_phy_cfg(const sched_nr_interface::cell_cfg_t& cfg);
srsran::phy_cfg_nr_t get_common_ue_phy_cfg(const sched_nr_cell_cfg_t& cfg);
} // namespace srsenb

2
srsgnb/src/stack/mac/mac_nr.cc
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@ -277,7 +277,7 @@ void mac_nr::get_metrics_nolock(srsenb::mac_metrics_t& metrics)
}
}
int mac_nr::cell_cfg(const std::vector<srsenb::sched_nr_interface::cell_cfg_t>& nr_cells)
int mac_nr::cell_cfg(const std::vector<srsenb::sched_nr_cell_cfg_t>& nr_cells)
{
cell_config = nr_cells;
sched->config(args.sched_cfg, nr_cells);

2
srsgnb/src/stack/mac/sched_nr.cc
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@ -290,7 +290,7 @@ void sched_nr::stop()
metrics_handler->stop();
}
int sched_nr::config(const sched_args_t& sched_cfg, srsran::const_span<cell_cfg_t> cell_list)
int sched_nr::config(const sched_args_t& sched_cfg, srsran::const_span<sched_nr_cell_cfg_t> cell_list)
{
cfg = sched_params_t{sched_cfg};
logger = &srslog::fetch_basic_logger(sched_cfg.logger_name);

46
srsgnb/src/stack/mac/sched_nr_cfg.cc
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@ -13,6 +13,7 @@
#include "srsgnb/hdr/stack/mac/sched_nr_cfg.h"
#include "srsgnb/hdr/stack/mac/sched_nr_helpers.h"
#include "srsran/adt/optional_array.h"
#include "srsran/asn1/rrc_nr_utils.h"
extern "C" {
#include "srsran/phy/phch/ra_ul_nr.h"
}
@ -38,16 +39,15 @@ void get_dci_locs(const srsran_coreset_t& coreset,
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
bwp_params_t::bwp_params_t(const cell_cfg_t& cell, const sched_args_t& sched_cfg_, uint32_t cc_, uint32_t bwp_id_) :
bwp_params_t::bwp_params_t(const cell_params_t& cell, uint32_t bwp_id_, const sched_nr_bwp_cfg_t& bwp_cfg) :
cell_cfg(cell),
sched_cfg(sched_cfg_),
cc(cc_),
sched_cfg(cell.sched_args),
cc(cell.cc),
bwp_id(bwp_id_),
cfg(cell.bwps[bwp_id_]),
logger(srslog::fetch_basic_logger(sched_cfg_.logger_name)),
cached_empty_prb_mask(cell.bwps[bwp_id_].rb_width,
cell.bwps[bwp_id_].start_rb,
cell.bwps[bwp_id_].pdsch.rbg_size_cfg_1)
cfg(bwp_cfg),
nof_prb(cell_cfg.carrier.nof_prb),
logger(srslog::fetch_basic_logger(sched_cfg.logger_name)),
cached_empty_prb_mask(bwp_cfg.rb_width, bwp_cfg.start_rb, bwp_cfg.pdsch.rbg_size_cfg_1)
{
srsran_assert(cfg.pdcch.ra_search_space_present, "BWPs without RA search space not supported");
const uint32_t ra_coreset_id = cfg.pdcch.ra_search_space.coreset_id;
@ -100,8 +100,8 @@ bwp_params_t::bwp_params_t(const cell_cfg_t& cell, const sched_args_t& sched_cfg
for (uint32_t sl = 0; sl < SRSRAN_NOF_SF_X_FRAME; ++sl) {
for (uint32_t agg_idx = 0; agg_idx < MAX_NOF_AGGR_LEVELS; ++agg_idx) {
rar_cce_list[sl][agg_idx].resize(SRSRAN_SEARCH_SPACE_MAX_NOF_CANDIDATES_NR);
int n = srsran_pdcch_nr_locations_coreset(&cell_cfg.bwps[0].pdcch.coreset[ra_coreset_id],
&cell_cfg.bwps[0].pdcch.ra_search_space,
int n = srsran_pdcch_nr_locations_coreset(&cell_cfg.bwps[0].cfg.pdcch.coreset[ra_coreset_id],
&cell_cfg.bwps[0].cfg.pdcch.ra_search_space,
0,
agg_idx,
sl,
@ -112,11 +112,11 @@ bwp_params_t::bwp_params_t(const cell_cfg_t& cell, const sched_args_t& sched_cfg
}
for (uint32_t ss_id = 0; ss_id < SRSRAN_UE_DL_NR_MAX_NOF_SEARCH_SPACE; ++ss_id) {
if (not cell_cfg.bwps[0].pdcch.search_space_present[ss_id]) {
if (not cell_cfg.bwps[0].cfg.pdcch.search_space_present[ss_id]) {
continue;
}
auto& ss = cell_cfg.bwps[0].pdcch.search_space[ss_id];
auto& coreset = cell_cfg.bwps[0].pdcch.coreset[ss.coreset_id];
auto& ss = cell_cfg.bwps[0].cfg.pdcch.search_space[ss_id];
auto& coreset = cell_cfg.bwps[0].cfg.pdcch.coreset[ss.coreset_id];
common_cce_list.emplace(ss_id);
bwp_cce_pos_list& ss_cce_list = common_cce_list[ss_id];
for (uint32_t sl = 0; sl < SRSRAN_NOF_SF_X_FRAME; ++sl) {
@ -131,12 +131,24 @@ bwp_params_t::bwp_params_t(const cell_cfg_t& cell, const sched_args_t& sched_cfg
}
}
cell_params_t::cell_params_t(uint32_t cc_, const cell_cfg_t& cell, const sched_args_t& sched_cfg_) :
cc(cc_), cfg(cell), sched_args(sched_cfg_)
cell_params_t::cell_params_t(uint32_t cc_, const sched_nr_cell_cfg_t& cell, const sched_args_t& sched_args_) :
cc(cc_),
sched_args(sched_args_),
default_ue_phy_cfg(get_common_ue_phy_cfg(cell)),
ssb(cell.ssb),
carrier(cell.carrier),
mib(cell.mib),
sibs(cell.sibs)
{
// Conversion 36.331 ASN1 TDD-UL-DL-ConfigCommon to srsran_duplex_config_nr_t
duplex.mode = SRSRAN_DUPLEX_MODE_FDD;
if (cell.tdd_ul_dl_cfg_common.is_present()) {
srsran_assert(srsran::make_phy_tdd_cfg(*cell.tdd_ul_dl_cfg_common, &duplex), "Failed to generate Cell TDD config");
}
bwps.reserve(cell.bwps.size());
for (uint32_t i = 0; i < cfg.bwps.size(); ++i) {
bwps.emplace_back(cfg, sched_cfg_, cc, i);
for (uint32_t i = 0; i < cell.bwps.size(); ++i) {
bwps.emplace_back(*this, i, cell.bwps[i]);
}
srsran_assert(not bwps.empty(), "No BWPs were configured");
}

11
srsgnb/src/stack/mac/sched_nr_interface_utils.cc
Unescape Escape View File

@ -11,6 +11,7 @@
*/
#include "srsgnb/hdr/stack/mac/sched_nr_interface_utils.h"
#include "srsran/asn1/rrc_nr_utils.h"
namespace srsenb {
@ -21,14 +22,13 @@ uint32_t coreset_nof_cces(const srsran_coreset_t& coreset)
return nof_freq_res * coreset.duration;
}
srsran::phy_cfg_nr_t get_common_ue_phy_cfg(const sched_nr_interface::cell_cfg_t& cfg)
srsran::phy_cfg_nr_t get_common_ue_phy_cfg(const sched_nr_cell_cfg_t& cfg)
{
srsran::phy_cfg_nr_t ue_phy_cfg;
ue_phy_cfg.csi = {}; // disable CSI until RA is complete
ue_phy_cfg.carrier = cfg.carrier;
ue_phy_cfg.duplex = cfg.duplex;
ue_phy_cfg.ssb = cfg.ssb;
ue_phy_cfg.pdcch = cfg.bwps[0].pdcch;
ue_phy_cfg.pdsch = cfg.bwps[0].pdsch;
@ -46,6 +46,13 @@ srsran::phy_cfg_nr_t get_common_ue_phy_cfg(const sched_nr_interface::cell_cfg_t&
}
}
// TDD UL-DL config
ue_phy_cfg.duplex.mode = SRSRAN_DUPLEX_MODE_FDD;
if (cfg.tdd_ul_dl_cfg_common.is_present()) {
srsran_sanity_check(srsran::make_phy_tdd_cfg(*cfg.tdd_ul_dl_cfg_common, &ue_phy_cfg.duplex),
"Failed to convert Cell TDDConfig to UEPHYConfig");
}
return ue_phy_cfg;
}

7
srsgnb/src/stack/mac/sched_nr_pdcch.cc
Unescape Escape View File

@ -68,10 +68,11 @@ coreset_region::coreset_region(const bwp_params_t& bwp_cfg_, uint32_t coreset_id
nof_freq_res = std::count(res_active, res_active + SRSRAN_CORESET_FREQ_DOMAIN_RES_SIZE, true);
srsran_assert(get_td_symbols() <= SRSRAN_CORESET_DURATION_MAX,
"Possible number of time-domain OFDM symbols in CORESET must be within {1,2,3}");
srsran_assert(nof_freq_res <= bwp_cfg_.cell_cfg.carrier.nof_prb,
"The number of frequency resources=%d of CORESET#%d exceeds BWP bandwidth",
srsran_assert(nof_freq_res <= bwp_cfg_.cell_cfg.nof_prb(),
"The number of frequency resources=%d of CORESET#%d exceeds BWP bandwidth=%d",
nof_freq_res,
coreset_id);
coreset_id,
bwp_cfg_.cell_cfg.nof_prb());
}
void coreset_region::reset()

4
srsgnb/src/stack/mac/sched_nr_sch.cc
Unescape Escape View File

@ -218,7 +218,7 @@ pdsch_t& pdsch_allocator::alloc_pdsch_unchecked(uint32_t cores
if (grant.is_alloc_type0()) {
out_dci.freq_domain_assigment = grant.rbgs().to_uint64();
} else {
uint32_t rb_start = grant.prbs().start(), nof_prb = bwp_cfg.nof_prb();
uint32_t rb_start = grant.prbs().start(), nof_prb = bwp_cfg.nof_prb;
if (SRSRAN_SEARCH_SPACE_IS_COMMON(ss_type)) {
prb_interval lims = bwp_cfg.coreset_prb_range(coreset_id);
if (dci_fmt == srsran_dci_format_nr_1_0) {
@ -345,7 +345,7 @@ pusch_t& pusch_allocator::alloc_pusch_unchecked(const prb_grant& grant, srsran_d
if (grant.is_alloc_type0()) {
out_dci.freq_domain_assigment = grant.rbgs().to_uint64();
} else {
uint32_t nof_prb = bwp_cfg.nof_prb();
uint32_t nof_prb = bwp_cfg.nof_prb;
out_dci.freq_domain_assigment = srsran_ra_nr_type1_riv(nof_prb, grant.prbs().start(), grant.prbs().length());
}

2
srsgnb/src/stack/mac/sched_nr_signalling.cc
Unescape Escape View File

@ -112,7 +112,7 @@ si_sched::si_sched(const bwp_params_t& bwp_cfg_) :
si.len_bytes = bwp_cfg->cell_cfg.sibs[i].len;
si.period_frames = bwp_cfg->cell_cfg.sibs[i].period_rf;
si.win_len_slots = bwp_cfg->cell_cfg.sibs[i].si_window_slots;
si.si_softbuffer = harq_softbuffer_pool::get_instance().get_tx(bwp_cfg->nof_prb());
si.si_softbuffer = harq_softbuffer_pool::get_instance().get_tx(bwp_cfg->nof_prb);
}
}

2
srsgnb/src/stack/mac/sched_nr_ue.cc
Unescape Escape View File

@ -62,8 +62,6 @@ slot_ue::slot_ue(ue_carrier& ue_, slot_point slot_tx_) : ue(&ue_), pdcch_slot(sl
uint32_t k2 = ue->bwp_cfg.active_bwp().pusch_ra_list[0].K;
pusch_slot = pdcch_slot + k2;
const srsran_duplex_config_nr_t& tdd_cfg = ue->cell_params.cfg.duplex;
dl_active = ue->cell_params.bwps[0].slots[pdsch_slot.slot_idx()].is_dl;
if (dl_active) {
dl_bytes = ue->common_ctxt.pending_dl_bytes;

2
srsgnb/src/stack/mac/sched_nr_worker.cc
Unescape Escape View File

@ -21,7 +21,7 @@ namespace sched_nr_impl {
cc_worker::cc_worker(const cell_params_t& params) :
cfg(params), logger(srslog::fetch_basic_logger(params.sched_args.logger_name))
{
for (uint32_t bwp_id = 0; bwp_id < cfg.cfg.bwps.size(); ++bwp_id) {
for (uint32_t bwp_id = 0; bwp_id < cfg.bwps.size(); ++bwp_id) {
bwps.emplace_back(cfg.bwps[bwp_id]);
}

23
srsgnb/src/stack/mac/test/sched_nr_cfg_generators.h
Unescape Escape View File

@ -14,6 +14,7 @@
#define SRSRAN_SCHED_NR_CFG_GENERATORS_H
#include "srsgnb/hdr/stack/mac/sched_nr_interface_utils.h"
#include "srsran/asn1/rrc_nr_utils.h"
#include "srsran/common/phy_cfg_nr_default.h"
namespace srsenb {
@ -43,13 +44,12 @@ inline srsran_search_space_t get_default_search_space0()
return ss;
}
inline sched_nr_interface::cell_cfg_t get_default_cell_cfg(
const srsran::phy_cfg_nr_t& phy_cfg = srsran::phy_cfg_nr_default_t{srsran::phy_cfg_nr_default_t::reference_cfg_t{}})
inline sched_nr_cell_cfg_t get_default_cell_cfg(const srsran::phy_cfg_nr_t& phy_cfg = srsran::phy_cfg_nr_default_t{
srsran::phy_cfg_nr_default_t::reference_cfg_t{}})
{
sched_nr_interface::cell_cfg_t cell_cfg{};
sched_nr_cell_cfg_t cell_cfg{};
cell_cfg.carrier = phy_cfg.carrier;
cell_cfg.duplex = phy_cfg.duplex;
cell_cfg.ssb = phy_cfg.ssb;
cell_cfg.mib.coreset0_idx = 6;
cell_cfg.mib.scs_common = srsran_subcarrier_spacing_15kHz;
@ -63,14 +63,21 @@ inline sched_nr_interface::cell_cfg_t get_default_cell_cfg(
cell_cfg.bwps[0].harq_ack = phy_cfg.harq_ack;
cell_cfg.bwps[0].rb_width = phy_cfg.carrier.nof_prb;
if (phy_cfg.duplex.mode == SRSRAN_DUPLEX_MODE_TDD) {
cell_cfg.tdd_ul_dl_cfg_common.reset(new asn1::rrc_nr::tdd_ul_dl_cfg_common_s{});
srsran_assert(
srsran::make_phy_tdd_cfg(phy_cfg.duplex, srsran_subcarrier_spacing_15kHz, cell_cfg.tdd_ul_dl_cfg_common.get()),
"Failed to generate TDD config");
}
return cell_cfg;
}
inline std::vector<sched_nr_interface::cell_cfg_t> get_default_cells_cfg(
inline std::vector<sched_nr_cell_cfg_t> get_default_cells_cfg(
uint32_t nof_sectors,
const srsran::phy_cfg_nr_t& phy_cfg = srsran::phy_cfg_nr_default_t{srsran::phy_cfg_nr_default_t::reference_cfg_t{}})
{
std::vector<sched_nr_interface::cell_cfg_t> cells;
std::vector<sched_nr_cell_cfg_t> cells;
cells.reserve(nof_sectors);
for (uint32_t i = 0; i < nof_sectors; ++i) {
cells.push_back(get_default_cell_cfg(phy_cfg));
@ -117,11 +124,11 @@ inline sched_nr_interface::ue_cfg_t get_default_ue_cfg(
return uecfg;
}
inline sched_nr_interface::cell_cfg_t get_default_sa_cell_cfg_common()
inline sched_nr_cell_cfg_t get_default_sa_cell_cfg_common()
{
srsran::phy_cfg_nr_default_t::reference_cfg_t ref;
ref.duplex = srsran::phy_cfg_nr_default_t::reference_cfg_t::R_DUPLEX_FDD;
sched_nr_interface::cell_cfg_t cell_cfg = get_default_cell_cfg(srsran::phy_cfg_nr_default_t{ref});
sched_nr_cell_cfg_t cell_cfg = get_default_cell_cfg(srsran::phy_cfg_nr_default_t{ref});
cell_cfg.bwps[0].pdcch.coreset_present[0] = true;
cell_cfg.bwps[0].pdcch.coreset[0] = get_default_coreset0(52);
cell_cfg.bwps[0].pdcch.coreset[0].offset_rb = 1;

7
srsgnb/src/stack/mac/test/sched_nr_common_test.cc
Unescape Escape View File

@ -83,12 +83,11 @@ void test_pdcch_collisions(const srsran_pdcch_cfg_nr_t& pdcch_cfg,
}
}
void test_dl_pdcch_consistency(const sched_nr_interface::cell_cfg_t& cell_cfg,
srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcchs)
void test_dl_pdcch_consistency(const cell_params_t& cell_cfg, srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcchs)
{
for (const auto& pdcch : dl_pdcchs) {
TESTASSERT(pdcch.dci.bwp_id < cell_cfg.bwps.size());
const srsran_pdcch_cfg_nr_t& pdcch_cfg = cell_cfg.bwps[pdcch.dci.bwp_id].pdcch;
const srsran_pdcch_cfg_nr_t& pdcch_cfg = cell_cfg.bwps[pdcch.dci.bwp_id].cfg.pdcch;
test_dci_ctx_consistency(pdcch_cfg, pdcch.dci.ctx);
const srsran_coreset_t& coreset = pdcch_cfg.coreset[pdcch.dci.ctx.coreset_id];
@ -120,7 +119,7 @@ void test_pdsch_consistency(srsran::const_span<mac_interface_phy_nr::pdsch_t> pd
void test_ssb_scheduled_grant(
const srsran::slot_point& sl_point,
const sched_nr_interface::cell_cfg_t& cell_cfg,
const sched_nr_impl::cell_params_t& cell_cfg,
const srsran::bounded_vector<mac_interface_phy_nr::ssb_t, mac_interface_phy_nr::MAX_SSB>& ssb_list)
{
/*

4
srsgnb/src/stack/mac/test/sched_nr_common_test.h
Unescape Escape View File

@ -26,13 +26,13 @@ void test_pdcch_collisions(const srsran_pdcch_cfg_nr_t& pdcch_c
srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcchs,
srsran::const_span<sched_nr_impl::pdcch_ul_t> ul_pddchs);
void test_dl_pdcch_consistency(const sched_nr_interface::cell_cfg_t& cell_cfg,
void test_dl_pdcch_consistency(const sched_nr_impl::cell_params_t& cell_cfg,
srsran::const_span<sched_nr_impl::pdcch_dl_t> dl_pdcch);
void test_pdsch_consistency(srsran::const_span<mac_interface_phy_nr::pdsch_t> dl_pdcch);
/// @brief Test whether the SSB grant gets scheduled with the correct periodicity.
void test_ssb_scheduled_grant(
const srsran::slot_point& sl_point,
const sched_nr_interface::cell_cfg_t& cell_cfg,
const sched_nr_impl::cell_params_t& cell_cfg,
const srsran::bounded_vector<mac_interface_phy_nr::ssb_t, mac_interface_phy_nr::MAX_SSB>& ssb_list);
} // namespace srsenb

4
srsgnb/src/stack/mac/test/sched_nr_parallel_test.cc
Unescape Escape View File

@ -39,7 +39,7 @@ public:
pdsch_count += cc_out.res.dl->phy.pdcch_dl.size();
cc_res_count++;
bool is_dl_slot = srsran_duplex_nr_is_dl(&cell_params[cc_out.res.cc].cfg.duplex, 0, current_slot_tx.slot_idx());
bool is_dl_slot = srsran_duplex_nr_is_dl(&cell_params[cc_out.res.cc].duplex, 0, current_slot_tx.slot_idx());
if (is_dl_slot) {
if (cc_out.res.dl->phy.ssb.empty() and not slot_ctxt.ue_db.empty()) {
@ -73,7 +73,7 @@ void run_sched_nr_test(uint32_t nof_workers)
sched_nr_interface::sched_args_t cfg;
cfg.auto_refill_buffer = true;
std::vector<sched_nr_interface::cell_cfg_t> cells_cfg = get_default_cells_cfg(nof_sectors);
std::vector<sched_nr_cell_cfg_t> cells_cfg = get_default_cells_cfg(nof_sectors);
std::string test_name = "Serialized Test";
if (nof_workers > 1) {

20
srsgnb/src/stack/mac/test/sched_nr_pdcch_test.cc
Unescape Escape View File

@ -31,13 +31,13 @@ void test_coreset0_cfg()
srsran::test_delimit_logger delimiter{"Test PDCCH Allocation in CORESET#0"};
sched_nr_impl::cell_cfg_t cell_cfg = get_default_sa_cell_cfg_common();
sched_nr_interface::sched_args_t sched_args;
bwp_params_t bwp_params{cell_cfg, sched_args, 0, 0};
sched_nr_impl::cell_params_t cell_cfg{0, get_default_sa_cell_cfg_common(), sched_args};
bwp_params_t& bwp_params = cell_cfg.bwps[0];
// UE config
ue_cfg_manager uecfg{get_rach_ue_cfg(0)};
uecfg.phy_cfg.pdcch = cell_cfg.bwps[0].pdcch; // Starts without UE-specific PDCCH
uecfg.phy_cfg.pdcch = cell_cfg.bwps[0].cfg.pdcch; // Starts without UE-specific PDCCH
ue_carrier_params_t ue_cc{0x46, bwp_params, uecfg};
pdcch_dl_list_t dl_pdcchs;
@ -48,7 +48,7 @@ void test_coreset0_cfg()
pdcch_ul_t* ul_pdcch = nullptr;
bwp_pdcch_allocator pdcch_sched(bwp_params, 0, dl_pdcchs, ul_pdcchs);
for (const srsran_coreset_t& cs : view_active_coresets(cell_cfg.bwps[0].pdcch)) {
for (const srsran_coreset_t& cs : view_active_coresets(cell_cfg.bwps[0].cfg.pdcch)) {
// Verify nof CCEs is correctly computed
TESTASSERT_EQ(coreset_nof_cces(cs), pdcch_sched.nof_cces(cs.id));
}
@ -140,13 +140,14 @@ void test_coreset2_cfg()
srsran::test_delimit_logger delimiter{"Test PDCCH Allocation in CORESET#0 and CORESET#2"};
sched_nr_impl::cell_cfg_t cell_cfg = get_default_sa_cell_cfg_common();
sched_nr_interface::sched_args_t sched_args;
sched_nr_cell_cfg_t cell_cfg = get_default_sa_cell_cfg_common();
cell_cfg.bwps[0].pdcch.search_space_present[2] = true;
cell_cfg.bwps[0].pdcch.search_space[2] = get_default_ue_specific_search_space(2, 2);
cell_cfg.bwps[0].pdcch.coreset_present[2] = true;
cell_cfg.bwps[0].pdcch.coreset[2] = get_default_ue_specific_coreset(2, cell_cfg.carrier.pci);
sched_nr_interface::sched_args_t sched_args;
bwp_params_t bwp_params{cell_cfg, sched_args, 0, 0};
sched_nr_impl::cell_params_t cellparams{0, cell_cfg, sched_args};
bwp_params_t& bwp_params = cellparams.bwps[0];
// UE config
ue_cfg_manager uecfg{get_rach_ue_cfg(0)};
@ -230,7 +231,7 @@ void test_invalid_params()
srsran::test_delimit_logger delimiter{"Test PDCCH Allocation with Invalid Arguments"};
sched_nr_impl::cell_cfg_t cell_cfg = get_default_sa_cell_cfg_common();
sched_nr_cell_cfg_t cell_cfg = get_default_sa_cell_cfg_common();
cell_cfg.bwps[0].pdcch.search_space_present[2] = true;
cell_cfg.bwps[0].pdcch.search_space[2] = get_default_ue_specific_search_space(2, 2);
cell_cfg.bwps[0].pdcch.coreset_present[2] = true;
@ -240,7 +241,8 @@ void test_invalid_params()
cell_cfg.bwps[0].pdcch.search_space[3].nof_formats = 1; // only DL
cell_cfg.bwps[0].pdcch.search_space[3].formats[0] = srsran_dci_format_nr_1_0;
sched_nr_interface::sched_args_t sched_args;
bwp_params_t bwp_params{cell_cfg, sched_args, 0, 0};
sched_nr_impl::cell_params_t cellparams{0, cell_cfg, sched_args};
bwp_params_t& bwp_params = cellparams.bwps[0];
// UE config
ue_cfg_manager uecfg{get_rach_ue_cfg(0)};

4
srsgnb/src/stack/mac/test/sched_nr_rar_test.cc
Unescape Escape View File

@ -34,8 +34,8 @@ void test_single_prach()
sched_cfg.auto_refill_buffer = std::uniform_int_distribution<uint32_t>{0, 1}(rgen) > 0;
// Set cells configuration
std::vector<sched_nr_interface::cell_cfg_t> cells_cfg = get_default_cells_cfg(1);
sched_params_t schedparams{sched_cfg};
std::vector<sched_nr_cell_cfg_t> cells_cfg = get_default_cells_cfg(1);
sched_params_t schedparams{sched_cfg};
schedparams.cells.emplace_back(0, cells_cfg[0], sched_cfg);
const bwp_params_t& bwpparams = schedparams.cells[0].bwps[0];
slot_ue_map_t slot_ues;

55
srsgnb/src/stack/mac/test/sched_nr_sch_test.cc
Unescape Escape View File

@ -22,9 +22,9 @@ namespace srsenb {
using namespace sched_nr_impl;
sched_nr_interface::cell_cfg_t get_cell_cfg()
sched_nr_cell_cfg_t get_cell_cfg()
{
sched_nr_impl::cell_cfg_t cell_cfg = get_default_sa_cell_cfg_common();
sched_nr_cell_cfg_t cell_cfg = get_default_sa_cell_cfg_common();
cell_cfg.bwps[0].pdcch.search_space_present[2] = true;
cell_cfg.bwps[0].pdcch.search_space[2] = get_default_ue_specific_search_space(2, 2);
cell_cfg.bwps[0].pdcch.coreset_present[2] = true;
@ -32,7 +32,7 @@ sched_nr_interface::cell_cfg_t get_cell_cfg()
return cell_cfg;
}
sched_nr_interface::ue_cfg_t get_ue_cfg(const sched_nr_interface::cell_cfg_t& cell_cfg)
sched_nr_interface::ue_cfg_t get_ue_cfg(const sched_nr_cell_cfg_t& cell_cfg)
{
sched_nr_ue_cfg_t uecfg = get_rach_ue_cfg(0);
uecfg.phy_cfg = get_common_ue_phy_cfg(cell_cfg);
@ -63,7 +63,7 @@ srsran_dci_ctx_t generate_dci_ctx(const srsran_pdcch_cfg_nr_t& pdcch,
void test_dci_freq_assignment(const bwp_params_t& bwp_params, prb_interval grant, const pdcch_dl_t& pdcch)
{
// Compute BWP PRB limits
prb_interval lims{0, bwp_params.nof_prb()};
prb_interval lims{0, bwp_params.nof_prb};
if (SRSRAN_SEARCH_SPACE_IS_COMMON(pdcch.dci.ctx.ss_type) and pdcch.dci.ctx.format == srsran_dci_format_nr_1_0) {
lims = bwp_params.dci_fmt_1_0_prb_lims(pdcch.dci.ctx.coreset_id);
}
@ -86,9 +86,10 @@ void test_si()
static const uint32_t ss_id = 0;
// Create Cell and UE configs
sched_nr_impl::cell_cfg_t cell_cfg = get_cell_cfg();
sched_nr_interface::sched_args_t sched_args;
bwp_params_t bwp_params{cell_cfg, sched_args, 0, 0};
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_params_t cell_params{0, cellcfg, sched_args};
const bwp_params_t& bwp_params = cell_params.bwps[0];
pdsch_list_t pdschs;
pdsch_alloc_result alloc_res;
@ -102,7 +103,7 @@ void test_si()
uint32_t max_prb = bwp_params.dci_fmt_1_0_prb_lims(pdcch.dci.ctx.coreset_id).stop();
std::array<prb_interval, 3> grant_list = {
prb_interval{2, 4}, prb_interval{min_prb, max_prb}, prb_interval{0, bwp_params.nof_prb()}};
prb_interval{2, 4}, prb_interval{min_prb, max_prb}, prb_interval{0, bwp_params.nof_prb}};
for (uint32_t i = 0; i < grant_list.size(); ++i) {
pdsch_sched.reset();
@ -144,9 +145,9 @@ void test_rar()
static const uint32_t ss_id = 1;
// Create Cell and UE configs
sched_nr_impl::cell_cfg_t cell_cfg = get_cell_cfg();
sched_nr_interface::sched_args_t sched_args;
bwp_params_t bwp_params{cell_cfg, sched_args, 0, 0};
sched_nr_impl::cell_params_t cell_cfg{0, get_cell_cfg(), sched_args};
const bwp_params_t& bwp_params = cell_cfg.bwps[0];
pdsch_list_t pdschs;
pdsch_alloc_result alloc_res;
@ -160,7 +161,7 @@ void test_rar()
uint32_t max_prb = bwp_params.dci_fmt_1_0_prb_lims(pdcch.dci.ctx.coreset_id).stop();
std::array<prb_interval, 3> grant_list = {
prb_interval{2, 4}, prb_interval{min_prb, max_prb}, prb_interval{0, bwp_params.nof_prb()}};
prb_interval{2, 4}, prb_interval{min_prb, max_prb}, prb_interval{0, bwp_params.nof_prb}};
for (uint32_t i = 0; i < grant_list.size(); ++i) {
pdsch_sched.reset();
@ -201,10 +202,11 @@ void test_ue_pdsch()
srsran::test_delimit_logger delimiter{"Test PDSCH UE Allocation"};
// Create Cell and UE configs
sched_nr_impl::cell_cfg_t cell_cfg = get_cell_cfg();
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cell_cfg)};
sched_nr_interface::sched_args_t sched_args;
bwp_params_t bwp_params{cell_cfg, sched_args, 0, 0};
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_params_t cell_params{0, get_cell_cfg(), sched_args};
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cellcfg)};
const bwp_params_t& bwp_params = cell_params.bwps[0];
ue_carrier_params_t ue_cc{0x4601, bwp_params, uecfg};
pdsch_list_t pdschs;
@ -217,7 +219,7 @@ void test_ue_pdsch()
pdcch_ue.dci.ctx = generate_dci_ctx(bwp_params.cfg.pdcch, 2, srsran_rnti_type_c, 0x4601);
prb_interval lims_common = bwp_params.dci_fmt_1_0_prb_lims(pdcch_common.dci.ctx.coreset_id);
prb_interval lims_ue{0, bwp_params.nof_prb()};
prb_interval lims_ue{0, bwp_params.nof_prb};
std::array<std::pair<uint32_t, prb_interval>, 4> grant_list = {std::make_pair(1, prb_interval{2, 4}),
std::make_pair(1, lims_common),
@ -268,10 +270,11 @@ void test_pdsch_fail()
srsran::test_delimit_logger delimiter{"Test PDSCH Allocation Failure"};
// Create Cell and UE configs
sched_nr_impl::cell_cfg_t cell_cfg = get_cell_cfg();
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cell_cfg)};
sched_nr_interface::sched_args_t sched_args;
bwp_params_t bwp_params{cell_cfg, sched_args, 0, 0};
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_params_t cell_params{0, cellcfg, sched_args};
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cellcfg)};
const bwp_params_t& bwp_params = cell_params.bwps[0];
ue_carrier_params_t ue_cc{0x4601, bwp_params, uecfg};
pdsch_list_t pdschs;
@ -304,7 +307,7 @@ void test_pdsch_fail()
// Allocations of DCI format 1_0 should start from CORESET first RB and their BW should be limited by CORESET#0 BW
prb_grant grant_type1 = prb_interval{0, bwp_params.coreset_prb_range(0).stop()};
TESTASSERT(pdsch_sched.alloc_ue_pdsch(1, srsran_dci_format_nr_1_0, grant_type1, ue_cc, pdcch.dci).is_error());
grant_type1 = prb_interval{bwp_params.coreset_prb_range(0).start(), bwp_params.nof_prb()};
grant_type1 = prb_interval{bwp_params.coreset_prb_range(0).start(), bwp_params.nof_prb};
TESTASSERT(pdsch_sched.alloc_ue_pdsch(1, srsran_dci_format_nr_1_0, grant_type1, ue_cc, pdcch.dci).is_error());
TESTASSERT(pdsch_sched.alloc_ue_pdsch(2, srsran_dci_format_nr_1_0, grant_type1, ue_cc, pdcch.dci).has_value());
@ -317,10 +320,11 @@ void test_multi_pdsch()
srsran::test_delimit_logger delimiter{"Test Multiple PDSCH Allocations"};
// Create Cell and UE configs
sched_nr_impl::cell_cfg_t cell_cfg = get_cell_cfg();
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cell_cfg)};
sched_nr_interface::sched_args_t sched_args;
bwp_params_t bwp_params{cell_cfg, sched_args, 0, 0};
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_params_t cell_params{0, cellcfg, sched_args};
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cellcfg)};
const bwp_params_t& bwp_params = cell_params.bwps[0];
ue_carrier_params_t ue_cc{0x4601, bwp_params, uecfg};
ue_carrier_params_t ue_cc2{0x4602, bwp_params, uecfg};
@ -380,7 +384,7 @@ void test_multi_pdsch()
pdcch = &pdcch_ue;
used_prbs = pdsch_sched.occupied_prbs(ss_id, srsran_dci_format_nr_1_0);
prb_interval ue_grant2 = find_empty_interval_of_length(used_prbs, used_prbs_ue.size(), 0);
TESTASSERT_EQ(bwp_params.nof_prb(), ue_grant2.stop());
TESTASSERT_EQ(bwp_params.nof_prb, ue_grant2.stop());
TESTASSERT_EQ(alloc_result::success,
pdsch_sched.is_ue_grant_valid(ue_cc, ss_id, srsran_dci_format_nr_1_0, ue_grant2));
alloc_res = pdsch_sched.alloc_ue_pdsch(ss_id, srsran_dci_format_nr_1_0, ue_grant2, ue_cc, pdcch->dci);
@ -408,10 +412,11 @@ void test_multi_pusch()
srsran::test_delimit_logger delimiter{"Test Multiple PUSCH Allocations"};
// Create Cell and UE configs
sched_nr_impl::cell_cfg_t cell_cfg = get_cell_cfg();
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cell_cfg)};
sched_nr_interface::sched_args_t sched_args;
bwp_params_t bwp_params{cell_cfg, sched_args, 0, 0};
sched_nr_cell_cfg_t cellcfg = get_cell_cfg();
sched_nr_impl::cell_params_t cell_params{0, cellcfg, sched_args};
sched_nr_impl::ue_cfg_manager uecfg{get_ue_cfg(cellcfg)};
const bwp_params_t& bwp_params = cell_params.bwps[0];
ue_carrier_params_t ue_cc{0x4601, bwp_params, uecfg};
ue_carrier_params_t ue_cc2{0x4602, bwp_params, uecfg};

12
srsgnb/src/stack/mac/test/sched_nr_sim_ue.cc
Unescape Escape View File

@ -154,10 +154,10 @@ void sched_nr_ue_sim::update_dl_harqs(const sched_nr_cc_result_view& cc_out)
}
}
sched_nr_base_test_bench::sched_nr_base_test_bench(const sched_nr_interface::sched_args_t& sched_args,
const std::vector<sched_nr_interface::cell_cfg_t>& cell_cfg_list,
std::string test_name_,
uint32_t nof_workers) :
sched_nr_base_test_bench::sched_nr_base_test_bench(const sched_nr_interface::sched_args_t& sched_args,
const std::vector<sched_nr_cell_cfg_t>& cell_cfg_list,
std::string test_name_,
uint32_t nof_workers) :
logger(srslog::fetch_basic_logger("TEST")),
mac_logger(srslog::fetch_basic_logger("MAC-NR")),
sched_ptr(new sched_nr()),
@ -312,9 +312,9 @@ void sched_nr_base_test_bench::process_results()
sched_nr_cc_result_view cc_out = cc_results[cc].res;
// Run common tests
test_dl_pdcch_consistency(cell_params[cc].cfg, cc_out.dl->phy.pdcch_dl);
test_dl_pdcch_consistency(cell_params[cc], cc_out.dl->phy.pdcch_dl);
test_pdsch_consistency(cc_out.dl->phy.pdsch);
test_ssb_scheduled_grant(cc_out.slot, cell_params[cc_out.cc].cfg, cc_out.dl->phy.ssb);
test_ssb_scheduled_grant(cc_out.slot, cell_params[cc_out.cc], cc_out.dl->phy.ssb);
// Run UE-dedicated tests
test_dl_sched_result(slot_ctxt, cc_out);

8
srsgnb/src/stack/mac/test/sched_nr_sim_ue.h
Unescape Escape View File

@ -112,10 +112,10 @@ public:
std::chrono::nanoseconds cc_latency_ns;
};
sched_nr_base_test_bench(const sched_nr_interface::sched_args_t& sched_args,
const std::vector<sched_nr_interface::cell_cfg_t>& cell_params_,
std::string test_name,
uint32_t nof_workers = 1);
sched_nr_base_test_bench(const sched_nr_interface::sched_args_t& sched_args,
const std::vector<sched_nr_cell_cfg_t>& cell_params_,
std::string test_name,
uint32_t nof_workers = 1);
virtual ~sched_nr_base_test_bench();
void run_slot(slot_point slot_tx);

16
srsgnb/src/stack/mac/test/sched_nr_test.cc
Unescape Escape View File

@ -33,10 +33,10 @@ class sched_tester : public sched_nr_base_test_bench
sim_args_t args;
public:
explicit sched_tester(sim_args_t args_,
const sched_nr_interface::sched_args_t& sched_args,
const std::vector<sched_nr_interface::cell_cfg_t>& cell_params_,
std::string test_name) :
explicit sched_tester(sim_args_t args_,
const sched_nr_interface::sched_args_t& sched_args,
const std::vector<sched_nr_cell_cfg_t>& cell_params_,
std::string test_name) :
sched_nr_base_test_bench(sched_args, cell_params_, test_name), args(args_)
{}
@ -123,8 +123,8 @@ void test_sched_nr_no_data(sim_args_t args)
uint16_t rnti = 0x4601;
sched_nr_interface::sched_args_t cfg;
cfg.auto_refill_buffer = false;
std::vector<sched_nr_interface::cell_cfg_t> cells_cfg = get_default_cells_cfg(nof_sectors);
cfg.auto_refill_buffer = false;
std::vector<sched_nr_cell_cfg_t> cells_cfg = get_default_cells_cfg(nof_sectors);
std::string test_name = "Test with no data";
sched_tester tester(args, cfg, cells_cfg, test_name);
@ -165,8 +165,8 @@ void test_sched_nr_data(sim_args_t args)
uint32_t nof_dl_bytes_to_tx = 2e6;
sched_nr_interface::sched_args_t cfg;
cfg.auto_refill_buffer = false;
std::vector<sched_nr_interface::cell_cfg_t> cells_cfg = get_default_cells_cfg(nof_sectors);
cfg.auto_refill_buffer = false;
std::vector<sched_nr_cell_cfg_t> cells_cfg = get_default_cells_cfg(nof_sectors);
std::string test_name = "Test with data";
sched_tester tester(args, cfg, cells_cfg, test_name);

19
srsgnb/src/stack/rrc/rrc_nr.cc
Unescape Escape View File

@ -299,9 +299,8 @@ void rrc_nr::config_mac()
ref_args.duplex = cfg.cell_list[0].duplex_mode == SRSRAN_DUPLEX_MODE_TDD
? srsran::phy_cfg_nr_default_t::reference_cfg_t::R_DUPLEX_TDD_CUSTOM_6_4
: srsran::phy_cfg_nr_default_t::reference_cfg_t::R_DUPLEX_FDD;
std::vector<sched_nr_interface::cell_cfg_t> sched_cells_cfg(
1, get_default_cell_cfg(srsran::phy_cfg_nr_default_t{ref_args}));
sched_nr_interface::cell_cfg_t& cell = sched_cells_cfg[0];
std::vector<sched_nr_cell_cfg_t> sched_cells_cfg(1, get_default_cell_cfg(srsran::phy_cfg_nr_default_t{ref_args}));
sched_nr_cell_cfg_t& cell = sched_cells_cfg[0];
// Derive cell config from rrc_nr_cfg_t
cell.bwps[0].pdcch = cfg.cell_list[0].phy_cell.pdcch;
@ -311,17 +310,23 @@ void rrc_nr::config_mac()
cell.ssb.position_in_burst[0] = true;
cell.ssb.scs = cfg.cell_list[0].ssb_cfg.scs;
cell.ssb.pattern = cfg.cell_list[0].ssb_cfg.pattern;
cell.duplex.mode = SRSRAN_DUPLEX_MODE_FDD;
if (not cfg.is_standalone) {
// Derive cell config from ASN1
valid_cfg = srsran::make_pdsch_cfg_from_serv_cell(base_sp_cell_cfg.sp_cell_cfg_ded, &cell.bwps[0].pdsch);
srsran_assert(valid_cfg, "Invalid NR cell configuration.");
valid_cfg =
srsran::make_duplex_cfg_from_serv_cell(base_sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common, &cell.duplex);
srsran_assert(valid_cfg, "Invalid NR cell configuration.");
if (base_sp_cell_cfg.sp_cell_cfg_ded.tdd_ul_dl_cfg_ded_present) {
cell.tdd_ul_dl_cfg_common.reset(
new tdd_ul_dl_cfg_common_s{base_sp_cell_cfg.recfg_with_sync.sp_cell_cfg_common.tdd_ul_dl_cfg_common});
}
} else {
cell.bwps[0].pdsch.p_zp_csi_rs_set = {};
bzero(cell.bwps[0].pdsch.nzp_csi_rs_sets, sizeof(cell.bwps[0].pdsch.nzp_csi_rs_sets));
cell.dl_cfg_common.reset(new dl_cfg_common_sib_s{cell_ctxt->sib1.serving_cell_cfg_common.dl_cfg_common});
cell.ul_cfg_common.reset(new ul_cfg_common_sib_s{cell_ctxt->sib1.serving_cell_cfg_common.ul_cfg_common});
if (cell_ctxt->sib1.serving_cell_cfg_common.tdd_ul_dl_cfg_common_present) {
cell.tdd_ul_dl_cfg_common.reset(
new tdd_ul_dl_cfg_common_s{cell_ctxt->sib1.serving_cell_cfg_common.tdd_ul_dl_cfg_common});
}
}
// Set SIB1 and SI messages

2
srsgnb/src/stack/rrc/test/rrc_nr_test.cc
Unescape Escape View File

@ -68,7 +68,7 @@ void test_sib_generation()
rrc_obj.init(rrc_cfg_nr, &phy_obj, &mac_obj, &rlc_obj, &pdcp_obj, nullptr, nullptr, bearer_mapper, nullptr) ==
SRSRAN_SUCCESS);
const sched_nr_interface::cell_cfg_t& nrcell = mac_obj.nr_cells.at(0);
const sched_nr_cell_cfg_t& nrcell = mac_obj.nr_cells.at(0);
TESTASSERT(nrcell.sibs.size() > 0);

2
test/phy/dummy_gnb_stack.h
Unescape Escape View File

@ -374,7 +374,7 @@ public:
mac_args.sched_cfg.fixed_dl_mcs = args.pdsch.mcs;
mac_args.sched_cfg.fixed_ul_mcs = args.pusch.mcs;
mac->init(mac_args, nullptr, nullptr, &rlc_obj, &rrc_obj);
std::vector<srsenb::sched_nr_interface::cell_cfg_t> cells_cfg = srsenb::get_default_cells_cfg(1, phy_cfg);
std::vector<srsenb::sched_nr_cell_cfg_t> cells_cfg = srsenb::get_default_cells_cfg(1, phy_cfg);
mac->cell_cfg(cells_cfg);
dl.mcs = args.pdsch.mcs;

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